Scheduling is one of the most important issues in the planning of manufacturing systems. This research focuses on solving the test scheduling problem which arises in semiconductor manufacturing environment. Semiconductor wafer devices undergo a series of test processes conducted on computer-controlled test stations at various temperatures. A test process consists of both setup operations and processing operations on the test stations. The test operations occur in a specified order on the wafer devices, resulting in precedence constraints for the schedule. Furthermore, the assignment of the wafer devices to test stations and the sequence in which they are processed affects the time required to finish the test operations, resulting in sequence dependent setup times. The goal of this research is to develop a realistic model of the semiconductor wafer test scheduling problem and provide heuristics for scheduling the precedence constrained test operations with sequence dependent setup times. A mathematical model is presented and two heuristics are developed to solve the scheduling problem with the objective of minimizing the makespan required to test all wafer devices on a set of test stations. The heuristic approaches generate a sorted list of wafer devices as a dispatching sequence and then schedule the wafer lots on test stations in order of appearance on the list. An experimental analysis and two case studies are presented to validate the proposed solution approaches. In the two case studies, the heuristics are applied to actual data from a semiconductor manufacturing facility. The results of the heuristic approaches are compared to the actual schedule executed in the manufacturing facility. For both the case studies, the proposed solution approaches decreased the makespan by 23-45% compared to the makespan of actual schedule executed in the manufacturing facility. The solution approach developed in this research can be integrated with the planning software of a semiconductor manufacturing facility to improve productivity. / Master of Science

Direct wafer bonding has been identified as an en-abling technology for microelectromechanical systems (MEMS). As the complexity of devices increase and the bonding of multiple patterned wafers is required, there is a need to understand the factors that lead to bonding failure. Bonding relies on short-ranged surface forces, thus flatness deviations of the wafers may prevent bonding. Bonding success is determined by whether or not the surface forces are sufficient to overcome the flatness deviations and deform the wafers to a common shape. A general bonding criterion based on this fact is developed by comparing the strain energy required to deform the wafers to the surface energy that is dissipated as the bond is formed. The bonding criterion is used to examine the case of bonding bowed wafers with etch patterns on the bonding surface. An analytical expression for the bonding criterion is developed using plate theory for the case of bowed wafers. Then, the criterion is implemented using finite element analysis, to demonstrate its use and to validate the analytical model. The results indicate that wafer thickness and curvature are important in determining bonding success and that the bonding criterion is independent of wafer diameter. Results also demonstrate that shallow etched patterns can make bonding more difficult while deep features, which penetrate through an appreciable thickness of the wafer, may facilitate bonding. Design implications of the model results are discussed in detail. Preliminary results from experiments designed to validate the model, agree with the trends seen in the model, but further work is required to achieve quantitative correlation. / Singapore-MIT Alliance (SMA)

No description available.

Wafer handling robotics are critical in semiconductor manufacturing to enable tight control of temperature, humidity, and particle contamination during processing. Closed-loop dynamic modeling during the robot design process ensures designs meet throughput and stability specifications prior to prototype hardware purchase. Dynamic models are also used in model-based control to improve performance. This thesis describes the generation and mathematical verification of a dynamic model for a three degrees-of-freedom wafer handling mechanism with one linear and two rotary axes. The dynamic plant model is integrated with motion and motor controller models, and the closed-loop performance is compared with experimental data. Models with rigid and flexible connections are compared, and the flexible connection models are shown to overall agree better with a measured step response. The simulation time increase from the addition of flexible connections can be minimized by modeling only the component stiffnesses that impact the closed-loop mechanism response. A method for selecting which elements to include based on controller bandwidth is presented and shown to significantly improve simulation times with minimal impact on model predictive performance.

Increased power densities in VLSI chips have led to a need to develop cooling methods that can cope with the increased heat produced by such chips. Currently one of the more attractive methods to meet this goal is through the use of two phase flow of a fluid as changing phase of the material allows high heat transfer rates for a low temperature change. To bring this technology to commercialisation a greater understanding of the underlying physics involved at the microscale is required as there is much debate within literature as to what occurs during two phase flow heat transfer at these scales. The work conducted as part of this thesis is a step towards improving the understanding of the mechanisms involved with this process. This thesis describes the fabrication of a novel microchannel structure, which can be used to experimentally characterise two phase heat transfer as it occurs. The final process reported for these microchannels structures provides the basis of a technology for the fabrication of microchannels with increased sensor densities. Two types of microchannel devices have been fabricated for this project. The first device of these was an array of parallel microchannels formed by the reactive ion etching (RIE) of silicon, which was then bonded with Pyrex glass. These microchannels were simple in that sensors were not integrated for local measurement. However the production of these devices incorporated fabrication techniques such as anodic bonding and inductively coupled plasma RIE that were essential to the fabrication of more complex devices. The second device built was a single microchannel that contained an integrated heater and several temperature sensors. The use of wafer bonding enabled the device to take full advantage of both bulk and surface micromachining technology as the placement of the temperature sensors on the channel floor would not be possible with conventional bulk micromachining. The initial microchannel structures demonstrated that wafer bonding could be used to fabricate novel devices, but they highlighted the difficulty of achieving strong anodic bonds due to the presence of dielectric films throughout the fusion bonded wafer stack used in the channel fabrication. To improve the performance of the device the process was optimised through the use of insitu, non-destructive test structures. These structures enabled the uniformity and strength of the bonds to be optimised through visualisation over the whole wafer surface. The integrated sensors enabled temperature measurements to be taken along the channel with a sensitivity 3.60 ΩK-1 while the integrated heater has delivered a controllable and uniform heat flux of 264 kWm-2.

This dissertation presents a series of studies related to the slurry mean residence time analysis and the pad-wafer contact characterization in Chemical Mechanical Planarization (CMP). The purpose of these studies is to further understand the fundamentals of CMP and to explore solutions to some of CMP's challenges. Mean residence time (MRT) is a widely used term that is mostly seen in classical chemical engineering reactor analysis. In a CMP process, the wafer-pad interface can be treated as a closed system reactor, and classical reactor theory can be applied to the slurry flow through the region. Slurry MRT represents the average time it takes for fresh incoming slurry to replace the existing slurry in the region bound between the pad and the wafer. Understanding the parameters that have an impact on MRT, and therefore removal rate, is critical to maintain tight specifications in the CMP process. In this dissertation, we proposed a novel slurry injection system (SIS) which efficiently introduced fresh slurry into the pad-wafer interface to reduce MRT. Results indicated that SIS exhibited lower slurry MRT and dispersion numbers but higher removal rates than the standard pad center slurry application by blocking the spent slurry and residual rinse water from re-entering the pad-wafer interface during polishing. Another study in this dissertation dealt with the effect of pad groove width on slurry MRT in the pad-wafer interface as well as slurry utilization efficiency (η). Three concentrically grooved pads with different groove widths were tested at different polishing pressures to experimentally determine the corresponding MRT using the residence time distribution (RTD) technique. Results showed that MRT and η increased significantly when the groove width increased from 300 to 600μm. On the other hand, when the groove width increased further to 900μm, MRT continued to increase while n remained constant. Results also indicated that MRT was reduced at a higher polishing pressure while η did not change significantly with pressure for all three pads. In the last study of this dissertation, the effect of pad surface micro-texture on removal rate during tungsten CMP was investigated. Two different conditioner discs ("Disc A" and "Disc B") were employed to generate different pad surface micro-textures during polishing. Results showed that "Disc B" generated consistently lower removal rates and coefficients of friction than "Disc A". To fundamentally elucidate the cause(s) of such differences, pad surface contact area and topography were analyzed using laser confocal microscopy. The comparison of the pad surface micro-texture analysis on pad surfaces conditioned by both discs indicated that "Disc A" generated a surface having a smaller abruptness (λ) and more solid contact area which resulted in a higher removal rate. In contrast, "Disc B" generated many large near-contact areas as a result of fractured and collapsed pore walls.

We report the creation of strained silicon on silicon (SSOS) substrate technology. The method uses a relaxed SiGe buffer as a template for inducing tensile strain in a Si layer, which is then bonded to another Si handle wafer. The original Si wafer and the relaxed SiGe buffer are subsequently removed, thereby transferring a strained-Si layer directly to Si substrate without intermediate SiGe or oxide layers. Complete removal of Ge from the structure was confirmed by cross-sectional transmission electron microscopy as well as secondary ion mass spectrometry. A plan-view transmission electron microscopy study of the strained-Si/Si interface reveals that the lattice-mismatch between the layers is accommodated by an orthogonal array of edge dislocations. This misfit dislocation array, which forms upon bonding, is geometrically necessary and has an average spacing of approximately 40nm, in excellent agreement with established dislocation theory. To our knowledge, this is the first study of a chemically homogeneous, yet lattice-mismatched, interface. / Singapore-MIT Alliance (SMA)

In today's semiconductor-based computer and communication technology, system performance is determined primarily by two factors, namely on-chip and off-chip operating frequency. In this dissertation, time-domain measurement-based methods that enable gigabit data transmission in both the IC and package have been proposed using Time-Domain Reflectometry (TDR) equipment. For the evaluation of the time-domain measurement-based method, a wafer level package test vehicle was designed, fabricated and characterized using the proposed measurement-based methods. Electrical issues associated with gigabit data transmission using the wafer-level package test vehicle were investigated. The test vehicle consisted of two board transmission lines, one silicon transmission line, and solder bumps with 50um diameter and 100um pitch. In this dissertation, 1) the frequency-dependent characteristic impedance and propagation constant of the transmission lines were extracted from TDR measurements. 2) Non-physical RLGC models for transmission lines were developed from the transient behavior for the simulation of the extracted characteristic impedance and propagation constant. 3) the solder bumps with 50um diameter and 100um pitch were analytically modeled. Then, the effect of the assembled wafer-level package, silicon substrate and board material, and material interfaces on gigabit data transmission were discussed using the wafer-level package test vehicle. Finally, design recommendations for the wafer-level package on integrated board were proposed for gigabit data transmission in both the IC and package.

No description available.

According to the fast development of portable electronic devices, their characteristics are inclined to miniature profile and lightweight. Nowadays, the wafer-level package (WLP) has been widely applied in portable electronic devices for its miniature profile and lightweight. It will become the mainstream trend later soon. The normal use of portable electronic devices brings low-frequency random vibrations to the electronic packages inside. Because of the increasing demand of these devices, the reliability of electronic packages subjected to repeated mechanical loads has become an important issue in the contemporary electronic packaging industry. In this paper both numerical and experimental studies were carried out to investigate the reliability life of Ultra-CSP under cyclic bending conditions. We perform four-point cyclic bending with various combinations of amplitudes and frequencies. Then, we do failure analysis in Ultra-CSP by observing the failure modes. A finite element model for the package is built up for dynamic as well as quasi-static analyses. Accumulated plastic work per bending cycle within the critical solder ball were calculated and together with the experimental results the parameters for the Coffin-Manson fatigue equation were fitted. Through finite element analysis we find that the solder ball which located in the corner has higher accumulated plastic work. Therefore, the crack in the solder ball grew more easily. Thus it lets package resistance rise to determine failure. It was observed from the bending experiments that the influence of frequencies on the fatigue life of the solder interconnects is inapparent. However, influence of amplitude is significant. From the results of both experiments and FEA, it was found that for this particular ultra-CSP specimen under cyclic bending conditions, the characteristic life was expressed as