Recently there has been an increased focus on the use of microfluidics for the synthesis of different products. One of the products proposed for synthesis is quantum dots. Microfluidics often uses Polydimethylsiloxane for structure in microfluidic chips, but quantum dots use octadecene in several synthesis steps. The purpose of this work was to create a lab setup capable of anodically bonding 4” diameter wafers, and to characterize the bond formed using the Plaza test chip so that microfluidic devices using glass and silicon as substrates could be created. Two stainless steel electrodes placed on top of a hot plate were attached to a high power voltage supply to perform anodic bonding. A Plaza test mask was created and used to pattern P type silicon wafers. The channels etched were between 300 and 500nm deep and ranged between 1000µm and 50µm. These wafers were then anodically bonded to Corning 7740 glass wafers. Bonding stopped once the entire surface of the wafer was bonded, determined by visual inspection. All bonds were formed at 400°C and the bond strength and toughness between wafers bonded at 400V and 700V was compared. A beam model was used to predict the interfacial fracture toughness, and the stress at the bond was calculated with a parallel spring model. By measuring the crack length of the test structures under a light microscope the load conditions of the beam could be found. It was concluded that the electrostatic forces between the wafers give the best indication of what the bond quality will be. This was seen by the large difference in crack length between samples that were bonded using a thick glass wafer (1 mm) and a thin glass wafer (500µm). The observed crack lengths for the thick glass wafers were between 40 and 60µm. Thin glass wafers had a crack length between 20 and 40µm. The fracture toughness was calculated using the beam model approximation. Fracture toughness of the thin glass wafers was 7MPa m1/2, and of the thick glass wafers was 30 MPa m1/2. The fracture toughness of the thick glass wafers agreed with results found through the use of the double cantilever beam samples in literature. The maximum observed interfacial stress was 70 MPa. Finally, to measure the change in the size of the sodium depletion zone formed during bonding, samples were placed under a scanning electron microscope (SEM). Depletion zones were found to be between 1.1 and 1.4µm for thin glass samples that were bonded at 400 and 700 volts. This difference was not found to have a significant effect on the strength or fracture toughness observed. Thicker glass samples could not have their depletion zone measured due to SEM chuck size.

In der vorliegenden Arbeit wurden experimentelle Untersuchungen zu Material begrenzenden Einflüssen beim Multidrahtsägen von Silicium unter Verwendung gerader und strukturierter Drähte durchgeführt. Ziel dieser Arbeit war es, den Einfluss von dünnen und strukturierten Drähten auf den Drahtsägeprozess von Silicium und die erzeugten Waferqualitäten zu untersuchen. Zusätzlich galt es, Grenzen und Potentiale für den Einsatz dieser Drähte im Sägeprozess aufzuzeigen und ein Modell zu entwickeln, das den Materialabtrag in Silicium für strukturierte Drähte beschreibt. Die in dieser Arbeit verfolgten Lösungsansätze beinhalten im ersten Teil der Arbeit die Durchführung von Sägeexperimenten mit einer Eindrahtsäge. Es wurden dünne Drähte mit Durchmesser ≤ 100 µm und zwei unterschiedliche Siliciumcarbid (SiC) Korngrößenverteilungen untersucht. Zusätzlich wurden die Normalkräfte in Vorschubrichtung variiert. Im zweiten Teil der Arbeit werden Sägeexperimente mit einer Multidrahtsäge vorgestellt. Es wurden zwei unterschiedlich strukturierte Drähte mit variierten Drahtgeschwindigkeiten und Vorschüben im Vergleich zu geradem Draht untersucht. Der industrielle Einsatz dünner Drähte im Sägeprozess zur Reduzierung des Sägeverschnitts ist derzeit auf Durchmesser von 100 µm begrenzt. Die getesteten Drähte mit geringerem Durchmesser sind nicht wirtschaftlich einsetzbar, da sie zu geringe Standzeiten aufweisen und zu einer Slurryverarmung beitragen können. Es konnte eine Slurryverarmung des Schnittspalts in Silicium beobachtet werden, die um mehrere Zentimeter in den Schnittspalt ragt und dadurch den Drahtsägeprozess negativ beeinflusst, indem Sägeriefen entstehen. Die Verschleißuntersuchungen von Sägedrähten zeigen, dass eine lineare Abnahme der Drahtdurchmesserreduzierung in Abhängigkeit der akkumulierten Eingriffslänge in Silicium auftritt. Der Prozess der Durchmesserreduzierung wird maßgeblich durch die aufgebrachte Normalkraft, welche durch die Zugfestigkeit und Härte des Drahts beeinflusst wird, die Drahtgeschwindigkeit und die verwendete Korngrößenverteilung bestimmt. Es konnte durch Sägeversuche mit Drähten unterschiedlicher Hersteller gezeigt werden, dass das beobachtete Verschleißverhalten nicht einem Drahthersteller zuordenbar ist, sondern eine globalere Gültigkeit besitzt. Der industrielle Einsatz strukturierter Drähte wirkt sich positiv auf den Sägeprozess aus. Es konnten signifikant höhere Vorschübe bei ähnlichen Kräften im Vergleich zu geraden Drähten erreicht werden. Für einen Vorschub von 0,6 mm/min sind die Kraftwerte für strukturierten Draht A im Vergleich zu geradem Draht um 40% reduziert, für Draht B um 16%. Durch die Drahtstruktur wird ein größeres Slurryvolumen durch den Schnittspalt befördert, was zu einem homogeneren Materialabtrag entlang des Schnittspalts führt. Die erhöhten Vorschübe konnten sowohl für mono- wie auch für multikristallines Siliciummaterial erreicht werden. Zusätzlich wurden homogenere Waferdicken durch den Einsatz strukturierter Drähte beim Sägeprozess erzeugt. Auf Basis der Ergebnisse für strukturierte Drähte wurde ein theoretisches Modell für den Materialabtrag entwickelt, welches die in dieser Arbeit durchgeführten Experimente gut beschreibt. / In the present work experimental analyses were carried out to investigate the material limiting influences in the multi wire sawing process of silicon while using thin and structured wires. The purpose of the work was to investigate influences on the wire sawing process and the resulting wafer qualities caused by thin and structured wires. Additionally, the purpose was to define the limits and potentials of thin and structured wires in industrial wire sawing processes and to develop a model which describes the material removal in silicon for structured wires. Experiments with two different SiC particle size distributions in combination with wire diameters of ≤ 100 µm and varying normal forces in feed direction were carried out in the first part of this work with a single wire saw. Experiments with two differently structured wires and variation of the wire speed and feed rate are shown in the second part using a multi wire saw. The actual limit for industrial sawing applications to reduce kerf loss is reached for 100 µm thin wire diameters. The tested lower wire diameters are uneconomical due to shorter durability and to aggravate slurry depletion effects. Such a depletion effect of several centimeters length which is detrimental for the wire sawing process was observed at the end of a sawing channel. The results of the experiments showed that the steel wire diameter is reduced linearly with the accumulated sawn length of silicon. The material removal process of the steel wire is significantly influenced by the normal force in feed direction and the hardness of the wire. The experiments with wires of different suppliers showed no difference in the material removal process. Therefore the abrasive wear of wires has a more global validation. The results of the experiments using differently structured wires showed that significantly lower forces in feed direction occur for a given feed rate in comparison to straight wires. The forces are reduced up to 40% for structured wire A and up to 16% for wire B for a feed rate of 0,6 mm/min. A higher slurry volume is transported due to the structure of the wire which enables a more homogeneous material removal process along the cutting channel. Higher feed rates were reached for mono- and multi crystalline silicon material. Additionally, more homogeneous wafer thicknesses were cut using structured wires.

L'objectif de cette thèse est d'établir les liens entre élaboration, microstructure et comportement des getters non-évaporables (NEG) en couches minces, en vue de leur utilisation dans le cadre du packaging collectif des MEMS sous vide ou sous atmosphère contrôlée. Après une étude bibliographique sur l'herméticité des MEMS et l'effet getter, la modification du comportement de piégeage de gaz par les NEG couches minces, engendré par l'ajout de sous-couches métalliques, est mise en évidence. Afin d'expliquer cette influence, la microstructure des couches minces est étudiée, notamment sa dépendance aux paramètres d'élaboration et aux traitements thermiques. Ensuite, le comportement macroscopique de piégeage de l'azote est caractérisé, de même que les mécanismes microscopiques d'activation et de pompage. Ces derniers permettent finalement d'élaborer quelques recommandations pour l'intégration des NEG couches minces dans les MEMS. / Whilst satisfying low-cost requirements, performances and lifetime of many MEMS can be enhanced by performing wafer-level packaging of devices under vacuum or controlled atmosphere conditions. However, this implies the use of non-evaporable getters (NEG) inside MEMS cavities for residual gases removal. Relationships between elaboration, microstructure and pumping behavior of NEG thin films are investigated in this thesis. After a literature review on MEMS hermetic sealing and getter effect, NEG thin films pumping behavior modification by metallic sub-layers addition is presented. Then, in order to explain this modification, elaboration parameters and thermal treatments influence on thin films microstructure is analyzed. Lastly, nitrogen gettering behavior of NEG is characterized, as well as activation and pumping mechanisms. From these results, some recommendations for NEG thin films integration in MEMS are finally proposed.

Depuis l'invention du transistor dans les années 50, les performances des composants microélectroniques n'ont cessé de progresser, en passant notamment par l'augmentation de leur densité. Malheureusement, la miniaturisation des composants augmente les coûts de fabrication de façon prohibitive. Une solution, permettant d'accroître la densification et les fonctionnalités tout en limitant les coûts, passe par l'empilement des composants microélectroniques. Leurs connexions électriques s'effectuent alors à l'aide d'interconnexions verticales soudées au moyen d'un joint de brasure. Afin d'empêcher leurs ruptures lors des dilatations thermiques, les interconnexions sont protégées au moyen d'un polymère underfill. L'objectif de cette thèse est d'évaluer la faisabilité et la pertinence d'une nouvelle solution de remplissage par polymère, appelée wafer-level underfill (WLUF). L'écoulement de l'underfill durant l'étape d'assemblage des composants est modélisé afin de prédire les paramètres de scellement idéaux, permettant la formation des interconnexions électriques. Puis, l'intégration de nouveaux underfills, possédant des propriétés thermomécaniques différentes, pouvant affecter l'intégrité et le fonctionnement du dispositif, l'étude de la fiabilité du procédé WLUF et, par conséquent, l'évaluation de sa possibilité d'industrialisation est effectuée. / Since the invention of the transistor in the Fifties, performances of microelectronics components did not cease progressing thanks to their density increase. Unfortunately, miniaturization of components increases manufacturing costs in a prohibitory way. A solution, allowing densification and functionalization increase without costs rise, is microelectronics components stack. Their electrical connections are carried out using vertical interconnections welded by means of solder joints. In order to prevent their ruptures during thermal dilatations, interconnections are protected thanks to polymer underfill. The objective of this thesis is to evaluate the feasibility and the relevance of a new solution of polymer filling, called wafer-level underfill (WLUF). Flow of underfill during components assembly step is modeled in order to predict ideal bonding parameters, allowing electrical interconnections formation. Then, integration of new underfills, having different thermomechanical properties, being able to affect device integrity and functioning, the study of WLUF process reliability and, consequently, the evaluation of its industrialization possibility is carried out.

Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung List of symbols and abbreviations Acknowledgement 1. Introduction 2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias 3. Fabrication of BiCMOS & Silicon Interposer with TSVs 4. Characterization of BiCMOS Embedded Through-Silicon Vias 5. Applications 6. Conclusion and Future Work 7. Appendix 8. Publications & Patents 9. Bibliography 10. List of Figures and Tables

Since 1970s, ever growing attention has been devoted by worldwide researchers and practitioners to the investigation of job release control. However, the need for control of flow of job/wafer into the wafer fabrication system is identified in the late 1988s. Subsequently, many release policies are developed and presented in the literature for improving its performance with respect to cycle time and throughput. Even though it is pointed out in the literature that there is a need for the development and analysis of policy that control the flow of job/wafer through the manufacturing process, still there is no exhaustive study in view of the previously developed release policies in the literature. Moreover, many new opportunities have evolved in the field of release policy in wafer fabrication industry due to the advancement in technology and computer science. It implies that near real-time decision making for efficient release policy is possible based on the global factory state. However, it appears from the literature that still to date the release policies, which are employed in real wafer fabrication system, are usually based on the static information. Release control/policy is emerging as an important research topic in the wafer fabrication industry given the extremely large capital investment and sales revenue of this industry. Release policy also hold practical significance for manufacturing managers, since neglecting it can lead to wide variations in shop workloads, can cause excessive backlogs, accomplishment of orders will be either too early or too late and there can be frequent need for expediting. All the challenges associated with the performance of the wafer fabrication system discussed here and the puzzle around the release policies and its impact on the wafer fabrication process, this research attempts to investigate existing release policies and proposing a few efficient release policies based on the knowledge gained from the existing release policies strength and weakness. Based on the insights gained from the existing release policies, three new closed loop release policies constant workload (CONSTWL), constant batch machine workload (CONSTBWL) and layer wise control (LWC) are developed by considering the parameters: workload in general, workload in batch machine, and re-entrant characteristics of the wafer fabrication system respectively. The conceptual significance in favour of these proposed closed loop release policies in improving performance of the wafer fabrication system is also outlined in this study. In the literature, few researchers clearly indicate that dispatching rule(s) influence the performance of wafer fabrication system either independently or in integration with release policies. Therefore, to empirically validate this fact, release policy is integrated with dispatching rule particularly applying on bottleneck (discrete processing machine) work station in this study. With these, the aims of proposed release policies are to efficiently improve the system performances in terms of average cycle time, standard deviation of cycle time and throughput. Accordingly, a simulation model is proposed and developed using Arena software for evaluating the performance of release policies in integration with dispatching rule applied on bottleneck work station in wafer fabrication environment. Further, to set the values of parameters in the simulation model, the cause and effect analysis is explored in this study by considering eight critical parameters or factors of the simulated wafer fabrication environment. It includes arrival rate, arrival distribution, processing time, maintenance schedule, operator’s schedule, batch size, dispatching rule and release policy. Simulation based cause and effect analysis not only helps in setting up the values of parameters in the proposed simulation model, but it also helps in strengthening the face validity of the developed simulation model. The verification and validation of the developed simulation model, which is a vital and fundamental aspect of simulation is discussed in detail in this study. Based on the analysis and the results observed from the cause and effect analysis, some modifications are incorporated and subsequently, the parameters values are set in the proposed simulation model for evaluating the performance of release policies integrating with dispatching rules. A series of simulation experiments are conducted using the proposed simulation model with systems conditions such as product mix, complexity of the process, level of machine unreliability, and system congestion level to study the relative effects of each of 18 release policies (one open loop release policy, 14 existing closed loop release policies, and 3 proposed release policies) in integration with dispatching rules (FIFO, LIFO and SRPT), considered in this study, at various throughput levels in the wafer fabrication environment. Particularly, the relative effect of integrating release policies and the dispatching rules are observed and analysed in terms of (a) the effect of dispatching rule on release policy, and (b) the effects of release policies on dispatching rules. It is observed from the overall inferences that dispatching rule: SRPT outperformed both FIFO and LIFO dispatching rule for all the considered release policies, except for the release policy: ‘TOTAL_CT’. Additionally, it is observed that for each of the eighteen release policies integrated with considered, the dispatching rule: SRPT produces less WIP inventory at the bottleneck work station for all throughput levels. The maximum deviation in delay (cycle time) is produced by dispatching rule: LIFO in all the release policies considered except for the release policy: ‘TOTAL_CT’ in which dispatching rule: SRPT produces maximum deviation in delay. Moreover, it is observed that the difference in mean delay with all three dispatching rules (FIFO, LIFO and SRPT) increases with the increase in throughput levels. Furthermore, it is observed that the throughput rate under all release policies (except ‘TOTAL_CT’) is more for dispatching rule: SRPT in comparison with both dispatching rules: FIFO and LIFO for nearly the same threshold values. The experimental results showed that proposed release policy: LWC reliably improves the system performance followed by the proposed release policy: CONSTWL and CONSTBWL with respect to both mean delay and standard deviation for corresponding throughput levels in wafer fabrication system. The characteristics of the proposed release policy: LWC are summarized and the same is presented as follows because this is proven to be best release policy among all the release policies considered in the proposed simulation model. The proposed release policy: LWC is a new measure of the work quantity on the shop floor system, which takes into account the location of jobs/wafers along the production line by employing re-entrant property of wafer fabrication system. As a result, it offers quick response to the stochastic events of the manufacturing system and can compensated the system disturbances in time. The proposed release policy: LWC offers more efficient control of flow of job/wafer in the wafer fabrication system with reduced delay (cycle time) and the standard deviation of delay (cycle time) for a given throughput level in comparison with almost all the release policies considered in this study in integration with all three dispatching rules considered and applied on bottleneck work station. For instance, from the analysis of simulation model, the proposed release policy: LWC reduces the average delay up to 98%, 95%, 90%, 89%, 49%, 35%, 21%, 17%, 13%, 12%, 10%, 9%, 9%, 9%, 6% and 4%, and reduces the standard deviation of delay up to 96%, 98%, 94%, 93%, 34%, 22%, 4%, 13%, 11%, 6%, 9%, 14%, 4%, 4%, 10% and 7% for a given throughput level, respectively in relation to other release polices: FRCP, EWIP, TOTAL_CT, PWR, EWC, DRCP, CONLOAD, WIPLCtrl, Droll, DEC, CONWIP, SA, RCONWIP, WR, CONSTBWL and CONSTWL respectively in integration with dispatching rule: SRPT. These improvements can also be understood from another aspect, that is, LWC can increase the system throughput rate for a given cycle time. The improvement is statistically significant according to the two sample t-test for all throughput values with a 95% confidence level. As the improvement of the proposed release policy: LWC is relatively less on the proposed release policies: CONSTWL and CONSTBWL with respect to mean delay, it can be inferred that the performance of CONSTWL and CONSTBWL is relatively better than other existing closed loop release policies for the scenarios considered in the simulation model. However, the best release policy: LWC provides satisfactory performance in comparison with other release policies for almost all scenarios considered in the simulation model. It is important to note that these proposed release policies can be easily applied in real wafer manufacturing systems because it possesses a simple logic and only the reference level need to be prescribed. The performance of four existing closed release policies that are FRCP, EWIP, TOTAL_CT and PWR are relatively worst in comparison with open loop release policy CONST. This is contradicting to the conclusions given in the literature by many authors that closed loop release policies are always better than open loop release policy with respect to cycle time and throughput measures. In fact, a reasonable closed loop release policy can provide better results than open loop release policy, if its objective and the release parameter are designed carefully, so that the release parameter can respond effectively to the dynamics of the manufacturing system. The reason for worst performance of these four existing closed loop release policies in comparison with open loop release policy and other existing policies is described in detail in this study. In order to see the impact of dispatching rules on a particular work station, batch machine work station, which usually has highest processing time in fabrication process, is considered in this study. The entire simulation experiments are replicated in the same manner except the basis that dispatching rules are applied on batch machine work station instead of bottleneck work station. Based on the analysis of the simulation results, the important observations are as follow: It is observed from the overall inferences that the influence of dispatching rules when applied to batch processing machine (diffusion) work station was not much on individual release policies, since the performance of all three dispatching rules provides nearly same performance at higher throughput level in the proposed simulation model. However, the performances of dispatching rule: SRPT in integration with all release policies considered in this study are summarized here because it produces less mean delay at most of the throughput values. In addition, from the analysis of simulation model, the proposed release policy: LWC reduces the average delay up to 97%, 93%, 87%, 85%, 22%, 17%, 15%, 15%, 13%, 11%, 10%, 10%, 9%, 6%, 6% and 2%, and reduces the standard deviation of delay up to 96%, 97%, 92%, 93%, 21%, 5%, 10%, 2%, 16%, 7%, 14%, 4%, 20%, 10%, 10% and 11% for a given throughput level, respectively in relation to FRCP, EWIP, PWR, TOTAL_CT, EWC, DEC, Droll, CONLOAD, SA, RCONWIP, WIPLCtrl, WR, DRCP, CONWIP, CONSTWL and CONSTBWL in integration with dispatching rule: SRPT, when applied on batch processing machine work station. The improvement is statistically significant according to the two sample t-test for most of the throughput values with a 95% confidence level. It is observed from overall inferences that the performance of all the release policies, considered in this study, in integration with dispatching rule: SRPT is better with respect to both mean delay and standard deviation of delay, when the dispatching rule is applied on the bottleneck (discrete machine, lithography) work station in the proposed simulation model. The performance of most of the release policies, considered in this study, in integration with dispatching rule: LIFO is better with respect to standard deviation of delay, when the dispatching rule is applied on the batch (batch machine, diffusion) work station. These results indicate that there is an influence of dispatching rule on the performance of wafer fabrication system if applied on batch machine work station or on bottleneck work station in integration with release policies. In addition, the effects of dispatching rules are highly dependent upon both the type of release policy used and the work station on which it is applied. Overall, the performance of the proposed release policies is proven to be very effective to system variability’s in scenarios considered in the simulation model. The significant impact of the choice of release policies on wafer manufacturing system performance is justified by the simulation experiments. It can be safely concluded that the efficient closed loop release policies that utilizes system information carefully based on the global factory state data can significantly improve the performance of wafer fabrication system. This thesis provides an extensive literature review covering several aspects of wafer fabrication process. Thereafter, a three new efficient closed loop release policies are developed and their workability are conceptually demonstrated with a framework and a flow diagram. The strength and the weakness of the existing release policies are conceptually highlighted and later it is proven to be true through comprehensive simulation study. A simulation model is developed by considering all the real-life fabrication environment for evaluating the performance of release policies in integration with dispatching rules. Cause and effect analysis is explored in proposed simulation model to set the parameters value. A series of simulation experiments are also constructed to empirically justify the conceptual significance of the proposed release policies.

Du fait de la miniaturisation des composants semi-conducteurs, il est devenu de plus en plus important de réduire les niveaux de contamination. Les salles blanches sont indispensables pour assurer un environnement adéquat pour l'élaboration des composants microélectroniques. Toutefois, jusqu'à présent aucune technologie ne permet le contrôle de la contamination organique volatile, et même dans tels environnements contrôlés, la contamination des surfaces de wafers a souvent lieu. Une nouvelle approche expérimentale a été développée dans notre laboratoire afin de suivre les processus d'adsorption et de désorption des contaminants organiques volatils et semi-volatils à la surface des wafers. Ce dispositif est constitué de trois composants principaux : un générateur des composés en phase gaz, un tube à écoulement et le spectromètre de masse par transfert de proton comme outil analytique de mesure de la composition de la phase gazeuse. Les comportements d'adsorption de cinq composés organiques volatils parmi les plus abondants dans les environnements des salles blanches (l'isopropanol, l'acétone, le xylène, l'acétate d'éthyle et le propylène glycol méthyl éther acétate) et trois semi-volatils (diéthylphtalate, tri-(2-chloroéthyl)-phosphate et le tri- (2-cloropropyl)-phosphate) ont été étudiés. Les paramètres cinétiques des processus d'adsorption ont été déterminés. Les corrélations entre leurs concentrations en phase gazeuse et leurs densités à la surface des wafers ont été établies. En comparant les comportements d'adsorption de tous les composés étudiés, il a été démontré que la constante de désorption kdes est le facteur le plus influent sur les équilibres d'adsorption. / As semiconductor devices become smaller, it is increasingly important to reduce the degree of organic contamination in the areas where such devices are produced. It has been shown that cleanrooms are indispensable to provide a suitable environment for processing semiconductor devices. However, at present time there is no technology for controlling the contamination with volatile organic compounds (VOC), and even in such an environment, the wafers are exposed to VOC. A new experimental approach has been developed in our laboratory in order to follow the adsorption and desorption processes of volatile and semi volatiles organic compounds on silicon wafer surfaces. This unique setup is based on three principal components: a stable gas-phase generator, a flow tube reactor, and a proton-transfer-reaction–mass spectrometry (PTR-MS) analytical device to monitor the VOC. The adsorption behavior of five the most abundant VOCs in the cleanroom environment (isopropanol, acetone, xylene, ethyl acetate and propylene glycol methyl ether acetate) and three semi volatile organic compounds (diethylphtalate, tri-(2-chloroethyl)-phosphate and tri-(2-cloropropyl)-phosphate) on silicon wafer surface was studied. The kinetic parameters were determined and correlations between the gas phase concentrations and the surface densities of the organic contaminants were established. By comparing the adsorption properties of the studied compounds, it has been demonstrated that time dependant changes in the surface concentration of the organic species are governed by desorption constants, kdes. Moreover, kdes was found to be dependent on the molecular weight of the studied organics.

Geometric quality variables of wafers, such as BOW and WARP, are critical in their applications. A large variation of these quality variables reduces the number of conforming products in the downstream production. Therefore, it is important to reduce the variation by variation modeling, analysis and control for multistage wafer manufacturing processes (MWMPs). First, an intermediate feedforward control strategy is developed to adjust and update the control actions based on the online measurements of intermediate wafer quality measurements. The control performance is evaluated in a MWMP to transform ingots into polished wafers. However, in a complex multistage manufacturing process, the quality variables may have nonlinear relationship with the parameters of the predictors. In this case, piecewise linear regression tree (PLRT) models are used to address nonlinear relationships in MWMP to improve the model prediction performance. The obtained PLRT model is further reconfigured to be complied with the physical layout of the MWMP for feedforward control purposes. The procedure and effectiveness of the proposed method is shown in a case study of a MWMP. Furthermore, as the geometric profiles and quality variables are important quality features for a wafer, fast and accurate measurements of those features are crucial for variation reduction and feedforward control. A sequential measurement strategy is proposed to reduce the number of samples measured in a wafer, yet provide adequate accuracy for the quality feature estimation. A Gaussian process model is used to estimate the true profile of a wafer with improved sensing efficiency. Finally, we study the multistage multimode process monitoring problem. We propose to use PLRTs to inter-relate the variables in a multistage multimode process. A unified charting system is developed. We further study the run length distribution, and optimize the control chart system by considering the modeling uncertainties. Finally, we compare the proposed method with the risk adjustment type of control chart systems based on global regression models, for both simulation study and a wafer manufacturing process.

<p>Semiconductor wafer bonding has been a subject of interestfor many years and a wide variety of wafer bonding techniqueshave been reported in literature. In adhesive wafer bondingorganic and inorganic adhesives are used as intermediatebonding material. The main advantages of adhesive wafer bondingare the relatively low bonding temperatures, the lack of needfor an electric voltage or current, the compatibility withstandard CMOS wafers and the ability to join practically anykind of wafer materials. Adhesive wafer bonding requires nospecial wafer surface treatmentssuch as planarisation.Structures and particles at the wafer surfaces can be toleratedand compensated for some extent by the adhesive material.Adhesive wafer bonding is a comparably simple, robust andlowcost bonding process. In this thesis, adhesive wafer bondingtechniques with different polymer adhesives have beendeveloped. The relevant bonding parameters needed to achievehigh quality and high yield wafer bonds have been investigated.A selective adhesive wafer bonding process has also beendeveloped that allows localised bonding on lithographicallydefined wafer areas.</p><p>Adhesive wafer bonding has been utilised in variousapplication areas. A novel CMOS compatible film, device andmembrane transfer bonding technique has been developed. Thistechnique allows the integration of standard CMOS circuits withthin film transducers that can consist of practically any typeof crystalline or noncrystalline high performance material(e.g. monocrystalline silicon, gallium arsenide,indium-phosphide, etc.). The transferred transducers or filmscan be thinner than 0.3 µm. The feature sizes of thetransferred transducers can be below 1.5 µm and theelectrical via contacts between the transducers and the newsubstrate wafer can be as small as 3x3 µm2. Teststructures for temperature coefficient of resistancemeasurements of semiconductor materials have been fabricatedusing device transfer bonding. Arrays of polycrystallinesilicon bolometers for use in uncooled infrared focal planearrays have been fabricated using membrane transfer bonding.The bolometers consist of free-hanging membrane structures thatare thermally isolated from the substrate wafer. Thepolycrystalline silicon bolometers are fabricated on asacrificial substrate wafer. Subsequently, they are transferredand integrated on a new substrate wafer using membrane transferbonding. With the same membrane transfer bonding technique,arrays of torsional monocrystalline silicon micromirrors havebeen fabricated. The mirrors have a size of 16x16 µm2 anda thickness of 0.34 µm. The advantages of micromirrorsmade of monocrystalline silicon are their flatness, uniformityand mechanical stability. Selective adhesive wafer bonding hasbeen used to fabricate very shallow cavities that can beutilised in packaging and component protection applications. Anew concept is proposed that allows hermetic sealing ofcavities fabricated using adhesive wafer bonding. Furthermore,microfluidic devices, channels and passive valves for use inmicro total analysis systems are presented.</p><p>Adhesive wafer bonding is a generic CMOS compatible bondingtechnique that can be used for fabrication and integration ofvarious microsystems such as infrared focal plane arrays,spatial light modulators, microoptical systems, laser systems,MEMS, RF-MEMS and stacking of active electronic films forthree-dimensional high-density integration of electroniccircuits. Adhesive wafer bonding can also be used forfabrication of microcavities in packaging applications, forwafer-level stacking of integrated circuit chips (e.g. memorychips) and for fabrication of microfluidic systems.</p>

Eine grundlegende Schwierigkeit in der Röntgenoptik liegt in der Bereitstellung geeigneter Optiken. So ist aufgrund der schwachen Wechselwirkung der Röntgenstrahlung mit Materie der Einsatz brechender Optiken nicht sinnvoll, und es wird auf alternative Konzepte wie Röntgenwellenleiter zurückgegriffen. Röntgenwellenleiter sind nicht-dispersive strahlführende Optiken, welche die Kohärenz der Röntgenstrahlung filtern und als quasi-Punktquellen fungieren. Hierbei wird der Röntgenstrahl in einer oder zwei Dimensionen räumlich beschränkt, wobei der Wellenlängenbereich der Röntgenstrahlung eine Abmessung im sub-100 nm-Bereich erfordert. In der vorliegenden Arbeit wurde ein Verfahren etabliert, mit welchem die Herstellung von Wellenleiterkanälen im sub-50 nm-Bereich in Silizium gelingt. Die Prozessierung basiert hierbei auf einem Schema aus elektronenstrahllithographischer Belichtung, Reaktivem Ionenätzen und Wafer bonding. Das Verfahren ist variabel in Bezug auf verschiedene Wellenleitergeometrien, beispielsweise gekreuzte Wellenleiter und Kanalwellenleiter, ist auf alternative Materialien übertragbar, und erlaubt die Strahlführung auf in einer Dimension gekrümmten Pfaden. Die im Rahmen der vorliegenden Arbeit hergestellten Wellenleiter wurden erfolgreich an verschiedenen Synchrotron-Messplätzen eingesetzt und ihre Fernfelder charakterisiert, und der kohärente Wellenleiterstrahl wurde in der Röntgenmikroskopie und der holographischen Bildgebung eingesetzt. Es finden sich sowohl für die Quellgröße der Wellenleiter als auch für die Auflösung in der Bildgebung Werte im sub-50 nm-Bereich.