Direct semiconductor wafer bonding has emerged as a technology to meet the demand foradditional flexibility in materials integration. The applications are found in microelectronics, optoelectronics and micromechanics. For instance, wafer bonding is used to produce silicon-on-insulator (SOI) wafers. Wafer bonding is also interesting to use for combining dissimilar semiconductors, such as Si and InP, with different dictated optical, electronic and mechanicalproperties. This enables a completely new freedom in the design of components and systems, e.g. for high performance optoelectronic integrated circuits (OEIC). Although wafer bonding has proved to be a useful and versatile tool, the high temperature annealing that is needed to achieve reliable properties sometimes hampers its applicability. Therefore, low temperature wafer bonding procedures may further qualify this technology. In the present thesis, low temperature wafer bonding procedures using oxygen plasma surface activation have been studied. A specially designed fixture was adopted enabling in situ oxygen plasma wafer bonding. Oxygen plasma surface activation was seen to indeed yield high Si-Si bonding-strength at low temperatures. Here, the optimisation of the plasma parameters was shown to be the key to improved results. Furthermore, dependence of wafer bonded Si p-n junctions on the annealing temperature was investigated. InP-to-Si wafer bonding is also presented within this thesis. High temperature annealing was seen to induce severe material degradation. However, using oxygen plasma assisted wafer bonding reliable InP-to-Si integration was achieved already at low temperature, thereby circumventing the problems associated with the lattice and thermal mismatch that exist between these materials. As a result, low temperature InP-based epitaxial-layer transferring to Si could be presented. Finally, high-quality SiO2 insulator on InP and Si was realised at low temperatures. It is concluded that low temperature oxygen plasma assisted wafer bonding is an interesting approach to integrate dissimilar materials, for a wide range of applications.

Vertical-cavity surface-emitting lasers (VCSELs) areattractive as potential inexpensive high-performance emittersfor fibre-optical communication systems. Their surface-normalemission together with the small dimensions are beneficial forlow-cost fabrication since it allows on-wafer testing,simplified packaging and effective fibre-coupling. Forhigh-speed data transmission up to hundreds of metres, 850-nmVCSELs are today the technology of choice. For higher bandwidthand longer distance networks, emission at long-wavelength(1.3-1.55 µm) is required. Long-wavelength VCSELs are,however, not available since no materials system offershigh-index-contrast distributed Bragg reflectors (DBRs) as wellas high-gain active regions at such wavelengths.High-performance DBRs may be built up from AlGaAs/GaAsmultilayers, but long wavelength quantum wells (QWs) are onlywell established in the InP system. Therefore, the bestperforming devices have relied on wafer-fusion betweenInP-based QWs and AlGaAs-DBRs. More recently, however, the mainefforts have been shifted towards all-epitaxial GaAs-baseddevices, employing 1.3-µm GaInNAs QWs. In this thesis, different processing technologies forlong-wavelength VCSELs are described. This includes a thoroughinvestigation of wafer-fusion between InP and GaAs regardingelectro-optical as well as metallurgical properties, and thedevelopment of a stable low-pressure process for the selectiveoxidation of AlAs. Optimised AlGaAs/GaAs DBRs were designed andfabricated. An important and striking observation from thatstudy is that n-type doping potentially is much moredetrimental to device performance than previously anticipated.These investigations were exploited in the realisation of twonew VCSEL designs. Near-room-temperature continuous-waveoperation of a single-fused 1.55-µm VCSEL was obtained.This demonstrated the potential of InGaAsP/InP DBRs inhigh-performance VCSELs, but also revealed a high sensitivityto self-heating. Further efforts were therefore directedtowards all-epitaxial GaAs-based structures. This resulted in ahigh-performance 1215-nm VCSEL with a highly strained InGaAssingle QW. This can be viewed as a basis for longer-wavelengthVCSELs, i.e., with an emission wavelength approaching 1300 nm,either by an extensive device detuning or with GaInNAs QWs. <b>Keywords</b>: VCSEL, vertical cavity laser, semiconductorlaser, long-wavelength, DBR, oxidation, wafer fusion, InGaAs,semiconductor processing

In recent years there has been a huge increase in the growth of communication systems such as mobile phones, wireless local area networks (WLAN), satellite navigation and various other forms of wireless data communication that have made analogue frequency control a key issue. The increase in frequency spectrum crowding and the increase of frequency into microwave region, along with the need for minimisation and capacity improvement, has shown the need for the development of high performance, miniature, on-chip filters operating in the low to medium GHz frequency range. This has hastened the need for alternatives to ceramic resonators due to their limits in device size and performance, which in turn, has led to development of the thin film electro-acoustics industry with surface acoustic wave (SAW) and bulk acoustic wave (BAW) filters now fabricated in their millions. Further, this new technology opens the way for integrating the traditionally incompatible integrated circuit (IC) and electro-acoustic (EA) technologies, bringing about substantial economic and performance benefits. In this thesis the compatibility of aluminium nitride (AlN) to IC fabrication is explored as a means for furthering integration issues. Various issues have been explored where either tailoring thin film bulk acoustic resonator (FBAR) design, such as development of an improved solidly mounted resonator (SMR) technology, and use of IC technology, such as chemical mechanical polishing (CMP) or nickel silicide (NiSi), has made improvements beneficial for resonator fabrication or enabled IC integration. The former has resulted in major improvements to Quality factor, power handling and encapsulation respectively. The later has provided alternative methods to reduce electro- or acoustomigration, reduced device size, for plate waves, supplied novel low acoustic impedance material for high power applications and alternative electrodes for use in high temperature sensors. Another method to enhance integration by using the piezoelectric material, AlN, in the IC side has also been explored. Here methods for analysing AlN film contamination and stoichiometry have been used for analysis of AlN as a high-k dielectric material. This has even brought benefits in knowledge of film composition for use as a passivation material with SiC substrates, investigated in high power high frequency applications. Lastly AlN has been used as a buried insulator material for new silicon-on-insulator substrates (SOI) for increased heat conduction. These new substrates have been analysed with further development for improved performance indicated. / wisenet

<p>Advancements of the semiconductor technology opened a new era in</p> <p>wireless communications which led manufacturers to produce faster,</p> <p>more functional devices in much smaller sizes. However, testing</p> <p>these devices of today's technology became much harder and expensive</p> <p>due to the complexity of the devices and the high operating speeds.</p> <p>Moreover, testing these devices becomes more important since decreasing</p> <p>feature sizes increase the probability of parametric and catastrophic</p> <p>faults because of the severe effects of process variations. Manufacturers</p> <p>have to increase their test budgets to address quality and reliability</p> <p>concerns. In the radio frequency (RF) domain, overall test cost are higher</p> <p>due to equipment costs, test development and test time costs. Advanced</p> <p>circuit integration, which integrates various analog and digital circuit</p> <p>blocks into single device, increases test costs further because of the</p> <p>additional tests requiring new test setups with extra test equipments.</p> <p>Today's RF transceiver circuits contain many analog and digital circuit</p> <p>blocks, such as synthesizers, data converters and the analog RF front-end</p> <p>leading to a mixed signal device. Verification of the specifications and</p> <p>functionality of each circuit block and the overall transceiver require</p> <p>RF instrumentation and lengthy test routines. In this dissertation, we</p> <p>propose efficient component and system level test methods for RF</p> <p>transceivers which are low cost alternatives to traditional tests.</p> <p>In the first component level test, we focus on in-band phase noise of the</p> <p>phase locked loops (PLL). Most on-chip self-test methods for PLLs aim at</p> <p>measuring the timing jitter that may require precise reference clocks and/or</p> <p>additional computation of measured specs. We propose a built in test (BiT)</p> <p>circuit to perform a go/no-go test for in-band PLL phase noise. The proposed</p> <p>circuit measures the band-limited noise power at the input of the voltage</p> <p>controlled oscillator (VCO). This noise power is translated as the high</p> <p>frequency in-band phase noise at the output of the PLL. Our circuit contains</p> <p>a self calibration sequence based on a simple sinusoidal input signal to make</p> <p>it robust with respect to process variations.</p> <p>The second component level test is a built in self test (BiST) scheme</p> <p>proposed for analog to digital converters (ADC) based on a linear ramp</p> <p>generator and efficient output analysis. The proposed analysis method is</p> <p>an alternative to histogram based analysis techniques to provide test time</p> <p>improvements, especially when the resources are scarce. In addition to the</p> <p>measurement of differential nonlinearity (DNL) and integral nonlinearity</p> <p>(INL), non-monotonic behavior of the ADC can also be detected with the</p> <p>proposed technique. The proposed ramp generator has a high linearity</p> <p>capable of testing 13-bit ADCs.</p> <p>In the proposed system level test methods, we utilize the loop-back</p> <p>configuration to eliminate the need for an RF instrument. The first loop-back</p> <p>test method, which is proposed for wafer level test of direct conversion</p> <p>transceivers, targets catastrophic and large parametric faults. The use of</p> <p>intermediate frequencies (IF) generates a frequency offset between the transmit</p> <p>and receive paths and prevents a direct loop-back connection. We overcome this</p> <p>problem by expanding the signal bandwidth through saturating the receive path</p> <p>composed of low noise amplifier (LNA) and mixer. Once the dynamic range of the</p> <p>receiver path is determined, complete transceiver can be tested for catastrophic</p> <p>signal path faults by observing the output signal. A frequency spectrum</p> <p>envelope signature technique is proposed to detect large parametric faults.</p> <p>The impact of impairments, such as transmitter receiver in-phase/quadrature</p> <p>(I/Q) gain and phase mismatches on the performance have become severe due to</p> <p>high operational speeds and continuous technology scaling. In the second system</p> <p>level loop-back test method, we present BiST solutions for quadrature modulation</p> <p>transceiver circuits with quadrature phase shift keying (QPSK) and Gaussian</p> <p>minimum shift keying (GMSK) baseband modulation schemes. The BiST methods</p> <p>use only transmitter and receiver baseband signals for test analysis. The</p> <p>mapping between transmitter input signals and receiver output signals are</p> <p>used to extract impairment and nonlinearity parameters separately with the</p> <p>help of signal processing methods and detailed nonlinear system modeling.</p> <p>The last system level test proposed in this dissertation combines the benefits </p> <p>of loop-back and multi-site test approaches. In this test method, we present </p> <p>a 2x-site test solution for RF transceivers. We perform all operations on </p> <p>communication standard-compliant signal packets, thereby putting the device </p> <p>under the normal operating conditions. The transmitter on one device under </p> <p>test (DUT) is coupled with a receiver on another DUT to form a complete TX-RX </p> <p>path. Parameters of the two devices are decoupled from one another by carefully </p> <p>modeling the system into a known format and using signal processing techniques.</p> / Dissertation

<p>The visible light photon counter (VLPC) is a high quantum efficiency (QE), Si-based, single-photon detector with high gain, low-noise multiplication, low timing jitter, and photon number resolution. While the VLPC has high QE in the visible wavelengths, the QE in the ultraviolet and infrared is low due to minimal absorption within the active layers of the device. In the ultraviolet, the absorption coefficient of Si is high and most of the incident photons are absorbed within the top contact of the device, whereas, in the infrared, Si is practically transparent. A number of applications in quantum information science would benefit from use of the VLPC if the QE was improved in the ultraviolet (e.g., state detection of trapped ions) and the infrared (e.g., long-distance quantum cryptography). This thesis describes the development of the ultraviolet photon counter (UVPC) and the infrared photon counter (IRPC), which are modified versions of the VLPC with increased QE in the ultraviolet and infrared wavelengths, respectively. The UVPC has a transparent metal Schottky contact to reduce absorption within the top contact of the VLPC, resulting in an increase in the QE in the ultraviolet by several orders of magnitude. The IRPC is a proposed device that has an InGaAs absorption layer that is wafer-fusion bonded to the VLPC. The band alignment of the resulting InGaAs/Si heterojunction is measured and shows a large discontinuity in the valence band that impedes carrier transport at the interface. A ultra-high vacuum wafer-bonding system was developed to understand the impact of the surface chemistry of the bonded wafers on the band alignment of the InGaAs/Si heterojunction of the IRPC.</p> / Dissertation

This thesis reports on a new low-cost wafer-level packaging technology for microelectromechanical systems (MEMS). The MEMS process is based on a revised version of High Aspect Ratio Polysilicon and Single Crystal Silicon (HARPSS) technology. The packaging technique is based on thermal decomposition of a sacrificial polymer through a polymer overcoat followed by metal coating to create resizable MEMS packages. The sacrificial polymer is created on top of the active component including beams, seismic mass, and electrodes by photodefining, dispensing, etching, or molding. The low loss polymer overcoat is patterned by photodefinition to provide access to the bond pads. The sacrificial polymer decomposes at temperatures around 200-280aC and the volatile products permeate through the overcoat polymer leaving an embedded air-cavity. For MEMS devices that do not need hermetic packaging, the encapsulated device can then be handled and packaged like an integrated circuit. For devices that are sensitive to humidity or need vacuum environment, hermiticity is obtained by deposition and patterning thin-film metals such as aluminum, chromium, copper, or gold. To demonstrate the potential of this technology, different types of capacitive MEMS devices have been designed, fabricated, packaged, and characterized. These includes beam resonators, RF tunable capacitors, accelerometers, and gyroscopes. The MEMS design includes mechanical, thermal, and electromagnetic analysis. The device performance, before and after packaging is compared and the correlation to the model is presented. The following is a summary of the main contributions of this work to the extensive research focused on MEMS and their packaging: 1)A new low-cost wafer-level packaging method for bulk or surface micromachined devices including resonators, RF passives and mechanical sensors is reported. This technique utilizes thermal decomposition of a sacrificial polymer through an overcoat polymer to create buried channels on top of the resonant/movable parts of the micromachined device. It provides small interconnections together with resizable package dimensions. We report MEMS package thicknesses in the range of 10 mm to 1 mm, and package size from 0.0001 mm to 1 mm. 2)A revised version of the HARPSS technology is presented to implement high aspect ratio silicon capacitors, resonators and inertial sensors in the smallest area.

The Wafer Level Chip Scale Package (WLCSP) is gaining popularity for its performance and ability to meet the miniaturization requirements of portable consumer electronics, such as cell phones. For the industry of electronic package, the package life of electronic products is deemed as the essential consideration in the operation period. In practice, electronic products are usually damaged due to a harsh mechanical impact, such as drop and bending. The solder interconnections provide not only the electronic path between electric components and printing circuit board, but also the mechanical support of components on the printing circuit board, so that the reliability of solder interconnection becomes an essential consideration for a package. In the thesis several parameters, including redistribution layer (RDL) material and thickness, passivation material and thickness, under-bump metallization (UBM) structure factors are discussed. A variety of WLCSP structures are investigated for solder joint reliability performance. In addition to the fatigue lives of the test vehicle, locations and modes of fractured solder joints were observed. It was found that wafer level packaging structure under drop clearly related with the characteristic life. The weakest point of solder ball was intermetallic compound (IMC), and wafer level packaging structure was the crack into the second passivation layer and UBM interface of the corner. WLCSP under temperature cycling test was done and observed the fracture only occurred at the solder ball near the package.

This study describes the design and fabrication of dual-mode film bulk acoustic resonator (TFBAR) devices to construct wafer level T-ladder type filters. Reactive radio-frequency (RF) magnetron sputtering method was used to deposit c-axis- tilted ZnO piezoelectric thin films. The piezoelectric ZnO thin films were deposited by a two-step method at room temperature with off-axis. In this investigation, off-axis distance was varied to determine the optimal growth parameters of the tilted piezoelectric thin film. The SEM and XRD analysis reveal that ZnO thin films deposited at off-axis distances of 35 mm yielded a highly textured and sufficiently-tilted ZnO piezoelectric layer for dual-mode TFBAR. Additionally, the ZnO piezoelectric layer with off-axis distances of 35 mm exhibited enhanced competitive growth, and had a c-axis-tilted angle of 5¢X. To explore the relationship between the c-axis-tilted angle and the dual-mode resonance frequency responses (fL and fS) of TFBAR, two TFBAR devices were fabricated with ZnO c-axis tilted at 4.4¢X and 5¢X, respectively. The TFBAR device with 5¢X-tilted ZnO layer exists shear and longitudinal resonant modes. The center-frequency of longitudinal resonant mode is 2.2 times that of the shear resonant mode. The longitudinal mode is suitable for designing as a communication receiver (Rx) device at WCDMA band. On the other hand, the shear mode of TFBAR is suitable for EGSM-900 band. To optimize the characteristics, the filter was annealed by CTA treatment in 400 ¢J. For the frequency responses of the longitudinal wave, the insertion loss was upgraded from -5.77 dB without annealing to -4.85 dB as annealed, the band rejection was reduced from 13.57 dB to 12.65 dB, the bandwidth was broaden from 69.69 MHz to 73.12 MHz. On the other hand, for the frequency responses of the shear wave, the insertion loss was upgraded from -9.94 dB to -8.21 dB, the band rejection was reduced from 13.74 dB to 13 dB, the bandwidth was decreased from 28.13 MHz to 28.12 MHz.

In this thesis 10x10 reconfigurable reflectarray is designed at 26.5 GHz where the change in the progressive phase shift between elements is obtained with RF MEMS switches in the transmission lines of unit elements composed of aperture coupled microstrip patch antenna (ACMPA). The reflectarray is illuminated by a horn antenna, and the reflected beam is designed to switch between broadside and 40&deg / by considering the position of the horn antenna with respect to the reflectarray. In the design, the transmission line analysis is applied for matching the ACMPA to the free space. The full wave simulation techniques in HFSS are discussed to obtain the phase design curve which is used in determining two sets of transmission line lengths for each element, one for the broadside and the other for switching to the 40&deg / at 26.5 GHz. The switching between two sets of transmission line lengths is sustained by inserting RF MEMS switches into the transmission lines in each element. Two types of RF MEMS switches, series and shunt configurations, are designed for the switching purpose in the reflectarray. The phase errors due to nonideal phase design curve and type of the RF MEMS switch are reduced. The possible mutual coupling effects of the bias lines used to actuate the RF MEMS switches are also eliminated by the proper design. To show the validity of the design procedure, a prototype of 20x20 reflectarray composed of ACMPA elements is designed at 25GHz and produced using Printed Circuit Board (PCB) technology. The measurement results of the prototype reflectarray show that the main beam can be directed to the 40&deg / as desired. The process flow for the production of the reconfigurable reflectarray is suggested in terms of integration of the wafer bonding step with the in-house standard surface micromachined RF MEMS process.

The goal of this research was to investigate an experimental infrared transmission technique to extract the full stress components of the in-plane residual stresses in thin multi crystalline silicon wafer, and try to meet the need of photovoltaic industry to in situ measure residual stress for large cast wafers.