Planning and scheduling in semiconductor manufacturing is a difficult problem due to long cycle times, a large number of operational steps, diversified product types, and low-volume high-mix customer demand. This research addresses several problems that arise in the semiconductor industry related to front-end wafer fabrication operations and back-end assembly and test operations. The mathematical models built for these problems turn out to be large-scale mixed integer programs and hard to solve with exact methods. The major contribution of this research is to combine mathematical programming with metaheuristics to find high quality solutions within the time limits imposed by the industrial engineers who oversee the fabrication and test facilities. In order to reduce the size of problems that arise in practice, it is common to cluster similar product types into groups that reflect their underlying technology. The first part of the research is aimed at developing a greedy randomized adaptive search procedure (GRASP) coupled with path relinking (PR) to solve the capacitated clustering problem. The model is generic and can be applied in many different situations. The objective is to maximize a similarity measure within each cluster such that the sum of the weights associated with the product types does not exceed the cluster capacity in each case. In phase I, both a heaviest weight edge (HWE) algorithm and a constrained minimum cut (CMC) algorithm are used to select seeds for initializing the clusters. Feasible solutions are obtained with the help of a self-adjusting restricted candidate list. In phase II, three neighborhoods are defined and explored using the following strategies: cyclic neighborhood search, variable neighborhood descent, and randomized variable neighborhood descent (RVND). The best solutions found are stored in an elite pool. In a post-processing step, PR coupled with local search is applied to the pool members to cyclically generate paths between each pair. The elite pool is updated after each iteration and the procedure ends when no further improvement is possible. After grouping the product types into technologies, a new model is presented for production planning in a high volume fab that uses quarterly commitments to define daily target outputs. Rather than relying on due dates and priority rules to schedule lot starts and move work in process through the shop, the objective is to minimize the sum of the deviations between the target outputs and finished goods inventory. The model takes the form of a large-scale linear program that is intractable for planning horizons beyond a few days. Both Lagrangian relaxation and Benders decomposition were investigated but each proved ineffective. As a consequence, a methodology was developed which was more tailored to the problem’s structure. This involved creating weekly subproblems that were myopic but could be solved to optimality within a few minutes, and then postprocessing the results with a decomposition algorithm to fully utilize the excessive machine time. The heart of the post-processor consists of a rescheduling algorithm and a dispatching heuristic. The third part of the research focuses on the combinatorial problem of machinetooling setup and lot assignments for performing back-end operations. A new model and solution methodology are presented aimed at maximizing the weighted throughput of lots undergoing assembly and test, while ensuring that critical lots are given priority. The problem is formulated as a mixed-integer program and solved again with a GRASP that makes use of linear programming. In phase I of the GRASP, machine-tooling combinations are tentatively fixed and lot assignments are made iteratively to arrive at a feasible solution. This process is repeated many times. In phase II, a novel neighborhood search is performed on a subset of good solutions found in phase I. Using a linear programming-Monte Carlo simulation-based algorithm, new machine-tooling combinations are identified within the neighborhood of the solutions carried over, and improvements are sought by optimizing the corresponding lot assignments. / text

As the thinnest material ever with high carrier mobility and saturation velocity, graphene is considered as a candidate for future high speed electronics. After pioneering research on graphene-based electronics at Georgia Tech, epitaxial graphene on SiC, along with other synthesized graphene, has been extensively investigated for possible applications in high frequency analog circuits. With a combined effort from academic and industrial research institutions, the best cut-off frequency of graphene radio-frequency (RF) transistors is already comparable to the best result of III-V material-based devices. However, the power gain performance of graphene transistors remained low, and the absence of a band gap inhibits the possibility of graphene in digital electronics. Aiming at solving these problems, this thesis will demonstrate the effort toward better high frequency power gain performance based on mono-layer epitaxial graphene on C-face SiC. Besides, a graphene/Si integration scheme will be proposed that utilizes the high speed potential of graphene electronics and logic functionality and maturity of Si-CMOS platform at the same time.

Lors de l'assemblage de wafers par adhésion moléculaire, un mince film d'air est piégé entre les deux wafers, créant ainsi un système fluide/structure couplé. La qualité finale de l'assemblage dépend fortement de la dynamique de ce système. L'initiation et la propagation du collage ont été étudiées, en régime transitoire, en utilisant un modèle de plaques minces couplée avec l'équation de Reynolds. La résolution numérique de l'équation, ainsi que la mesure optique du déplacement vertical de la plaquette durant le collage, nous a permis de valider le modèle et de mieux comprendre la dynamique du collage. Dans la continuité de cette étude, nous avons proposé une expression analytique de la courbure finale de l'assemblage en fonction des forces en jeu pendant le collage, ceci en utilisant à nouveau la théorie des plaques minces et en considérant l'existence d'un saut de déformation transverse le long de l'interface collée. Ce modèle a été validé par une expérience, impliquant le collage de wafers d'épaisseur différentes et en prenant soin de contrôler l'ensemble des forces agissant sur ces wafers. Nous observons une influence importante du film d'air sur la forme finale des wafers. En complément, un modèle du travail d'adhésion a été développé prenant en compte, à la fois, la rugosité d'interface et la quantité d'eau adsorbée. La différence de répartition de l'eau à l'interface de collage, nous permet d'expliquer les résultats expérimentaux montrant des valeurs d'énergie de séparation supérieure à celle de l'adhésion. Enfin, nous proposons une nouvelle méthode de mesure du travail d'adhésion pour la géométrie entière des wafers, utilisant la mesure de la taille d'une bulle cylindrique intentionnellement créée, par un petit objet, à l'interface de collage.

Depuis l'invention du transistor dans les années 50, les performances des composants microélectroniques n'ont cessé de progresser, en passant notamment par l'augmentation de leur densité. Malheureusement, la miniaturisation des composants augmente les coûts de fabrication de façon prohibitive. Une solution, permettant d'accroître la densification et les fonctionnalités tout en limitant les coûts, passe par l'empilement des composants microélectroniques. Leurs connexions électriques s'effectuent alors à l'aide d'interconnexions verticales soudées au moyen d'un joint de brasure. Afin d'empêcher leurs ruptures lors des dilatations thermiques, les interconnexions sont protégées au moyen d'un polymère underfill. L'objectif de cette thèse est d'évaluer la faisabilité et la pertinence d'une nouvelle solution de remplissage par polymère, appelée wafer-level underfill (WLUF). L'écoulement de l'underfill durant l'étape d'assemblage des composants est modélisé afin de prédire les paramètres de scellement idéaux, permettant la formation des interconnexions électriques. Puis, l'intégration de nouveaux underfills, possédant des propriétés thermomécaniques différentes, pouvant affecter l'intégrité et le fonctionnement du dispositif, l'étude de la fiabilité du procédé WLUF et, par conséquent, l'évaluation de sa possibilité d'industrialisation est effectuée.

This dissertation reports, for the first time, on the design and implementation of tunable micromachined bandpass filters in the ultra high frequency (UHF) range that are fully integrated on CMOS-grade (resistivity=10-20 ohm.cm) silicon. Filters, which are designed in the Elliptic and coupled-resonator configuration, are electrostatically tuned using tunable microelectromechanical (MEM) capacitors with laterally movable interdigitated fingers. Tunable filters and high-quality factor (Q) integrated passives are made in silver (Ag), which has the highest conductivity of all materials in nature, to reduce the ohmic loss. The loss of the silicon substrate is eliminated by using micromachining techniques. The combination of the highest-conductivity metal and a low-loss substrate significantly improves the performance of lumped components at radio frequencies (RF), resulting in an insertion loss of 6 dB for a tunable lumped bandpass filter at 1075 MHz with a 3 dB-bandwidth of 63 MHz and tuning range of 123 MHz. The bandpass filters are encapsulated at the wafer level using a low-temperature, thermally released, polymer packaging process. This thesis details the design, fabrication, and measurement results of the filters and provides strategies to improve their performance. The performance of filter components, including the tunable capacitors and inductors, is characterized and compared to the state-of-the-art micromachined passive components. The silver inductors reported in this thesis exhibit the record high Q, and the silver bandpass filters show the minimum insertion loss that has been achieved on a CMOS-grade silicon substrate, to the best of our knowledge. Alternatively, tunable capacitors can be made in the bulk of silicon using a modified version of the high-aspect-ratio polysilicon and single crystal silicon (HARPSS) fabrication technique to obtain a larger capacitance density at the expense of a higher conductive loss. Using this process, a 15 pF two-port tunable capacitor is fabricated and tuned by 240% with the application of 3.5 V to the isolated actuator. Silver inductors can be post integrated with HARPSS tunable capacitors to obtain tunable filters in the very high frequency (VHF) range. The reported bandpass filters can be monolithically integrated with CMOS and have the potential to replace several transmit and receive acoustic filters currently used in cellular phones.

Ultra-broadband Monolithic Microwave Integrated Circuit (MMIC) amplifiers find applications in multi-gigabit communication systems for 5G and millimeter wave measurement instrumentation systems. The aim of the research was to achieve maximum bandwidth of operation of the amplifier from the foundry process used and high reverse isolation ( < -25.0 dB) across the whole bandwidth. To achieve this, several design variations of DC - 110 GHzMMIC Cascode TravellingWave Amplifier (TWA) on 100 nm AlGaAs/GaAs pHEMT process were done for application in next generation instrumentation and high data transfer rate (100 Gb/s) optical modulator systems. The foundry service and device models used for the design are of the WINPP10-10 process from WIN Semiconductor Corp., Taiwan, a commercial and highly stable process. The cut-off frequency ft and maximum frequency of oscillation fmax for this process are 135 GHz and 185 GHz respectively. Thus, the design was aimed at pushing the ultimate limits of operation for this process. The design specifications were targeted to have S21 = 9.0 to 10.0 ± 1.0 dB, S11 & S22 ≤ -10.0 dB and S12 ≤ -25.0 dB in the whole frequency range. In order to achieve the targeted RF performance, it is imperative to have accurate transistor models over the frequency range of operation, transistor configuration mode and operating bias points. Using smaller periphery transistors results in lower extrinsic & intrinsic input and output capacitances that lead to achieving very wide band performance. Thus, device sizes as small as 2x10 μm were used for the design. A cascode topology, which is a series connection of a common-source and common-gate field effect transistor (FET), was used to achieve large bandwidth of operation, high reverse isolation and high input and output impedance. Using very small periphery devices at cascode bias points posed limitation in the design in terms of accuracy of transistor models under these conditions, specifically at high frequencies i.e., above 50 GHz. One of the major systemrequirements for the application of MMIC ultra-broadband amplifiers in instrumentation is to achieve and maintain high reverse isolation (≤ -25.0 dB) over the whole frequency range of operation which cannot be achieved alone by the cascode topology and new design techniques have to be devised. These twomajor challenges, namely high frequency small periphery FET model modification & development and design technique to achieve high reverse isolation in ultra-broadband frequency range have been addressed in this research.

Ces travaux de thèse accompagnent le développement de nouvelles architectures d’interrupteurs monolithiques bidirectionnels en courant et en tension. L’une des voies technologiques proposées consiste à contrôler les propriétés électriques de l’interface de soudure Si-Si. Nous avons mis en évidence la nature complexe de l’activité électrique de l’interface avec l’existence d’un continuum d’états d’énergie au caractère recombinant. L’intégration d’une telle brique technologique nécessite alors la maîtrise de la passivation/décoration de l’interface par diffusion d’impuretés. La passivation des états d’interfaces par hydrogénation a montré une amélioration des propriétés électriques globales de l’interface de soudure avec une réduction de la dispersion des paramètres électriques. Une contamination contrôlée par diffusion de platine, nous a permis d’obtenir une désactivation, voire une compensation, du phosphore à l’interface, accompagnée d’une disparition des niveaux profonds. / 1-lydrophobic silicon direct wafer bonding is an interesting way to realize new devices, espccia1lhen it could substitutc for double-side lithography or give access tu buried layers during process. This study goes with the design of a monolithic switch bidirectional in current and voltage for household appliances. We investigate the electrical properties of hydrophobic silicon wafer bonded interface. We have shown the interface is composed of several electronic defects, due to lattice deformations and residual contaminations, generating deep levels with recombinant properties. Finally, this study is focused on its electrical characterization and how to control its electrical activity. Hydrogenation and platinum diffusion are performed at Iow temperature and underline the possibility to restore the phosphorus biilk doping level. Therefore, an appropriate thermal treatment could be used to passivate a bonded interface without any bulk contamination.

Cette thèse est dédiée à l’étude, à la réalisation et à la caractérisation de nouvelles périphéries de TRIAC. L’objet de cette recherche est de réduire l’espace occupé par la périphérie en tentant de conserver le même niveau de performances au blocage. Deux voies d’amélioration ont été poursuivies : l’une concerne la réalisation de caissons d’isolation par thermomigration d’aluminium, l’autre implique l’intégration du silicium poreux dans le caisson d’isolation. La thermomigration d’aluminium est une technique attractive permettant de remplacer les techniques de diffusion conventionnelles. Son industrialisation subit cependant quelques verrous technologiques, notamment le retrait des résidus aluminés et la formation de billes. Deux procédés de gravure ont été développés en vue d’enlever sélectivement l’ensemble de résidus. L’origine des billes a été analysée à l’aide d’observations expérimentales et de modélisations numériques. En utilisant un motif incluant des trous carrés aux intersections, des résultats encourageants ont été démontrés malgré une uniformité thermique encore optimisable. La deuxième voie d’innovation consiste à profiter des propriétés diélectriques du silicium poreux. Un procédé de masquage par fluoropolymère a été développé pour la localisation du silicium poreux. Les conditions d’anodisation adéquates ont été déterminées. La caractérisation de prototypes a montré des tenues au blocage largement améliorées par rapport à l’étude précédente. Bien que les tenues en tension nécessaires n’aient pas été atteintes, des courants de fuite inférieures à 10 μA ont été constatés jusqu’à plusieurs centaines de volts. / This thesis is dedicated to the study, the realization and the testing of “Planar” type TRIAC with novel peripheries. The aim of this research is to shrink the device periphery while maintaining the same level of blocking performances. Two paths of innovation have been pursued: one concerning Al-Si thermomigration for the production of through-wafer isolation walls, and the other involving porous silicon and its integration in the isolation walls. Al-Si thermomigration is an attractive mean allowing to replace conventional diffusion technologies. However, several remaining issues, such as the removal of the unintentional residues and the ball formation phenomenon, block its commercial application. Two different etching procedures have been developed in order to selectively remove all residues. The origin of the ball phenomenon has been analyzed using experimental observations and numerical modeling. By using a new pattern including square holes at intersections, encouraging results have been demonstrated in spite of an optimizable thermal uniformity. The second way of innovation is to take advantage of the dielectric properties of the porous silicon. A fluoropolymer masking process has been developed for local porous silicon formation. The appropriate anodization conditions have been determined. The characterization results showed improved blocking performances compared to the previous study. Although the necessary voltage requirements are not met, leakage currents of less than 10 μA have been observed up to several hundred volts.

Neste trabalho foi estudado o desenvolvimento de uma superfície modelo de silício monocristalino, SiO2/Si, modificada com organossilanos derivados de N-heterocíclicos que permitisse a imobilização de um complexo de coordenação, FeTIM. Estas superfícies modificadas poderão ser empregadas em estudos de reatividade frente a analitos de interesse, como o NO. Sob esse aspecto, a síntese desses novos silanos, contendo N-heterocíclicos, e o desenvolvimento de uma metodologia de formação dos filmes finos automontados, sobre a superfície de SiO2/Si, tornou-se de grande relevância na aplicabilidade deste trabalho. Para a obtenção dessas superfícies, fez-se necessária a compreensão dos parâmetros de formação dos filmes de silanos. Os parâmetros estudados foram os efeitos do tempo de adsorção, da concentração da solução dos silanos, da polaridade do solvente e do tamanho da cadeia alquílica do silano no processo de formação dos filmes. Deste modo, foi possível inferir sobre as alterações na morfologia e na estrutura química dos filmes formados, através de medidas de Espectroscopia de Fotoelétrons excitados por Raios-X (XPS), Microscopia de Força Atômica (AFM) e Microscopia Eletrônica de Varredura (MEV). A imobilização do complexo de FeTIM sobre a superfície organomodificada foi comprovada pela variação da linha de fotoemissão do Fe 2p nas medidas de XPS. / This work describes the study of model surfaces on oxidized silicon wafer, SiO2/Si, modified with N-heterocycles rings, that allows the grafting of a macrocycle iron complex, FeTIM, that could be used in reactivity studies, with biologically relevant molecules, as nitrogen monoxide (NO). On this way, the synthesis of these silanes and a new methodology of the formation of self-assembled monolayers had become a relevant question on this work applicability. These thin films contain silanes bearing nitrogenated Lewis bases on silicon surfaces. In order to obtain these modified surfaces, it was necessary a comprehensive study of the adsorption parameters of the thin films. The parameters studied were the effect of: adsorption time, the solution concentration, the role of the solvents polarity and the chain length alkylsilanes in the film formation. Then, it was possible to infer about the film\'s morphology differences and chemical structures by the XPS, AFM and MEV measurements. X-ray photoemission lines of Fe 2p were used to probe the iron chemical environment in the chemically adsorbed macrocycles complexes.

Future 450mm semiconductor wafer foundries are expected to produce billions of low cost, leading-edge processors, memories, and wireless sensors for Internet of Everything applications in smart cities, smart grids, and smart infrastructures. The problem has been a lack of wise investment decision making using traditional semiconductor industry models. The purpose of this study was to design decision-making models to conserve financial resources from conception to commercialization using real options to optimize production capacity, to defer an investment, and to abandon the project. The study consisted of 4 research questions that compared net present value from real option closed-form equations and binomial lattice models using the Black-Scholes option pricing theory. Three had focused on sensitivity parameters. Moore's second law was applied to find the total foundry cost. Data were collected using snowball sampling and face-to-face surveys. Original survey data from 46 Americans in the U.S.A. were compared to 46 Europeans in Germany. Data were analyzed with a paired-difference test and the Box-Behnken design was employed to create prediction models to support each hypothesis. Data from the real option models and survey findings indicate American 450mm foundries will likely capture greater value and will choose the differentiation strategy to produce premium chips, whereas higher capacity, cost leadership European foundries will produce commodity chips. Positive social change and global quality of life improvements are expected to occur by 2020 when semiconductors will be needed for the $14 trillion Internet of Everything market to create safe self-driving vehicles, autonomous robots, smart homes, novel medical electronics, wearable computers with streaming augmented reality information, and digital wallets for cashless societies.