As one of the major building blocks in a wireless receiver, the Analog-to-Digital Interface (ADI) provides link and transition between the analog Radio Frequency (RF) frontend and the baseband Digital Signal Processing (DSP) module. The rapid development of the radio technologies raises new design challenges for the receiver ADI implementation. Requirements, such as power consumption optimization, multi-standard compatibility, fast settling capability and wide signal bandwidth capacity, are often encountered in a low voltage ADI design environment. Previous research offers ADI design schemes that emphasize individual merit. A systematic ADI design methodology is, however, not suffciently studied. In this work, the ADI design for two receiver systems are employed as research vehicles to provide solutions for different ADI design issues. A zero-crossing demodulator ADI is designed in the 0.35µm CMOS technology for the Bluetooth receiver to provide fast settling. Architectural level modification improves the process variation and the Local Oscillation (LO) frequency offset immunity of the demodulator. A 16.2dB Signal-to-Noise Ratio (SNR) at 0.1% Bit Error Rate (BER) is achieved with less than 9mW power dissipation in the lab measurement. For ADI in the 802.11b/Bluetooth dual-mode receiver, a configurable time-interleaved pipeline Analog-to-Digital-Converter (ADC) structure is adopted to provide the required multi-standard compatibility. An online digital calibration scheme is also proposed to compensate process variation and mismatching. The prototype chip is fabricated in the 0.25µm BiCMOS technology. Experimentally, an SNR of 60dB and 64dB are obtained under the 802.11b and Bluetooth receiving modes, respectively. The power consumption of the ADI is 20.2mW under the 802.11b receiving mode and 14.8mW under the Bluetooth mode. In this dissertation, each step of the receiver ADI design procedure, from system level optimization to the transistor level implementation and lab measurement, is illustrated in detail. The observations are carefully studied to provide insight on receiver ADI design issues. The ADI design for the Ultra-Wide Band (UWB) receiver is also studied at system level. Potential ADI structure is proposed to satisfy the wide signal bandwidth and high speed requirement for future applications.

<p>The goals for most of today’s receiver system are sampling at high-speed, with high resolution and with as few errors as possible. This master thesis describes the design of a high-speed sampling system with"state-of-the-art"components available on the market. The system is designed with a parallel Analog-to-digital converter (ADC) architecture, also called time interleaving. It aims to increase the sampling speed of the system. The system described in this report uses four 12-bits ADCs in parallel. Each ADC can sample at 125 MHz and the total sampling speed will then theoretically become 500 Ms/s. The system has been implemented and manufactured on a printed circuit board (PCB). Up to four boards can be connected in parallel to get 2 Gs/s theoretically. </p><p>In an approach to increase the systems performance even further, a timing error estimation algorithm will be used on the sampled data. This algorithm estimates the timing errors that occur when sampling with non-uniform time interval between samples. After the estimations, the sampling clocks can be adjusted to correct the errors. </p><p>This thesis is concerning some ADC theory, system design and PCB implementation. It also describes how to test and measure the system’s performance. No measurement results are presented in this thesis because measurements will be done after this project. The last part of the thesis discusses future improvementsto achieve even higher performance.</p>

The object of the thesis was to develop a simple method of the ADC quality evaluation of computer audio systems, which does not require a special apparatus, and software for its realization. To correct the ADC ENOB measurement methodology recommended in the IEEE Std 1241-2000. By applying the recommended method, to investigate possibilities of formation and application of new test analog signals for ADC investigation. To show the possibilities of untraditional computer audio systems application for measurements.

The object of the thesis was to develop a simple method of the ADC quality evaluation of computer audio systems, which does not require a special apparatus, and software for its realization. To correct the ADC ENOB measurement methodology recommended in the IEEE Std 1241-2000. By applying the recommended method, to investigate possibilities of formation and application of new test analog signals for ADC investigation. To show the possibilities of untraditional computer audio systems application for measurements.

The miniaturization of dc–dc switch-mode power supplies (SMPS) is of a key importance in volume-sensitive portable devices, such as cell phones, tablet computers, and digital cameras. In these systems, multiple SMPS are required to provide well regulated voltage and power to various electronic components such as the central processing unit (CPU) and random-access memory (RAM). The combined volume, weight, and surface area footprint of these SMPS is usually the largest component. Traditionally, SMPS volume reduction has been achieved through increased switching frequencies; however, for power-sensitive applications this is undesirable due to the increased switching losses. This thesis presents two alternative, power-efficient, SMPS miniaturization methods: one control and one topology based. The presented controller recovers from load transients with virtually minimum possible output voltage deviation, reducing the reactive component size. The controller utilizes a simple algorithm, requiring no knowledge of the converter parameters and virtually no processing power. The simplicity of the control concept enabled the design of an area and power efficient integrated circuit (IC) implementation. The entire IC is implemented in a CMOS 0.18µm process on a 0.26 mm2 silicon area, which is comparable to the state-of-the-art analog solutions. For the experimental system the deviation (output capacitor size) is about four times smaller than that of a fast PID compensator having a 1/10th of the switching frequency bandwidth. The second solution is a complementary converter topology that has a smaller output filter volume, improved dynamic response, and lower switching losses compared to the state-of-the-art solutions. To reduce the volume and switching losses, the input-to-output voltage difference is decreased with a capacitive attenuator that replaces the input filter capacitor and has approximately the same volume. Both the attenuator and the downstream buck converter share the same set of switches, minimizing conduction losses. A single multi-mode digital controller governs operation of both stages, seamlessly regulating the output and input center-tap voltages. Experiments with a 5–1.5-V, 2.5-A, 1-MHz prototype show that, compared to the conventional buck, the merged topology has 43% smaller inductor, 36% smaller output capacitor, up to 30% lower power losses, and a 25% faster transient response.

The miniaturization of dc–dc switch-mode power supplies (SMPS) is of a key importance in volume-sensitive portable devices, such as cell phones, tablet computers, and digital cameras. In these systems, multiple SMPS are required to provide well regulated voltage and power to various electronic components such as the central processing unit (CPU) and random-access memory (RAM). The combined volume, weight, and surface area footprint of these SMPS is usually the largest component. Traditionally, SMPS volume reduction has been achieved through increased switching frequencies; however, for power-sensitive applications this is undesirable due to the increased switching losses. This thesis presents two alternative, power-efficient, SMPS miniaturization methods: one control and one topology based. The presented controller recovers from load transients with virtually minimum possible output voltage deviation, reducing the reactive component size. The controller utilizes a simple algorithm, requiring no knowledge of the converter parameters and virtually no processing power. The simplicity of the control concept enabled the design of an area and power efficient integrated circuit (IC) implementation. The entire IC is implemented in a CMOS 0.18µm process on a 0.26 mm2 silicon area, which is comparable to the state-of-the-art analog solutions. For the experimental system the deviation (output capacitor size) is about four times smaller than that of a fast PID compensator having a 1/10th of the switching frequency bandwidth. The second solution is a complementary converter topology that has a smaller output filter volume, improved dynamic response, and lower switching losses compared to the state-of-the-art solutions. To reduce the volume and switching losses, the input-to-output voltage difference is decreased with a capacitive attenuator that replaces the input filter capacitor and has approximately the same volume. Both the attenuator and the downstream buck converter share the same set of switches, minimizing conduction losses. A single multi-mode digital controller governs operation of both stages, seamlessly regulating the output and input center-tap voltages. Experiments with a 5–1.5-V, 2.5-A, 1-MHz prototype show that, compared to the conventional buck, the merged topology has 43% smaller inductor, 36% smaller output capacitor, up to 30% lower power losses, and a 25% faster transient response.

With increase in frequency and convergence toward mixed signal systems, supplying stable voltages to integrated circuits and blocking noise coupling in the systems are major problems. Electromagnetic band gap (EBG) structures have been in the limelight for power/ground noise isolation in mixed signal applications due to their capability to suppress unwanted electromagnetic mode transmission in certain frequency bands. The EBG structures have proven effective in isolating the power/ground noise in systems that use a common power supply. However, while the EBG structures have the potential to present many advantages in noise suppression applications, there is no method in the prior art that enables reliable and efficient synthesis of these EBG structures. Therefore, in this research, a novel EBG synthesis method for mixed signal applications is presented. For one-dimensional periodic structures, three new approaches such as current path approximation method, border to border radius, power loss method have been introduced and combined for synthesis. For two-dimensional EBG structures, a novel EBG synthesis method using genetic algorithm (GA) has been presented. In this method, genetic algorithm (GA) is utilized as a solution-searching technique. Synthesis procedure has been automated by combining GA with multilayer finite-difference method and dispersion diagram analysis method. As a real application for EBG structures, EBG structures have been applied to a GHz ADC load board design for power/ground noise suppression.

Le domaine de l'instrumentation des capteurs est en constante évolution. Ce travail propose la conception des éléments clefs qui constituent les chaines d'instrumentations de capteurs d'aujourd'hui au travers de 3 applications concrètes. La première application est la mesure de vitesse et de position, par exemple dans un roulement. Nous présentons la conception et la réalisation d'un circuit analogique pour le conditionnement d'un capteur de type magnétorésistif. Ce capteur mesure le champ magnétique généré par les pôles magnétiques d'une roue codeuse. Le circuit est optimisé en bruit, en consommation et travaille sur une bande passante de plusieurs kHz. Pour compenser la dispersion des capteurs, le circuit permet des réglages d'offset et une calibration de gains. Il contient également une mémoire de type OTP (One Time Programmable Memory) qui sauvegarde les réglages associés au capteur. La deuxième application est la mesure de signaux de type EcoG afin d'interfacer le cerveau humain. Nous décrivons la conception et la réalisation d'un convertisseur Analogique/Numérique de type SAR. Il possède un convertisseur numérique analogique capacitif avec une capacité d'atténuation afin de réduire le nombre total de condensateur et ainsi la consommation. Le comparateur possède une entrée rail-to-rail et un système de préamplification avec auto zéro pour diminuer l'offset. Sa consommation est de 86µW pour une vitesse de 24Ks/S et 12bits de résolution. Enfin la troisième application est la mesure de pression stationnaire sur la voilure des avions afin d'en connaître les contraintes. Nous décrivons l'étude architecturale d'un convertisseur sigma-delta permettant d'atteindre une grande résolution pour des signaux de faible fréquence. Il sera de type incrémentale et répondra à des applications de type instrumentation de capteur. Sa résolution est de 16bits ENOB pour une fréquence maximale d'entrée de 100Hz et minimale de sortie d'1Ks/S. Le mode incrémental permettra d'obtenir une sortie en réponse à une requête de manière asynchrone. Une modélisation de chaque élément du système complet convertisseur plus capteur a été effectuée sous Matlab. L'étude de la partie filtrage numérique du convertisseur et l'optimisation de son implémentation numérique sont présentées. Cette étude architecturale complète aboutit au dimensionnement de chaque élément pour répondre au cahier des charges de l'application . / The domain of sensors instrumentation is constantly evolving. The present work proposes the design of the key elements conception which constitute the instrumentations chains of current sensors through 3 concrete applications. The first application is speed and position measurement, for example in a wheel bearing. We present the design and realization of an analogical circuit for the conditioning of magneto resistive sensor. This sensor measures the magnetic field generated by the coding wheel magnetic poles inside the bearing. The circuit is noise and power consumption optimized on a bandwidth of few kHz. To compensate sensors variability, the circuit includes offset regulations and gains. It also contains an OTP (One Time Programmable) memory which backs up the associated sensor regulations. The second application is the measurement of EcoG's signals to interface with the human brain. We describe the design and realization of SAR ADC. It is composed of a capacitive DAC with an attenuation capacitor to reduce the total number of condensers and, in doing so, to reduce power consumption. The comparator is composed by a rail-to-rail input and multistage preamplification and output offset storage. ADC total power consumption is 86µW for 24Ks/S speed and 12bits resolution. Finally the third application is the pressure measurement on aircraft wings. We describe the architectural study sigma-delta incremental ADC which reaches high resolution for low band pass signals. Its resolution is 16bits ENOB for a maximal input frequency of 100Hz and an output speed of 1Ks/S. The incremental mode leads to obtain output code in answer to asynchronous requests. Each system element (converter plus sensors) has been matlab modelled. The converter digital filtering study and its digital implementation optimization are presented. This complete architectural study concludes with the sizing of each element in order to answer the technical specifications of the application.

Conversores analógico-digitais (ADCs) têm papel fundamental na implementação dos sistemas-em-chip, do inglês System-on-Chip (SoC), atuais. Em razão dos requisitos destes sistemas e dos compromissos entre as características fundamentais dos ADCs, como largura de banda, consumo de energia e exatidão, diversas topologias e estratégias para sua implementação em circuitos integrados (CIs) têm sido desenvolvidas através dos tempos. Dentre estas topologias, os conversores sigma-delta (SDC) têm se destacado pela versatilidade, aliada ao baixo consumo e excelente exatidão. Inicialmente desenvolvidos e empregados para a conversão de sinais de baixa frequência e com operação em tempo discreto (DT), esta classe de conversores têm evoluído e nos últimos anos está sendo desenvolvida para operar em tempo contínuo e ser empregada na conversão de sinais com frequências de centenas de kHz a dezenas de MHz. Neste trabalho, os moduladores sigma-delta em tempo contínuo (SDMs-CT) são estudados, visando sua aplicação à conversão analógico-digital (AD). Os SDMs-CT oferecem vantagens significativas sobre seus homólogos em tempo discreto, como menor consumo de energia, maior largura de banda do sinal de entrada e filtro anti-alias, do inglês anti-alias filter (AAF), implícito. Entretanto, os SDMs-CT apresentam limitações adicionais, responsáveis pela degradação de seu desempenho, como os efeitos do jitter do sinal de relógio, o atraso excessivo do laço de realimentação, do inglês Excess Loop Delay (ELD), e as limitações impostas aos integradores analógicos. Após o estudo e análise de SDMs-CT e de suas limitações, foi desenvolvido um modelo comportamental no ambiente Matlab/Simulink R , que permite a simulação do impacto destas limitações no modulador, possibilitando a obtenção de uma estimativa mais aproximada do seu desempenho. Com base nestas simulações foi possível a determinação das especificações mínimas de cada bloco analógico que compõe o modulador (como o slew rate, a frequência de ganho unitário (fu) e o ganho DC dos amplificadores operacionais utilizados nos integradores) e os valores toleráveis de ELD e jitter do sinal de relógio. Adicionalmente, neste trabalho foi desenvolvida uma metodologia para simulação de SDMs-CT compostos por DACs a capacitor chaveado e resistor, do inglês Switched-Capacitor-Resistor (SCR). Com base neste modelo e no estudo das diferentes topologias de SDMs, um circuito foi desenvolvido para aplicação em receptores de RF, sendo do tipo passa-baixas de laço único, do inglês single-loop, single-bit, de terceira ordem, voltado ao baixo consumo de energia. Este circuito foi desenvolvido em tecnologia CMOS IBM de 130 nanômetros, tendo sido enviado para fabricação. Através das simulações pós-leiaute realizadas espera-se que seu desempenho fique próximo ao que tem sido publicado recentemente sobre SDMs-CT passa-baixas de laço único e single-bit. / Analog-to-Digital Converters (ADCs) play a fundamental role in the implementation of current systems-on-chip (SoC). Due to the requirements of these systems and the tradeoffs between the main ADCs characteristics, such as signal bandwidth, power consumption and accuracy, many topologies and strategies for their implementation in integrated circuits (ICs) have been developed through the ages. Among these topologies, the sigmadelta converters (SDC) have highlighted the versatility combined with low power consumption and excellent accuracy. Initially developed and used for the conversion of low frequency signals and operation in the discrete time (DT) domain, this class of converters have been evolved and developed over the past to operate in continuous time domain for the conversion of signals with frequencies of hundreds of kHz up to tens of MHz. In this work, continuous time sigma-delta modulators (CT-SDMs) are studied focusing its application to the analog-to-digital (AD) conversion. CT-SDMs offer significant advantages over their discrete-time counterparts, such as lower power consumption, higher input signal bandwidth and implicit anti-alias filter (AAF). However, CT-SDMs present additional limitations that are responsible for their performance degradation, such as the clock jitter, Excess Loop Delay (ELD) and the limitations imposed on the analog integrators. After the study and analysis of CT-SDMs and their performance limitations, a behavioral model approach was developed in the Matlab/Simulink R environment, which allows the simulation of the limitations impact on the modulator, allowing the obteinment of a more accurate estimate of its performance. Based on these simulations it was possible to determine the minimum specifications for each block that composes the analog modulator (such as slew rate, the unity gain frequency (fu) and the DC gain of the operational amplifiers used in integrators) and tolerable values of ELD and clock jitter. Additionally, it was developed in this work a methodology for simulate CT-SDMs with Switched-Capacitor- Resistor (SCR) DACs that provide exponential waveforms. Based on this model and the study of different SDMs topologies, it was developed a low-pass, single-loop, single-bit, third order circuit focused on low-power intended for application in RF receivers. This circuit was developed in an IBM 130 nanometers CMOS technology, and was send to manufacturing. Based on the post-layout simulations it is expected to have performance close to what has been recently published of low-pass, single-loop, single-bit CT-SDMs.

Made available in DSpace on 2015-05-08T14:57:18Z (GMT). No. of bitstreams: 1 arquivototal.pdf: 3795959 bytes, checksum: 7a11a6cf0b41c67297d55642c2b80df3 (MD5) Previous issue date: 2014-02-21 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - CAPES / In this work, we analyse different architectures of analog-to-digital converters (ADC) and propose an architecture based on sampling by crossing levels and adaptive quantization step, aiming at reducing the energy required to convert and process specific signals. The proposed architecture has parameters which can be dynamically configured by the user, as to adapt the conversion process to the signal being sampled and to the requirements of power consumption of the target application. The architecture was modeled and simulated using Matlab, and used to convert several test signals, of which an ECG signal. The use of the proposed architecture resulted in SNR improvements of up to 10dB if compared against uniform (periodic) sampling. The digital logic was implemented in FPGA from a SystemVerilog description functionally compatible with the Matlab model, and the analog part was implemented with discrete components. / Neste trabalho, faz-se uma análise de diferentes arquiteturas de conversores analógico-digitais, e propõe-se uma arquitetura de conversor analógico-digital baseado em amostragem por cruzamento de níveis (não-uniforme) com adaptação do passo de quantização, com o objetivo de reduzir o consumo de energia requerido pela conversão analógica-digital e processamento de sinais com características específicas. A arquitetura proposta possui parâmetros que podem ser configurados dinamicamente pelo usuário, a fim de que o processo de conversão se adeque às características do sinal a ser amostrado e aos requerimentos de consumo de energia da aplicação. A arquitetura foi modelada e simulada em MatLab, tendo sido utilizada na conversão de diversos sinais de teste, dentre os quais um sinal típico de eletrocardiograma. Verificou-se que a amostragem não-uniforme com adaptação do passo de quantização proposta resultou em um aumento da relação sinal-ruído do sinal amostrado de até 10dB quando comparado com a amostragem uniforme. A implementação da parte digital foi feita em FPGA a partir de uma descrição em SystemVerilog funcionalmente compatível com o modelo em Matlab, e a parte analógica foi implementada com componentes discretos.