Behaviour occurs in time, and precise timing in the range of seconds and fractions of seconds is for most living organisms necessary for successful interaction with the environment. Our ability to time discrete actions and to predict events on the basis of prior events indicates the existence of an internal timing mechanism. The nature of this mechanism provides essential constraints on models of the functional organisation of the brain. The present work indicates that there are discontinuities in the function of time close to 1 s and 1.4 s, both in the amount of drift in a series of produced intervals (Study I) and in the detectability of drift in a series of sounds (Study II). The similarities across different tasks further suggest that action and perceptual judgements are governed by the same (kind of) mechanism. Study III showed that series of produced intervals could be characterised by different amounts of positive fractal dependency related to the aforementioned discontinuities. In conjunction with other findings in the literature, these results suggest that timing of intervals up to a few seconds is strongly dependent on previous intervals and on the duration to be timed. This argues against a clock-counter mechanism, as proposed by scalar timing theory, according to which successive intervals are random and the size of the timing error conforms to Weber's law. A functional model is proposed, expressed in an autoregressive framework, which consists of a single-interval timer with error corrective feedback. The duration-specificity of the proposed model is derived from the order of error correction, as determined by a semi-flexible temporal integration span.

The telomeres are specialized structures at the end of the chromosomes composed of the repeated DNA sequence (TTAGGG)n and specific proteins bound to the DNA. The telomeres protect the chromosomes from degradation and end to end fusions. Due to the end-replication problem, the telomeric DNA shortens every cell division, forcing the cells into senescence at a critical telomere length. This process can be counteracted by activating a specialized enzyme, telomerase, which adds telomeric repeats to the chromosome ends leading to an extended or infinite cellular life span. Telomerase activity is absent in most somatic tissues but is found in germ cells, stem cells, activated lymphocytes and the vast majority of tumor cells and permanent cell lines. Hence, telomerase has been suggested as a target for cancer treatment as malignant cells almost exclusively express the enzyme and in that context telomere length measurements will be of great importance. Telomere length is traditionally measured with a Southern blot based technique. A new method for telomere analysis of cells in suspension, called flow-FISH, was developed based on fluorescence in situ hybridization using a telomeric peptide nucleic acid (PNA) probe, DNA staining with propidium iodide and quantification by flow cytometry. Flow-FISH had high reproducibility and the telomere length measurements showed good correlation with Southern blotting results. The flow-FISH technique also allows studies of cells in specific phases of the cell cycle and the replication timing of telomeric, centromeric and other repetitive sequences were analyzed in a number of cells. Like previous studies, centromeres were shown to replicate late in S phase while the telomere repeats were found to replicate early in S phase or concomitant with the bulk DNA, which is opposite to the patterns described in yeast. In benign immunopurified lymphocytes from tonsils, high telomerase activity was found in germinal center (GC) B cells. This population also had high hTERT mRNA levels and displayed a telomere elongation as shown by flow-FISH and Southern blotting. Combined immunophenotyping and flow-FISH on unpurified tonsil cells confirmed the results. Chronic lymphocytic leukemia (CLL), the most common leukemia in adults, can be divided into pre-GC CLL, characterized by unmutated immunoglobulin VH genes and worse prognosis, and post-GC CLL, with mutated VH genes and better prognosis. In 61 cases of CLL, telomere length was measured with Southern blotting and VH gene mutation status was analyzed. A new association was found between VH mutation status and telomere length, where cases with longer telomeres and mutated VH genes (post-GC CLL) had better prognosis than CLL with short telomeres and unmutated VH genes (pre-GC CLL). A larger study of 112 CLL cases was performed using flow-FISH. The same correlation between telomere length and VH mutation status was found but gender seemed to be of importance as telomere length was a significant prognostic factor for the male CLL patients but not in the female group. Age of the patients and spread of disease seemed to affect the prognostic value of VH gene mutation status.

The last few decades have been a very exciting period in thedevelopment of micro-electronics and brought us to the brink ofimplementing entire systems on a single chip, on a hithertounimagined scale. However an unforeseen challenge has croppedup in the form of managing wires, which have become the mainbottleneck in performance, masking the blinding speed of activedevices. A major problem is that increasingly complicatedeffects need to be modelled, but the computational complexityof any proposed model needs to be low enough to allow manyiterations in a design cycle. This thesis addresses the issue of closed form modelling ofthe response of coupled interconnect systems. Following astrict mathematical approach, second order models for thetransfer functions of coupled RC trees based on the first andsecond moments of the impulse response are developed. The2-pole-1-zero transfer function that is the best possible fromthe available information is obtained for the signal path fromeach driver to the output in multiple aggressor systems. Thisallows the complete response to be estimated accurately bysumming up the individual waveforms. The model represents theminimum complexity for a 2-pole-1-zero estimate, for this classof circuits. Also proposed are new techniques for the optimisation ofwires in on-chip buses. Rather than minimising the delay overeach individual wire, the configuration that maximises thetotal bandwidth over a number of parallel wires isinvestigated. It is shown from simulations that there is aunique optimal solution which does not necessarily translate tothe maximum possible number of wires, and in fact deviatesconsiderably from it when the resources available for repeatersare limited. Analytic guidelines dependent only on processparameters are derived for optimal sizing of wires andrepeaters. Finally regular tiled architectures with a commoncommunication backplane are being proposed as being the mostefficient way to implement systems-on-chip in the deepsubmicron regime. This thesis also considers the feasibility ofimplementing a regular packet-switched network-on-chip in atypical future deep submicron technology. All major physicalissues and challenges are discussed for two differentarchitectures and important limitations are identified.

Most engineering systems are highly nonlinear in nature and thus one could not develop efficient mathematical models for these systems. Artificial neural networks, which are used in estimation, filtering, identification and control in technical literature, are considered as universal modeling and functional approximation tools. Unfortunately, developing a well trained monolithic type neural network (with many free parameters/weights) is known to be a daunting task since the process of loading a specific pattern (functional relationship) onto a generic neural network is proven to be a NP-complete problem. It implies that if training is conducted on a deterministic computer, the time required for training process grows exponentially with increasing size of the free parameter space (and the training data in correlation). As an alternative modeling technique for nonlinear dynamic systems / this thesis proposed a general methodology for structured neural network topologies and their corresponding applications are realized. The main idea behind this (rather classic) divide-and-conquer approach is to employ a priori information on the process to divide the problem into its fundamental components. Hence, a number of smaller neural networks could be designed to tackle with these elementary mapping problems. Then, all these networks are combined to yield a tailored structured neural network for the purpose of modeling the dynamic system under study accurately. Finally, implementations of the devised networks are taken into consideration and the efficiency of the proposed methodology is tested on four different types of mechanical systems.

Cars, trains, trucks, telecom networks and industrial robots are examples of products relying on complex embedded software systems, running on embedded computers. Such systems may consist of millions of lines of program code developed by hundreds of engineers over many years, often decades. Over the long life-cycle of such systems, the main part of the product development costs is typically not the initial development, but the software maintenance, i.e., improvements and corrections of defects, over the years. Of the maintenance costs, a major cost is the verification of the system after changes has been applied, which often requires a huge amount of testing. However, today's techniques are not sufficient, as defects often are found post-release, by the customers. This area is therefore of high relevance for industry. Complex embedded systems often control machinery where timing is crucial for accuracy and safety. Such systems therefore have important requirements on timing, such as maximum response times. However, when maintaining complex embedded software systems, it is difficult to predict how changes may impact the system's run-time behavior and timing, e.g., response times.Analytical and formal methods for timing analysis exist, but are often hard to apply in practice on complex embedded systems, for several reasons. As a result, the industrial practice in deciding the suitability of a proposed change, with respect to its run-time impact, is to rely on the subjective judgment of experienced developers and architects. This is a risky and inefficient, trial-and-error approach, which may waste large amounts of person-hours on implementing unsuitable software designs, with potential timing- or performance problems. This can generally not be detected at all until late stages of testing, when the updated software system can be tested on system level, under realistic conditions. Even then, it is easy to miss such problems. If products are released containing software with latent timing errors, it may cause huge costs, such as car recalls, or even accidents. Even when such problems are found using testing, they necessitate design changes late in the development project, which cause delays and increases the costs. This thesis presents an approach for impact analysis with respect to run-time behavior such as timing and performance for complex embedded systems. The impact analysis is performed through optimizing simulation, where the simulation models are automatically generated from the system implementation. This approach allows for predicting the consequences of proposed designs, for new or modified features, by prototyping the change in the simulation model on a high level of abstraction, e.g., by increasing the execution time for a particular task. Thereby, designs leading to timing-, performance-, or resource usage problems can be identified early, before implementation, and a late redesigns are thereby avoided, which improves development efficiency and predictability, as well as software quality. The contributions presented in this thesis is within four areas related to simulation-based analysis of complex embedded systems: (1) simulation and simulation optimization techniques, (2) automated model extraction of simulation models from source code, (3) methods for validation of such simulation models and (4) run-time recording techniques for model extraction, impact analysis and model validation purposes. Several tools has been developed during this work, of which two are in commercialization in the spin-off company Percepio AB. Note that the Katana approach, in area (2), is subject for a recent patent application - patent pending. / PROGRESS

Side-Channel Analysis plays an important role in cryptology, as it represents an important class of attacks against cryptographic implementations, especially in the context of embedded systems such as hand-held mobile devices, smart cards, RFID tags, etc. These types of attacks bypass any intrinsic mathematical security of the cryptographic algorithm or protocol by exploiting observable side-effects of the execution of the cryptographic operation that may exhibit some relationship with the internal (secret) parameters in the device. Two of the main types of side-channel attacks are timing attacks or timing analysis, where the relationship between the execution time and secret parameters is exploited; and power analysis, which exploits the relationship between power consumption and the operations being executed by a processor as well as the data that these operations work with. For power analysis, two main types have been proposed: simple power analysis (SPA) which relies on direct observation on a single measurement, and differential power analysis (DPA), which uses multiple measurements combined with statistical processing to extract information from the small variations in power consumption correlated to the data. In this thesis, we propose several countermeasures to these types of attacks, with the main themes being timing analysis and SPA. In addition to these themes, one of our contributions expands upon the ideas behind SPA to present a constructive use of these techniques in the context of embedded systems debugging. In our first contribution, we present a countermeasure against timing attacks where an optimized form of idle-wait is proposed with the goal of making the observable decryption time constant for most operations while maintaining the overhead to a minimum. We show that not only we reduce the overhead in terms of execution speed, but also the computational cost of the countermeasure, which represents a considerable advantage in the context of devices relying on battery power, where reduced computations translates into lower power consumption and thus increased battery life. This is indeed one of the important themes for all of the contributions related to countermeasures to side- channel attacks. Our second and third contributions focus on power analysis; specifically, SPA. We address the issue of straightforward implementations of binary exponentiation algorithms (or scalar multiplication, in the context of elliptic curve cryptography) making a cryptographic system vulnerable to SPA. Solutions previously proposed introduce a considerable performance penalty. We propose a new method, namely Square-and-Buffered- Multiplications (SABM), that implements an SPA-resistant binary exponentiation exhibiting optimal execution time at the cost of a small amount of storage --- O(\sqrt(\ell)), where \ell is the bit length of the exponent. The technique is optimal in the sense that it adds SPA-resistance to an underlying binary exponentiation algorithm while introducing zero computational overhead. We then present several new SPA-resistant algorithms that result from a novel way of combining the SABM method with an alternative binary exponentiation algorithm where the exponent is split in two halves for simultaneous processing, showing that by combining the two techniques, we can make use of signed-digit representations of the exponent to further improve performance while maintaining SPA-resistance. We also discuss the possibility of our method being implemented in a way that a certain level of resistance against DPA may be obtained. In a related contribution, we extend these ideas used in SPA and propose a technique to non-intrusively monitor a device and trace program execution, with the intended application of assisting in the difficult task of debugging embedded systems at deployment or production stage, when standard debugging tools or auxiliary components to facilitate debugging are no longer enabled in the device. One of the important highlights of this contribution is the fact that the system works on a standard PC, capturing the power traces through the recording input of the sound card.

From studies of the circadian clock in the plant model species Arabidopsis (Arabidopsis thaliana), a number of important properties and components have emerged. These include the genes CIRCADIAN CLOCK ASSOCIATED 1 (CCA1), GIGANTEA (GI), ZEITLUPE (ZTL) and TIMING OF CAB EXPRESSION 1 (TOC1 also known as PSEUDO-RESPONSE REGULATOR 1 (PRR1)) that via gene expression feedback loops participate in the circadian clock. Here, we present results from ectopic expression of four Norway spruce (Picea abies) putative homologs (PaCCA1, PaGI, PaZTL and PaPRR1) in Arabidopsis, their flowering time, circadian period length, red light response phenotypes and their effect on endogenous clock genes were assessed. For PaCCA1-ox and PaZTL-ox the results were consistent with Arabidopsis lines overexpressing the corresponding Arabidopsis genes. For PaGI consistent results were obtained when expressed in the gi2 mutant, while PaGI and PaPRR1 expressed in wild type did not display the expected phenotypes. These results suggest that protein function of PaCCA1, PaGI and PaZTL are at least partlyconserved compared to Arabidopsis homologs, however further studies are needed to reveal the protein function of PaPRR1. Our data suggest that components of thethree-loop network typical of the circadian clock in angiosperms were present beforethe split of gymnosperms and angiosperms.

The goals for most of today’s receiver system are sampling at high-speed, with high resolution and with as few errors as possible. This master thesis describes the design of a high-speed sampling system with"state-of-the-art"components available on the market. The system is designed with a parallel Analog-to-digital converter (ADC) architecture, also called time interleaving. It aims to increase the sampling speed of the system. The system described in this report uses four 12-bits ADCs in parallel. Each ADC can sample at 125 MHz and the total sampling speed will then theoretically become 500 Ms/s. The system has been implemented and manufactured on a printed circuit board (PCB). Up to four boards can be connected in parallel to get 2 Gs/s theoretically. In an approach to increase the systems performance even further, a timing error estimation algorithm will be used on the sampled data. This algorithm estimates the timing errors that occur when sampling with non-uniform time interval between samples. After the estimations, the sampling clocks can be adjusted to correct the errors. This thesis is concerning some ADC theory, system design and PCB implementation. It also describes how to test and measure the system’s performance. No measurement results are presented in this thesis because measurements will be done after this project. The last part of the thesis discusses future improvementsto achieve even higher performance.

Timing offsets result from the use of real clocks that are non-ideal in sampling intervals. These offsets also known as timing jitter were shown to degrade the performance of the two forms of UWB systems impulse radio and orthogonal frequency division multiplexing (OFDM)-based UWB. It was shown that for impulse radio, timing jitter distorts the correlation property of the transmitted signal and the resulting performance loss is proportional to the root-mean-square (RMS) value of the timing jitter. For the OFDM-based UWB, timing jitter introduced inter-channel interference (ICI) and the performance loss was dependent on the product of the bandwidth and the RMS of the timing jitter. A number of techniques were proposed for mitigating the performance degradation in each form of UWB. Specifically, for impulse radio, the methods of pulse shaping and sample averaging were provided, whereas for OFDM-based UWB, oversampling and adaptive modulation were given. Through analysis and simulation, it was shown that substantial gain in signal power-to-noise ratio can be achieved using these jitter-reduction methods.

Networks-on-Chip (NoCs) are a general purpose, scalable replacement for shared medium wired interconnects offering many practical applications in industry. Dynamic Voltage Frequency Scaling (DVFS) is a technique whereby a chip?s voltage-frequency levels are varied at run time, often used to conserve dynamic power. Various DVFSbased NoC optimization techniques have been proposed. However, due to the resources required to validate architectural decisions through prototyping, few are implemented. As a result, designers are faced with a lack of insight into potential power savings or performance gains at early architecture stages. This thesis proposes a DVFS aware NoC simulator with support for per node power-frequency modeling to allow fine-tuning of such optimization techniques early on in the design cycle. The proposed simulator also provides a framework for benchmarking various candidate strategies to allow selective prototyping and optimization. As part of the research, DVFS extensions were built for an existing NoC performance simulator and released for public use. This thesis presents some of the preliminary results from our simulator that show the average power consumed per node for all the benchmarks in SPLASH 2 benchmark suite [74] to be quite similar to each other. This thesis also serves as a technical manual for the simulator extensions. Important links for downloading and using the simulator are provided at the end of this document in Appendix C.