With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation. Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can frame data transfers differently. The IBUS protocol provides two novel transfer modes – the block and state modes, and is also backward compatible with the conventional linear mode. In order to evaluate the bus performance automatically and accurately, we also proposed an evaluation methodology based on the standard circuit design flow. Experimental results show that the IBUS based design uses the least hardware resource and reduces energy consumption to a half of an AMBA Advanced High-Performance Bus (AHB) and Advanced eXensible Interface (AXI). Additionally, the valid bandwidth of the IBUS based design is 2.3 and 1.6 times, respectively, compared with the AHB and AXI based implementations. As IoT advances, privacy and security issues become top tier concerns in addition to the high performance requirement of embedded chips. To leverage limited resources for tiny size chips and overhead cost for complex security mechanisms, we further proposed an advanced IBUS architecture to provide a structural support for the block-based AES algorithm. Our results show that the IBUS based AES-encrypted design costs less in terms of hardware resource and dynamic energy (60.2%), and achieves higher throughput (x1.6) compared with AXI. Effectively dealing with the automation in design and verification for mixed-signal integrated circuits is a critical problem, particularly when the bus architecture is new. Therefore, we further proposed a configurable and synthesizable IBUS design methodology. The flexible structure, together with bus wrappers, direct memory access (DMA), AES engine, memory controller, several mixed-signal verification intellectual properties (VIPs), and bus performance models (BPMs), forms the basic for integrated circuit design, allowing engineers to integrate application-specific modules and other peripherals to create complex SoCs.

After a brief review of machine learning techniques and applications, this Ph.D. thesis examines several approaches for implementing machine learning architectures and algorithms into hardware within our laboratory. From this interdisciplinary background support, we have motivations for novel approaches that we intend to follow as an objective of innovative hardware implementations of dynamically self-reconfigurable logic for enhanced self-adaptive, self-(re)organizing and eventually self-assembling machine learning systems, while developing this new particular area of research. And after reviewing some relevant background of robotic control methods followed by most recent advanced cognitive controllers, this Ph.D. thesis suggests that amongst many well-known ways of designing operational technologies, the design methodologies of those leading-edge high-tech devices such as cognitive chips that may well lead to intelligent machines exhibiting conscious phenomena should crucially be restricted to extremely well defined constraints. Roboticists also need those as specifications to help decide upfront on otherwise infinitely free hardware/software design details. In addition and most importantly, we propose these specifications as methodological guidelines tightly related to ethics and the nowadays well-identified workings of the human body and of its psyche.

L’émergence des circuits complexes numériques, ou System-On-Chip (SOC), pose notamment la problématique de la consommation énergétique. Parmi les blocs fonctionnels significatifs à ce titre, apparaissent les mémoires et en particulier les mémoires statiques (SRAM). La maîtrise de la consommation énergétique d’une mémoire SRAM inclue la capacité à rendre la mémoire fonctionnelle sous très faible tension d’alimentation, avec un objectif agressif de 300 mV (inférieur à la tension de seuil des transistors standard CMOS). Dans ce contexte, les travaux de thèse ont concerné la proposition d’un point mémoire SRAM suffisamment performant sous très faible tension d’alimentation et pour les nœuds technologiques avancés (CMOS bulk 28nm et FDSOI 28nm). Une analyse comparative des architectures proposées dans l’état de l’art a permis d’élaborer deux points mémoire à 10 transistors avec de très faibles impacts de courant de fuite. Outre une segmentation des ports de lecture, les propositions reposent sur l’utilisation de périphéries adaptées synchrones avec notamment une solution nouvelle de réplication, un amplificateur de lecture de données en mode tension et l’utilisation d’une polarisation dynamique arrière du caisson SOI (Body Bias). Des validations expérimentales s’appuient sur des circuits en technologies avancées. Enfin, une mémoire complète de 32kb (1024x32) a été soumise à fabrication en 28 FDSOI. Ce circuit embarque une solution de test (BIST) capable de fonctionner sous 300mV d’alimentation. Après une introduction générale, le 2ème chapitre du manuscrit décrit l’état de l’art. Le chapitre 3 présente les nouveaux points mémoire. Le 4ème chapitre décrit l’amplificateur de lecture avec la solution de réplication. Le chapitre 5 présente l’architecture d’une mémoire ultra basse tension ainsi que le circuit de test embarqué. Les travaux ont donné lieu au dépôt de 4 propositions de brevet, deux conférences internationales, un article de journal international est accepté et un autre vient d’être soumis. / Emergence of large Systems-On-Chip introduces the challenge of power management. Of the various embedded blocks, static random access memories (SRAM) constitute the angrier contributors to power consumption. Scaling down the power supply is one way to act positively on power consumption. One aggressive target is to enable the operation of SRAMs at Ultra-Low-Voltage, i.e. as low as 300 mV (lower than the threshold voltage of standard CMOS transistors). The present work concerned the proposal of SRAM bitcells able to operate at ULV and for advanced technology nodes (either CMOS bulk 28 nm or FDSOI 28 nm). The benchmarking of published architectures as state-of-the-art has led to propose two flavors of 10-transitor bitcells, solving the limitations due to leakage current and parasitic power consumption. Segmented read-ports have been used along with the required synchronous peripheral circuitry including original replica assistance, a dedicated unbalanced sense amplifier for ULV operation and dynamic forward back-biasing of SOI boxes. Experimental test chips are provided in previously mentioned technologies. A complete memory cut of 32 kbits (1024x32) has been designed with an embedded BIST block, able to operate at ULV. After a general introduction, the manuscript proposes the state-of-the-art in chapter two. The new 10T bitcells are presented in chapter 3. The sense amplifier along with the replica assistance is the core of chapter 4. The memory cut in FDSOI 28 nm is detailed in chapter 5. Results of the PhD have been disseminated with 4 patent proposals, 2 papers in international conferences, a first paper accepted in an international journal and a second but only submitted paper in an international journal.

This master’s thesis deals with the analysis, design and implementation of a system for organizing running races with the support of racers registration and the possibility of multiple online and offline checkpoints during the race. The system is composed of two web applications and a client desktop application. An administration web application is used to create and manage the race. A presentation web application with optional registration is responsible for publishing the race. It is possible to scan RFID chips of the racers on multiple track stations during the race using a client application. The RFID chips are scanned by an RFID reader connected to host device. If the client application is connected to the internet, the scanned times of racers are displayed on the presentation application in real time. Web applications are implemented with the ASP.NET MVC technology. Authorization and Authentication is provided by ASP.NET Identity. The client application is implemented using the WPF technology.

The presence of non-metallic inclusions (NMIs) have critical effects on both the mechanical properties and machinability of steels. In the present thesis, one focus is to study the characteristics of deformed sulfides (MnS) for a stainless steel (3R65) and a tool steel (42CrMo4). Three groups of MnS inclusions were detected in the samples taken after deformation of the steel: i) type RS (sulfides with a Rod-like geometry), ii) type PS (sulphides with a plate-like geometry) and iii) type OS (oxy-sulfides). Here, the elongated inclusions present in both stainless and tool steels were studied more in detail using SEM to determine the tendency for the inclusions to break.  The results showed that three types of elongated MnS inclusions could be identified, namely UU, UB and BB. Here, ‘U’ represents the unbroken edge(s) of inclusion and ‘B’ represents the broken edge(s) of an inclusion. The presence of these three types of inclusions in samples collected both before and after a heat treatment was studied and the results showed that the heat treatment had a very small effect on the morphologies of the elongated MnS inclusions for both stainless steels (containing <0.1 mass % C) and tool steels (containing 0.42 mass % C).  In the second part of the thesis, the characteristics of chips after machining of a 157REM Ce-treated steel and a 157C reference steel was studied. Furthermore, the effect of the NMIs on the chip breakability during machining was determined. The results show that a Ce modification of a 157C steel transforms the NMIs from large size elongated inclusions to small size inclusion with a spherical shape. This leads to an improved machinability of 157C steels. In addition, a newly developed weight distribution of chips (WDC) method, based on the chip weight measurements, was used to determine the tendencies for breaking of chips. The results of this investigation showed that the chips that were obtained from the machining of 157C and the 157REM steels could be classified into the following three types: i) type I chips (with a geometry containing one arc) and having a weight of less than 0.08 g, ii) type II chips (with a geometry containing two arcs) and having weights between 0.08 g and 0.15 g, and iii) type III chips (with a geometry containing three or more arcs) and having weights larger than 0.15 g. From industrial experience, it is known that a high amount of small type I chips will lead to a good chip breakability. The results from the machining test show that the fraction of type I chips from machining of the 157REM steel (65 %) is smaller than from machining of the 157C reference steel (80 %) when using a lower feed rate of 0.4 mm/rev. However, when using a higher feed rate of 0.5 mm/rev, 40 % of the chips belong to type I small chips for the 157REM steel and 14 % for the 157C steel. Based on the conditions used in this study and the obtained results, the following is clear in order to reach the best machinability: i) it is most advantageous to use the 157C steel when using a lower feed rate of 0.4 mm/rev and ii) it is most advantageous to use the 157REM steel when using a higher feed rate of 0.5 mm/rev. / Närvaron av icke-metalliska inneslutningar (NMIs) har en betydande påverkan både med avseende på mekaniska egenskaper såväl som skärbarhetsförmågan hos stål. I denna avhandling är ett fokus att studera deformerade sulfider (MnS)  i ett rostfritt stål (3R65) och ett verktygsstål (42CrMo4). Tre grupper av MnS inneslutningar återfanns i stålproverna, som togs efter deformation av stålet: i) RS (sulfider som har en cylindrisk geometri), ii) PS (sulfider som har en platt geometri) och iii) OS (oxy-sulfider). Dessutom så studerades utdragna inneslutningar mer i detalj med användande av SEM undersökningar i syfte att studera tendensen till att dessa inneslutningar bröts sönder. Resultaten visade att tre typer av utdragna inneslutningar kunde identifieras, nämligen UU, UB och BB. Här representerar ‘U’ en ände av en inneslutning som inte brutits sönder och ‘B’ representerar en ände av en inneslutning som brutits sönder. Närvaron av dessa tre typer av utdragna inneslutningar studerades i prover som togs både före och efter en värmebehandling, men resultaten visade att en värmebehandling hade en mycket liten påverkan på morfologin hos de utdragna MnS inneslutningarna för både rostfria stål (innehållande <0.1 mass % C) och verktygsstål (innehållande 0.42 mass % C).  I den andra delen av avhandlingen så studerades karakteristiken hos spånor som bildats efter skärande bearbetning av ett 157REM (Ce-behandlat) modifierat stål och ett 157C referensstål som inte modifierats. Dessutom så studerades inverkan av icke-metalliska inneslutningar på spånbrytningen under den skärande bearbetningen. Resultaten visar att en Ce-modifiering av stålet omvandlar inneslutningarna från stora och utdragna geometrier till små inneslutningar med en sfärisk geometri. Detta leder till en ökad skärbarhet hos 157C stål. Spånbrytbarheten bestämdes också med användande av en nyutvecklad metod (WDC metoden) som baseras sig på att bestämma vikten av spånor. Resultaten av denna utvärdering visade att spånorna som erhölls från bearbetning av 157C och 157REM stål kunde klassificeras enligt följande tre typer: i) typ I spånor (en geometri som består av en bågform) som har en vikt som är mindre än 0.08 g, ii) typ II spånor (en geometri som består av två bågformar) som har en mellan 0.08 g och 0.15 g och iii) typ III spånor (en geometri som består av tre eller fler bågformar) som har en vikt som är större än 0.15 g. Baserat på industriell erfarenhet så är det känt att en stor mängd av små typ I spånor är kopplad till en bra spånbrytbarhet. Resultaten från skärbarhetstesterna visar att andelen typ I spånor från bearbetning av ett 157REM stål (65 %) är mindre än vid bearbetning av ett 157C referens stål (80 %), när en lägre matningshastighet av 0.4 mm/rev används. Däremot så visar resultaten att om en högre matningshastighet av 0.5 mm/rev används vid bearbetning, så är andelen typ I spånor 40 % för 157REM stålet och 14 % för 157C referensstålet. I syfte att erhålla bästa möjliga skärbarhet så är det fördelaktigt att använda ett 157C referensstål för den lägre matningshastigheten av 0.4 mm/rev, men att använda ett 157REM stål för en högre matningshastighet av 0.5 mm/rev.

This thesis aims to create effective and comprehensive learning materials for students enrolled in the Switching Theory and Digital Design course. The lab is designed to enable students to program an FPGA using VHDL in the Quartus programming environment to control traffic intersections with sensors and traffic signals. This laboratory aims to provide students with practical experience in digital engineering design and help them develop the necessary skills to program and implement state machines for regulating traffic environments

Planetens resurser utnyttjas inte på ett ansvarsfullt sätt och för att uppnå en hållbar utveckling behöver en förändring ske i hur dessa resurser konsumeras och produceras. Ett företag som arbetar för att använda sina resurser mer effektivt och minska sin negativa miljöpåverkan är Aurobay Sweden AB.  Aurobay tillverkar drivlinor för interna hybrid- och förbränningsmotorer och använder skärande bearbetning i delar av sin produktionsprocess. Till den skärande bearbetningen används skärvätska vilket behöver filtreras för att kunna återanvändas. Företaget använder en filtreringsprocess med filterduk för att separera spånor från skärvätskan. Aurobay vill minska sin förbrukning av filterduk och skaffa en bättre förståelse för hur företagets filtreringsutrustning kan nyttjas bättre i framtiden.  Ett experiment genomfördes för att utvärdera hur en förändring av cykeltid påverkade mängden spånor som transporterades bort från filtreringsutrustningen. Resultatet visade att mätningar behöver genomföras under en längre period eftersom externa faktorer kan ha en påverkande effekt. Efter en nulägesanalys av utnyttjandegraden på några av företagets filtreringsutrustningar kunde det konstateras att den kunde vara så låg som 15 %. Genom att öka cykeltiden som filtreringsutrustningarna filtrerar kan utnyttjandegraden höjas och förbrukningen av filterduk minskas med 26 %. Utan ytterligare investeringar kan Aurobay minska kostnaderna för att köpa in ny filterduk och hantering av den förbrukade. / The planet’s resources are not being utilized responsibly, and to achieve sustainable development, changes are needed in how these resources are consumed and produced. Aurobay Sweden AB is one such company working to use its resources more efficiently and reduce its negative environmental impact.  Aurobay manufactures drivetrains for internal hybrid and combustion engines and for some of its production process machining is used. Cutting fluid is used in this machining process and it needs to be filtered before reuse. Aurobay utilizes a filtration process with filter media to separate chips from the cutting fluid. Aurobay aims to reduce its use of filter media and seeks to gain a better understanding of how the company’s filtration equipment can be optimized for future use.  An experiment was conducted to assess the impact of changing the filtration equipment’s cycle time when it comes to remove chips from a filtration process. The results indicated that measurements need to be conducted over a longer period as external factors may have an influencing effect. After an analysis of the utilization rate on some of the company’s filtration process equipment, it was found that utilization rates could be as low as 15 %. The utilization rate can be improved by increasing the cycle time which the filtration equipment operates, and the consumption of filter media can be reduced by 26 %. Without additional investments, Aurobay can reduce the costs for both purchasing new filter media and removal of the old one.

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<p>The development of low-cost, and reliable platforms for on-site detection of pathogenic agents, and toxic environmental traces is still a critical need for real-time monitoring of potential environmental pollution and imminent outbreaks. The biosensors market is projected to attain 31.5 billion by 2024. In this landscape, colorimetric and electrochemical devices continue to have significant relevance, with paper-based platforms leading the point-of-care (POC) segment for pathogen detection and environmental monitoring.</p> <p>Despite the true potential of biosensors in general, they have witnessed a slow rate in commercialization, mainly due to cost restrictions, and concerns related to their reliability and repeatability once scaled-up. This research evaluates the implementation of printing techniques as a strong approach for the fabrication of paper-based and flexible electrochemical biosensors. The results obtained demonstrated the ability to control and predict the variables affecting the sensing performance, achieving high precision of the printing parameters, and allowing optimization, and iterations since very early stages of prototype development.</p> <p>Besides the novel fabrication approach, this work introduces the use of truncated aptameric DNA sequences for whole cell detection of E. coli O157:H7 and heavy metals (Hg2+ and As3+), providing evidence of high stability and robustness under harsh conditions. Results obtained demonstrate their equal or even superior performance when compared to antibodies.</p> <p>We established the use of aptamer-functionalized multilayered label particles (PEI-grafted gold decorated polystyrene) with high stability as label particles. These particles address the well known drawback of non-selective aggregation typical of traditional naked Gold nanoparticles. The outstanding stability of these multilayered labels was demonstrated when used in an enhanced version of the lateral flow assay for detection of E. coli O157:H7 (state of the art for paper-based colorimetric detection of whole cell bacteria), and in a multiplexed paper-based microfluidic device for dual detection of Mercury and Arsenic. This work sets the foundation of the development of a next generation of health care and environmental monitoring devices that are portable, sensitive, quantitative, and can reliably detect multiple targets with one single test.</p>