Este trabalho consiste em um estudo acerca dos efeitos da radiação em circuitos programáveis e sistemas em chip, do inglês System-on-Chip (SoC), baseados em FPGAs (Field-Programmable Gate Array). Dentre os diversos efeitos que podem ensejar falhas nos circuitos integrados, destacam-se a ocorrência de Single Event Effects (SEEs), Efeitos Transitórios em tradução livre, e a Dose Total Ionizante, do inglês Total Ionizing Dose (TID). SEEs podem ocorrer em razão da incidência de nêutrons originários de interações de raios cósmicos com a atmosfera terrestre, íons pesados provenientes do espaço e prótons originários do Sol (vento solar) e dos cinturões de Van Allen. A Dose Total Ionizante diz respeito à exposição prolongada de um circuito integrado à radiação ionizante e cuja consequência é a alteração das características elétricas de partes do dispositivo em razão das cargas elétricas induzidas pela radiação e acumuladas nas interfaces dos semicondutores. Dentro desse contexto, este trabalho descreve em detalhes a caracterização do SoC-FPGA baseado em memória FLASH e de sinais mistos SmartFusion A2F200-FG484, da empresa Microsemi, quando exposto à radiação (SEEs e TID) através do uso da técnica de Redundância Diversificada visando a detecção de erros. Também, uma arquitetura que utiliza um esquema baseado em Redundância Modular Tripla e Diversificada é testada através da sua implementação no FPGA baseado em memória SRAM da família Spartan-6, modelo LX45, da empresa Xilinx, visando a detecção e correção de erros causados pela radiação (SEEs). Os resultados obtidos mostram que os diversos blocos funcionais que compõe SoC SmartFusion apresentam diferentes níveis de tolerância à radiação e que o uso das técnicas de Redundância Modular Tripla e Redundância Diversificada em conjunto mostrou-se extremamente eficiente no que se refere a tolerância a SEEs. / This work consists in a study about the radiation effects in programmable circuits and System-on-Chips (SoCs) based on FPGAs (Field-Programmable Gate Arrays). Single Event Effects (SEEs) and Total Ionizing Dose (TID) are the two main effects caused by the radiation incidence, and both can imply in the occurrence of failures in integrated circuits. SEEs are due to the incidence of neutrons derived from the interaction of the cosmic rays with the terrestrial atmosphere, as well as heavy ions coming from the space and protons provided from the solar wind and the Van Allen belts. Total Ionizing Dose regards the prolonged exposure of an integrated circuit to the ionizing radiation, which deviates the standard electrical characteristics of the device due to radiation-induced electrical charges accumulated in the semiconductors’ interfaces. In this context, this work aims to describe in details the characterization of Microsemi’s mixed-signal SoC-FPGA SmartFusion A2F200-FG484 when exposed to radiation (SEEs and TID), using a Diverse Redundancy approach for error detection. As well, an architecture using a Diversified Triple Modular Redundancy scheme was tested (SEEs) through its implementation in a Xilinx’s Spartan-6 LX45 FPGA, aiming error detection and correction. The results obtained show that several functional blocks from SmartFusion have different radiation tolerance levels and that the use of the Triple Modular Redundancy together with Diversified Redundancy proved to be extremely efficient in terms of SEEs tolerance.

Le perçage profond (Lu >= 5 x Øoutil) à l'aide de la technologie BTA (Boring Trepanning Association) intervient lorsqu'on souhaite fabriquer des pièces avec un bon rendement productif associé à une bonne qualité d'usinage. Les industries mécaniques évoluent dans un contexte de concurrence perpétuelle, avec des exigences technico-économiques toujours plus importantes. Cette étude résulte donc de la volonté de plusieurs acteurs industriels (AREVA et CIRTES) et universitaire (LEMTA, Université de Lorraine), de faire progresser la compréhension des mécanismes d'usinage qui régissent ce procédé. Une analyse bibliographique approfondie a révélé que cette technologie propose un champ d'investigation très vaste et relativement peu exploré car difficile à appréhender et à étudier. Le but de ce travail est d'analyser et de modéliser les phénomènes ayant lieu au cours d'une opération de perçage profond. Une analyse de la morphologie des copeaux a permis d'introduire un nouveau paramètre permettant d'évaluer les contraintes mécaniques subies par le matériau usiné. L'approche proposée permet quant elle de définir le torseur des contraintes mécaniques en intégrant la géométrie effective de coupe, et ce pour toutes les surfaces de coupe actives d'une tête de forage BTA. Les principes des modélisations utilisées permettent une application relativement aisée à de nombreux matériaux et à partir de l'identification d'un minimum de paramètres. Des moyens expérimentaux originaux ont permis d'identifier des paramètres ainsi que d'ajuster et d'étudier la validité des modélisations. Les limitations de la loi de comportement utilisée ont été mises en évidences, et des perspectives d'études complémentaires ont donc été proposées.Néanmoins, l'ensemble des résultats issus de cette étude ouvrent, modestement, des perspectives intéressantes, notamment dans le domaine d'aide aux choix des paramètres de coupe optimaux, et pour l'aide à la compréhension des phénomènes physiques de la coupe / Deep drilling (Drilling distance >= 5 x Øtool) with BTA system (Boring Trepanning Association) occurs when you produce parts with good productive performance combined with good machining quality. Mechanical industries operate in a context of constant competition, with ever greater technical and economic requirements. This study illustrates the desire of many industrial players (AREVA and CIRTES) and university (LEMTA, Université de Lorraine), to advance in the understanding of machining mechanisms that govern this process. A literature review revealed that this technology offers a vast and relatively unexplored field of investigation and study. The aim of this study is to analyze and modelling the phenomena which occurring in a deep drilling operation. An analysis of the morphology of the chips has introduced a new parameter for assessing the mechanical stresses suffered by the material being machined . The proposed approach allows to define the mechanical stress torsor by integrating the real cutting geometry, for all cut surfaces of active drilling head BTA. The principles of modeling used allow a relatively easy application to many materials and from the identification of a minimum parameters. Original experimental methods have allowed the identification of parameters and adjust and examine the validity of modeling. The limitations of the law of behavior have been used in evidence, and the prospects for further studies have been proposed. Nevertheless, all the results of this study open, modestly, interesting perspectives, especially in the field of helping for the choice of optimum cutting parameters, and help in the understanding of the physical phenomena of the cut

Automotive headlamps work in very variable operating conditions during which the producer have to guarantee their primary function of seeing and being seen. During the development stage of the new headlamps the manufacturers want to eliminate defects which could led to malfunction in operation. The numerical simulations along with the test procedures are appropriate tools for detection of problematic areas. The most appropriate approach is designing of experiment with a view to the subsequent simple implementation of the measured data into numerical simulations software and carefully choosing a measuring method of the monitored physical quantities. The thesis deals with phenomenon of condensation in headlamps, which has a negative effect on the light distribution and their life expectancy. Due to this experimental defog methodology was developed based on evaporation of a specified amount of water into the headlamp and then condensation on the inside surface of the headlamp lens. Pictures are taken during the measurements and the fogged and defogged areas are automatically detected. The results from experiments are used to adjust and verify a numerical model. The next part is devoted to the thermal load of the headlamp components which are mostly heated by waste heat from light sources. This phenomena depends mainly on the type of source, emissivity and thermal conductivity. A methodology of temperature measurement, thermal conductivity measurement, non-stationary method for emissivity determination and spectral characterization of thermal source based on their thermal fluxes to the surroundings has been developed.

The project aim is an optimalization of production of pressure die casting, which serves as a one part of handle in office furniture area. The main emphasis was for mass finishing operation, which serves for rounding of very sharp part edges after die casting operation. A few tests of single mass finishing parameter was carried out and as result was a few partial recommendations for an increasing of production efficiency and improving of manufacturing process, namely an adjustment of separation cycle, proposal of optimum amount of pieces in each single batch and an innovation of chips type and dimensions. The project includes a proposal of a new and more efficiency layout of pieces on the transport pallet.

The thesis deals with the design of a grate steam boiler which has natural circulation and is determined for combustion of wood chips. The boiler has a capacity of 45 t/h and produces superheated steam with the output parameters of 3,5 MPa and 450 °C at the 125 °C feed water temperature. Stoichiometric calculations and the flue gases enthalpy calculations are based on the composition of the specified fuel. The efficiency and fuel consumption of the boiler is also determined. The thesis mainly focuses on the thermal calculation and geometric design of the individual heat transfer surfaces of the boiler. The drawing documentation of the steam boiler is available in the attachment of the thesis.

Theory predicts that sexually antagonistic mutations will be over- or under-represented on the X and Z chromosomes, depending on the average dominance coefficient of the mutations. However, as little is known about the dominance coefficients for new mutations, the effect of sexually antagonistic selection is difficult to predict. To elucidate the role of sexually antagonistic selection in the evolution of Z chromosome gene content in chicken, we analyzed publicly available microarray data from several somatic tissues as well as somatic and germ cells of the ovary. We found that the Z chromosome is enriched for genes showing preferential expression in ovarian somatic cells, but not for genes with preferential expression in primary oocytes or non-sex-specific somatic tissues. Our results suggest that sexual antagonism leads to higher abundance of female-benefit alleles on the Z chromosome. No bias towards Z-linkage of oocyte-enriched genes can be explained by lower intensity of sexually antagonistic selection in ovarian germ cells compared to ovarian somatic cells. An alternative explanation would be that meiotic Z chromosome inactivation hinders accumulation of oocyte-expressed genes on the Z chromosome. Our results are consistent with findings in mammals and indicate that recessive rather than dominant...

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Synchoros VLSI design style can be an alternative choice to fit the increasing complexity of embedded multi-processor architectures. SiLago Block is part of the synchoros blocks, which can effectively reduce the cost of logic and physical synthesis as it is hardened and highly centralized details from each layer of metal. Global NoCs play an essential part in system-level design and there is necessary to benchmark the SiLago global NoC against other existing NoC libraries. In this degree project, the structure of the NoC is established based on the SiLago models, including the wires and the switches. The whole structure has nine times nine grids and sixteen switches are placed inside symmetrically. The connection between two adjacent switches is built up by wires. The routing algorithm inside the switches can support the most common routing situations by destinations, routing states, and routing history. Except the routing algorithm, this essay provides some deadlock situations and also conclude some ways to solve them. The scripts developed from the NoC generator can be used to do the logical and physical synthesis for the SiLago models. The results from the synthesis can be explored to compare against other methods about the hability to estimate cost metrics from a high level of abstraction and the quality of results. The concept of partition is introduced to accomplish physical synthesis, and through this, the design can be more approach to the core idea of synchoros VLSI design. / Synchoros VLSI designstil kan vara ett alternativt val för att passa den ökande komplexiteten hos inbäddade flerprocessorarkitekturer. SiLago Block är en del av synchoros-blocken, som effektivt kan minska kostnaderna för logik och fysisk syntes eftersom det är härdat och mycket centraliserade detaljer från varje lager av metall. Globala NoC spelar en viktig roll i design på systemnivå och det är nödvändigt att jämföra SiLago globala NoC mot andra befintliga NoC-bibliotek. I detta examensarbete fastställs strukturen för NoC baserat på SiLago-modellerna, inklusive ledningarna och switcharna. Hela strukturen har nio gånger nio rutnät och sexton brytare är placerade inuti symmetriskt. Förbindelsen mellan två intilliggande brytare byggs upp av ledningar. Routingalgoritmen inuti switcharna kan stödja de vanligaste routingsituationerna efter destinationer, routingtillstånd och routinghistorik. Förutom routingalgoritmen ger den här uppsatsen några dödlägessituationer och kommer också fram till några sätt att lösa dem. Skripten som utvecklats från NoC-generatorn kan användas för att göra den logiska och fysiska syntesen för SiLago-modellerna. Resultaten från syntesen kan utforskas för att jämföras med andra metoder om förmågan att uppskatta kostnadsmått från en hög abstraktionsnivå och kvaliteten på resultaten. Begreppet partition introduceras för att åstadkomma fysisk syntes, och genom detta kan designen vara mer förhållningssätt till kärnidén med synchoros VLSI-design.

La micro-oxygénation des vins, par la dispersion de bulles d’oxygène, est une pratique de plus en plus utilisée dans le domaine de l’œnologie. Cette technique n’est pas toujours convenablement maitrisée par manque de connaissances scientifiques sur les paramètres régissant le transfert de l’oxygène. La recherche s'est focalisée sur l'étude des coefficients de transfert en fonction des composés du vin (CO2, éthanol, sucrose, consommateurs d’oxygène) et des conditions opératoires (type de diffuseur, température, rapport entre hauteur et diamètre du contenant de liquide). Les résultats montrent que lors de la micro-oxygénation, le dioxyde de carbone dissous et le sucrose ont une incidence négative sur le transfert alors que la présence d’éthanol améliore le transfert. En ce qui concerne les conditions opératoires, l’augmentation de débit de gaz et l’augmentation de rapport entre la hauteur et le diamètre de la cuve de micro-oxygénation joue positivement sur le transfert d’oxygène La surface spécifique des bulles et le coefficient de transfert de matière ont pu être dissociés pour les vins. La nature tensio-active des composés du vin semble être un élément important sur le transfert de matière. Les connaissances acquises ont été appliquées à la micro-oxygénation au cours de deux étapes de l'élaboration des vins : la fermentation alcoolique avec la maitrise de l’apport d’oxygène et la simulation de la technique d’élevage en barrique par micro-oxygénation couplée à l’ajout de copeaux de bois. Une nouvelle approche concerne l'étude d'un contacteur membranaire qui permet le transfert d’oxygène par diffusion. / Micro-oxygenation of the wines, by the dispersion of oxygen bubbles, is a practice increasingly used in oenology. This technique is not always suitably controlled for lack of scientific knowledge on the parameters governing the transfer of oxygen. Research was focused on the study of transfer coefficients in function of wine components (CO2, ethanol, sucrose, consuming oxygen) and of operating conditions (type of diffuser, temperature, relationship between height and diameter of the container of liquid). The results show that during micro-oxygenation, the dissolved carbon dioxide and the sucrose have a negative incidence on the transfer whereas the presence of ethanol improves the transfer. As operating conditions are concerned, the increase in gas output and the increase in micro-oxygenation tank height/diameter ratio positively influence oxygen transfer. For wines, the specific surface of the bubbles and the mass transfer coefficient could be dissociated. The surfactant nature of wine components seems to be the most important factor in mass transfer. The knowledge so acquired was applied to micro-oxygenation during two stages of wine making: alcoholic fermentation with the oxygen yield control and the simulation of ageing technique in barrels coupled with the wood chips addition. A new approach relates to the study of a membrane contactor application allowing the oxygen transfer by diffusion.

Network on Chips[1][2][3][4] are critical elements of modern System on Chip(SoC) as well as Chip Multiprocessor(CMP)designs. Network on Chips (NoCs) help manage high complexity of designing large chips by decoupling computation from communication. SoCs and CMPs have a multiplicity of communicating entities like programmable processing elements, hardware acceleration engines, memory blocks as well as off-chip interfaces. With power having become a serious design constraint[5], there is a great need for designing NoC which meets the target communication requirements, while minimizing power using all the tricks available at the architecture, microarchitecture and circuit levels of the de-sign. This thesis presents a holistic, QoS based, power optimal design solution of a NoC inside a CMP taking into account link microarchitecture and processor tile configurations. Guaranteeing QoS by NoCs involves guaranteeing bandwidth and throughput for connections and deterministic latencies in communication paths. Label Switching based Network-on-Chip(LS-NoC) uses a centralized LS-NoC Management framework that engineers traffic into QoS guaranteed routes. LS-NoC uses label switching, enables band-width reservation, allows physical link sharing and leverages advantages of both packet and circuit switching techniques. A flow identification algorithm takes into account band-width available in individual links to establish QoS guaranteed routes. LS-NoC caters to the requirements of streaming applications where communication channels are fixed over the lifetime of the application. The proposed NoC framework inherently supports heterogeneous and ad-hoc SoC designs. A multicast, broadcast capable label switched router for the LS-NoC has been de-signed, verified, synthesized, placed and routed and timing analyzed. A 5 port, 256 bit data bus, 4 bit label router occupies 0.431 mm2 in 130nm and delivers peak band-width of80Gbits/s per link at312.5MHz. LS Router is estimated to consume 43.08 mW. Bandwidth and latency guarantees of LS-NoC have been demonstrated on streaming applications like Hiper LAN/2 and Object Recognition Processor, Constant Bit Rate traffic patterns and video decoder traffic representing Variable Bit Rate traffic. LS-NoC was found to have a competitive figure of merit with state-of-the-art NoCs providing QoS. We envision the use of LS-NoC in general purpose CMPs where applications demand deterministic latencies and hard bandwidth requirements. Design variables for interconnect exploration include wire width, wire spacing, repeater size and spacing, degree of pipelining, supply, threshold voltage, activity and coupling factors. An optimal link configuration in terms of number of pipeline stages for a given length of link and desired operating frequency is arrived at. Optimal configurations of all links in the NoC are identified and a power-performance optimal NoC is presented. We presents a latency, power and performance trade-off study of NoCs using link microarchitecture exploration. The design and implementation of a framework for such a design space exploration study is also presented. We present the trade-off study on NoCs by varying microarchitectural(e.g. pipelining) and circuit level(e.g. frequency and voltage) parameters. A System-C based NoC exploration framework is used to explore impacts of various architectural and microarchitectural level parameters of NoC elements on power and performance of the NoC. The framework enables the designer to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. Latency, power and throughput results using this framework to study a 4x4 CMP are presented. The framework is used to study NoC designs of a CMP using different classes of parallel computing benchmarks[6]. One of the key findings is that the average latency of a link can be reduced by increasing pipeline depth to a certain extent, as it enables link operation at higher link frequencies. Abstract There exists an optimum degree of pipelining which minimizes the energy-delay product of the link. In a 2D Torus when the longest link is pipelined by 4 stages at which point least latency(1.56 times minimum) is achieved and power(40% of max) and throughput (64%of max) are nominal. Using frequency scaling experiments, power variations of up to40%,26.6% and24% can be seen in 2D Torus, Reduced 2D Torus and Tree based NoC between various pipeline configurations to achieve same frequency at constant voltages. Also in some cases, we find that switching to a higher pipelining configuration can actually help reduce power as the links can be designed with smaller repeaters. We also find that the overall performance of the ICNs is determined by the lengths of the links needed to support the communication patterns. Thus the mesh seems to perform the best amongst the three topologies(Mesh, Torus and Folded Torus) considered in case studies. The effects of communication overheads on performance, power and energy of a multiprocessor chip using L1,L2 cache sizes as primary exploration parameters using accurate interconnect, processor, on-chip and off-chip memory modelling are presented. On-chip and off-chip communication times have significant impact on execution time and the energy efficiency of CMPs. Large cache simply larger tile area that result in longer inter-tile communication link lengths and latencies, thus adversely impacting communication time. Smaller caches potentially have higher number of misses and frequent of off-tile communication. Energy efficient tile design is a configuration exploration and trade-off study using different cache sizes and tile areas to identify a power-performance optimal configuration for the CMP. Trade-offs are explored using a detailed, cycle accurate, multicore simulation frame-work which includes superscalar processor cores, cache coherent memory hierarchies, on-chip point-to-point communication networks and detailed interconnect model including pipelining and latency. Sapphire, a detailed multiprocessor execution environment integrating SESC, Ruby and DRAM Sim was used to run applications from the Splash2 benchmark(64KpointFFT).Link latencies are estimated for a16 core CMP simulation on Sapphire. Each tile has a single processor, L1 and L2 caches and a router. Different sizesofL1 andL2lead to different tile clock speeds, tile miss rates and tile area and hence interconnect latency. Simulations across various L1, L2 sizes indicate that the tile configuration that maximizes energy efficiency is related to minimizing communication time. Experiments also indicate different optimal tile configurations for performance, energy and energy efficiency. Clustered interconnection network, communication aware cache bank mapping and thread mapping to physical cores are also explored as potential energy saving solutions. Results indicate that ignoring link latencies can lead to large errors in estimates of program completion times, of up to 17%. Performance optimal configurations are achieved at lower L1 caches and at moderateL2 cache sizes due to higher operating frequencies and smaller link lengths and comparatively lesser communication. Using minimal L1 cache size to operate at the highest frequency may not always be the performance-power optimal choice. Larger L1 sizes, despite a drop in frequency, offer a energy advantage due to lesser communication due to misses. Clustered tile placement experiments for FFT show considerable performance per watt improvement (1.2%). Remapping most accessed L2 banks by a process in the same core or neighbouring cores after communication traffic analysis offers power and performance advantages. Remapped processes and banks in clustered tile placement show a performance per watt improvement of5.25% and energy reductionof2.53%. This suggests that processors could execute a program in multiple modes, for example, minimum energy, maximum performance.