Cette thèse porte sur deux aspects complémentaires, le développement et l’implémentation de nouvelles approches de cristallisation et de cristallographie sérielle ainsi que leur mise en œuvre dans l’étude structurale de complexes enzymes : ARNt. La cristallographie est la méthode la plus employée en biologie structurale, mais elle présente encore des points délicats. Plusieurs méthodes avancées ont été déployées dans ce travail pour y pallier qui ont conduit à la résolution de la structure de l’ARNt nucléotidyltransférase du psychrophile Planococcus halocryophilus et à l’étude de son adaptation structurale au froid ; des puces microfluidiques de cristallisation qui ont servi à la résolution de plusieurs structures à température ambiante par cristallographie sérielle ; enfin le Xtal Controller utilisé pour l’étude d’évènements de nucléation et de croissance cristalline dans un but de préparation d’échantillons pour analyse sous rayonnement XFEL. Entre autres systèmes biologiques, cette thèse présente la caractérisation de deux familles d’inhibiteurs visant les aspartyl-ARNt synthétases, notamment du pathogène Pseudomonas aeruginosa. / This thesis focuses on two complementary aspects, the development and implementation of new approaches of crystallization and of serial crystallography as well as their use in the structural study of enzymes/tRNA complexes. Crystallography is the most used method in structural biology, but it presents delicate points. Different methods were implemented in this work to overcome these points, which led to the resolution of the structure of the CCA-adding enzyme of the psychrophilic organism Planococcus halocryophilus and to the study of its structural adaptation to the cold; novel microfluidic crystallization chips that have been used for the resolution of several structures by serial crystallography at room-temperature; finally the Xtal Controller used for the study of nucleation and crystal growth events with the purpose of preparing samples for analysis under XFEL radiation. Among other biological systems, this thesis presents the study and characterization of two families of inhibitors targeting aspartyl-tRNA synthetases, including the one of the pathogenic organism Pseudomonas aeruginosa.

The main objective of this thesis was to improve the understanding of some aspects on wood and fibre mechanics related to conditions in the thermomechanical pulping process. Another objective was to measure the power distribution between the rotating plates in a refiner.   The thesis comprises the following parts: –A literature review aimed at describing fracture in wood and fibres as related to the thermomechanical pulping process –An experimental study of fracture in wood under compression, at conditions similar to those in feeding of chips into preheaters and chip refiners –An experimental study of the effect of impact velocity on the fracture of wood, related to conditions of fibre separation in the breaker bar zone in a chip refiner –A micromechanical model of the deterioration of wood fibres, related to the development of fibre properties during the intense treatment in the small gap in the refining zone –Measurements of the power distribution in a refiner.   The fracture in wood under compression was investigated by use of acoustic emission monitoring. The wood was compressed in both lateral and longitudinal directions to predict preferred modes of deformation in order to achieve desired irreversible changes in the wood structure. It was concluded that the most efficient compression direction in this respect is longitudinal. Preferable temperature at which the compression should be carried out and specific energy input needed in order to achieve substantial changes in the wood structure were also given.   The fibre separation step and specifically the effect of impact velocity on the fracture energy were studied by use of a falling weight impact tester. The fracture surfaces were also examined under a microscope. An increase in impact velocity resulted in an increase in fracture energy. In the thermomechanical pulping process the fibres are subjected to lateral compression, tension and shear which causes the creation of microcracks in the fibre wall. This damage reduces the fibre wall stiffness. A simplified analytical model is presented for the prediction of the stiffness degradation due to the damage state in a wood fibre, loaded in uni-axial tension or shear. The model was based on an assumed displacement field together with the minimum total potential energy theorem. For the damage development an energy criterion was employed. The model was applied to calculate the relevant stiffness coefficients as a function of the damage state. The energy consumption in order to achieve a certain damage state in a softwood fibre by uniaxial tension or shear load was also calculated. The energy consumption was found to be dependent on the microfibril angle in the middle secondary wall, the loading case, the thicknesses of the fibre cell wall layers, and conditions such as moisture content and temperature. At conditions, prevailing at the entrance of the gap between the plates in a refiner and at relative high damage states, more energy was needed to create cracks at higher microfibril angles. The energy consumption was lower for earlywood compared to latewood fibres. For low microfibril angles, the energy consumption was lower for loading in shear compared to tension for both earlywood and latewood fibres. Material parameters, such as initial damage state and specific fracture energy, were determined by fitting of input parameters to experimental data. Only a part of the electrical energy demand in the thermomechanical pulping process is considered to be effective in fibre separation and developing fibre properties. Therefore it is important to improve the understanding of how this energy is distributed along the refining zone. Investigations have been carried out in a laboratory single-disc refiner. It was found that a new developed force sensor is an effective way of measuring the power distribution within the refining zone. The collected data show that the tangential force per area and consequently also the power per unit area increased with radial position. The results in this thesis improve the understanding of the influence of some process parameters in thermomechanical pulping related wood and fibre mechanics such as loading rate, loading direction, moisture content and temperature to separate the fibres from the wood and to achieve desired irreversible changes in the fibre structure. Further, the thesis gives an insight of the spatial energy distribution in a refiner during thermomechanical pulping.

Ultra-cold dilute gases of neutral atoms are attractive candidates for creating controlled mesoscopic quantum systems. In particular, quantum degenerate gases of bosonic and fermionic atoms can be used to model the correlated many-body behaviour of Bose and Fermi condensed matter systems, and to study matter wave interference and coherence. This thesis describes the experimental realization and manipulation of Bose-Einstein condensates (BECs) of 87Rb and degenerate Fermi gases (DFGs) of 40K using static and dynamic magnetic atom chip traps. Atom chips are versatile modern tools used to manipulate atomic gases. The chips consist of micrometre-scale conductors supported by a planar insulating substrate, and can be used to create confining potentials for neutral atoms tens or hundreds of micrometres from the chip surface. We demonstrate for the first time that a DFG can be produced via sympathetic cooling with a BEC using a simple single-vacuum-chamber apparatus. The large 40K-87Rb collision rate afforded by the strongly confining atom chip potential permits rapid cooling of 40K to quantum degeneracy via sympathetic cooling with 87Rb. By studying 40K-87Rb cross-thermalization as a function of temperature, we observe the Ramsauer-Townsend reduction in the 40K-87Rb elastic scattering cross-section. We achieve DFG temperatures as low as T = 0.1TF , and observe Fermi pressure in the time-of-flight expansion of the gas. This thesis also describes the radio-frequency (RF) manipulation of trapped atoms to create dressed state double-well potentials for BEC and DFG.We demonstrate for the first time that RF-dressed potentials are species-selective, permitting the formation of simultaneous 87Rb double-well and 40K single-well potentials using a 40K-87Rb mixture. We also develop tools to measure fluctuations of the relative atom number and relative phase of a dynamically split 87Rb BEC. In particular, we observe atom number fluctuations at the shot-noise level using time-of-flight absorption imaging. These measurement tools lay the foundation for future investigations of number squeezing and matter wave coherence in BEC and DFG systems.

Ultra-cold dilute gases of neutral atoms are attractive candidates for creating controlled mesoscopic quantum systems. In particular, quantum degenerate gases of bosonic and fermionic atoms can be used to model the correlated many-body behaviour of Bose and Fermi condensed matter systems, and to study matter wave interference and coherence. This thesis describes the experimental realization and manipulation of Bose-Einstein condensates (BECs) of 87Rb and degenerate Fermi gases (DFGs) of 40K using static and dynamic magnetic atom chip traps. Atom chips are versatile modern tools used to manipulate atomic gases. The chips consist of micrometre-scale conductors supported by a planar insulating substrate, and can be used to create confining potentials for neutral atoms tens or hundreds of micrometres from the chip surface. We demonstrate for the first time that a DFG can be produced via sympathetic cooling with a BEC using a simple single-vacuum-chamber apparatus. The large 40K-87Rb collision rate afforded by the strongly confining atom chip potential permits rapid cooling of 40K to quantum degeneracy via sympathetic cooling with 87Rb. By studying 40K-87Rb cross-thermalization as a function of temperature, we observe the Ramsauer-Townsend reduction in the 40K-87Rb elastic scattering cross-section. We achieve DFG temperatures as low as T = 0.1TF , and observe Fermi pressure in the time-of-flight expansion of the gas. This thesis also describes the radio-frequency (RF) manipulation of trapped atoms to create dressed state double-well potentials for BEC and DFG.We demonstrate for the first time that RF-dressed potentials are species-selective, permitting the formation of simultaneous 87Rb double-well and 40K single-well potentials using a 40K-87Rb mixture. We also develop tools to measure fluctuations of the relative atom number and relative phase of a dynamically split 87Rb BEC. In particular, we observe atom number fluctuations at the shot-noise level using time-of-flight absorption imaging. These measurement tools lay the foundation for future investigations of number squeezing and matter wave coherence in BEC and DFG systems.

Este trabalho consiste em um estudo acerca dos efeitos da radiação em circuitos programáveis e sistemas em chip, do inglês System-on-Chip (SoC), baseados em FPGAs (Field-Programmable Gate Array). Dentre os diversos efeitos que podem ensejar falhas nos circuitos integrados, destacam-se a ocorrência de Single Event Effects (SEEs), Efeitos Transitórios em tradução livre, e a Dose Total Ionizante, do inglês Total Ionizing Dose (TID). SEEs podem ocorrer em razão da incidência de nêutrons originários de interações de raios cósmicos com a atmosfera terrestre, íons pesados provenientes do espaço e prótons originários do Sol (vento solar) e dos cinturões de Van Allen. A Dose Total Ionizante diz respeito à exposição prolongada de um circuito integrado à radiação ionizante e cuja consequência é a alteração das características elétricas de partes do dispositivo em razão das cargas elétricas induzidas pela radiação e acumuladas nas interfaces dos semicondutores. Dentro desse contexto, este trabalho descreve em detalhes a caracterização do SoC-FPGA baseado em memória FLASH e de sinais mistos SmartFusion A2F200-FG484, da empresa Microsemi, quando exposto à radiação (SEEs e TID) através do uso da técnica de Redundância Diversificada visando a detecção de erros. Também, uma arquitetura que utiliza um esquema baseado em Redundância Modular Tripla e Diversificada é testada através da sua implementação no FPGA baseado em memória SRAM da família Spartan-6, modelo LX45, da empresa Xilinx, visando a detecção e correção de erros causados pela radiação (SEEs). Os resultados obtidos mostram que os diversos blocos funcionais que compõe SoC SmartFusion apresentam diferentes níveis de tolerância à radiação e que o uso das técnicas de Redundância Modular Tripla e Redundância Diversificada em conjunto mostrou-se extremamente eficiente no que se refere a tolerância a SEEs. / This work consists in a study about the radiation effects in programmable circuits and System-on-Chips (SoCs) based on FPGAs (Field-Programmable Gate Arrays). Single Event Effects (SEEs) and Total Ionizing Dose (TID) are the two main effects caused by the radiation incidence, and both can imply in the occurrence of failures in integrated circuits. SEEs are due to the incidence of neutrons derived from the interaction of the cosmic rays with the terrestrial atmosphere, as well as heavy ions coming from the space and protons provided from the solar wind and the Van Allen belts. Total Ionizing Dose regards the prolonged exposure of an integrated circuit to the ionizing radiation, which deviates the standard electrical characteristics of the device due to radiation-induced electrical charges accumulated in the semiconductors’ interfaces. In this context, this work aims to describe in details the characterization of Microsemi’s mixed-signal SoC-FPGA SmartFusion A2F200-FG484 when exposed to radiation (SEEs and TID), using a Diverse Redundancy approach for error detection. As well, an architecture using a Diversified Triple Modular Redundancy scheme was tested (SEEs) through its implementation in a Xilinx’s Spartan-6 LX45 FPGA, aiming error detection and correction. The results obtained show that several functional blocks from SmartFusion have different radiation tolerance levels and that the use of the Triple Modular Redundancy together with Diversified Redundancy proved to be extremely efficient in terms of SEEs tolerance.

L’augmentation de la taille des réseaux actuels ainsi que de la diversité des applications qui les utilisent font que les architectures de calcul traditionnelles deviennent limitées. En effet, les architectures purement logicielles ne permettent pas de tenir les débits en jeu, tandis que celles purement matérielles n’offrent pas assez de flexibilité pour répondre à la diversité des applications. Ainsi, l’utilisation de solutions de type matériel programmable, en particulier les Field Programmable Gate Arrays (FPGAs), a été envisagée. En effet, ces architectures sont souvent considérées comme un bon compromis entre performances et flexibilité, notamment grâce à la technique de Reconfiguration Dynamique Partielle (RDP), qui permet de modifier le comportement d’une partie du circuit pendant l’exécution. Cependant, cette technique peut présenter des inconvénients lorsqu’elle est utilisée de manière intensive, en particulier au niveau du stockage des fichiers de configuration, appelés bitstreams. Pour palier ce problème, il est possible d’utiliser la relocation de bitstreams, permettant de réduire le nombre de fichiers de configuration. Cependant cette technique est fastidieuse et exige des connaissances pointues dans les FPGAs. Un flot de conception entièrement automatisé a donc été développé dans le but de simplifier son utilisation.Pour permettre une flexibilité sur l’enchaînement des traitements effectués, une architecture de communication flexible supportant des hauts débits est également nécessaire. Ainsi, l’étude de Network-on-Chips dédiés aux circuits reconfigurables et au traitements réseaux à haut débit.Enfin, un cas d’étude a été mené pour valider notre approche. / The increase in both size and diversity of applications regarding modern networks is making traditional computing architectures limited. Indeed, purely software architectures can not sustain typical throughputs, while purely hardware ones severely lack the flexibility needed to adapt to the diversity of applications. Thus, the investigation of programmable hardware, such as Field Programmable Gate Arrays (FPGAs), has been done. These architectures are indeed usually considered as a good tradeoff between performance and flexibility, mainly thanks to the Dynamic Partial Reconfiguration (DPR), which allows to reconfigure a part of the design during run-time.However, this technique can have several drawbacks, especially regarding the storing of the configuration files, called bitstreams. To solve this issue, bitstream relocation can be deployed, which allows to decrease the number of configuration files required. However, this technique is long, error-prone, and requires specific knowledge inFPGAs. A fully automated design flow has been developped to ease the use of this technique. In order to provide flexibility regarding the sequence of treatments to be done on our architecture, a flexible and high-throughput communication structure is required. Thus, a Network-on-Chips study and characterization has been done accordingly to network processing and bitstream relocation properties. Finally, a case study has been developed in order to validate our approach.

La conception de systèmes embarqués modernes est de plus en plus complexe, car plus de fonctionnalités sont intégrées dans ces systèmes. En même temps, afin de répondre aux exigences de calcul tout en conservant une consommation d'énergie de faible niveau, MPSoCs sont apparus comme les principales solutions pour tels systèmes embarqués. En outre, les systèmes embarqués sont de plus en plus adaptatifs, comme l’adaptabilité peut apporter un certain nombre d'avantages, tels que la flexibilité du logiciel et l'efficacité énergétique. Cette thèse vise la conception sécuritaire de ces MPSoCs adaptatifs. Tout d'abord, chaque configuration de système doit être analysée en ce qui concerne ses propriétés fonctionnelles et non fonctionnelles. Nous présentons un cadre abstraite de conception et d’analyse qui permet des décisions d’implémentation plus rapide et plus rentable. Ce cadre est conçu comme un support de raisonnement intermédiaire pour les environnements de co-conception de logiciel / matériel au niveau de système. Il peut élaguer l'espace de conception à sa plus grande portée, et identifier les candidats de solutions de conception de manière rapide et efficace. Dans ce cadre, nous utilisons un codage basé sur l’horloge abstrait pour modéliser les comportements du système. Différents scénarios d'applications de mapping et de planification sur MPSoCs sont analysés via les traces d'horloge qui représentent les simulations du système. Les propriétés d'intérêt sont l’exactitude du comportement fonctionnel, la performance temporelle et la consommation d'énergie. Deuxièmement, la gestion de la reconfiguration de MPSoCs adaptatifs doit être abordée. Nous sommes particulièrement intéressés par les MPSoCs implémentés sur des architectures reconfigurables de hardware (ex. FPGA tissus) qui offrent une bonne flexibilité et une efficacité de calcul pour les MPSoCs adaptatifs. Nous proposons un cadre général de conception basésur la technique de la synthèse de contrôleurs discrets (SCD) pour résoudre ce problème. L’avantage principal de cette technique est qu'elle permet une synthèse d'un contrôleur automatique vis-à-vis d’une spécification donnée des objectifs de contrôle. Dans ce cadre, le comportement de reconfiguration du système est modélisé en termes d'automates synchrones en parallèle. Le problème de calcul de la gestion reconfiguration vis-à-vis de multiples objectifs concernant, par exemple, les usages des ressources, la performance et la consommation d’énergie est codé comme un problème de SCD . Le langage de programmation BZR existant et l’outil Sigali sont employés pour effectuer SCD et générer un contrôleur qui satisfait aux exigences du système. Finalement, nous étudions deux façons différentes de combiner les deux cadres de conception proposées pour MPSoCs adaptatifs. Tout d'abord, ils sont combinés pour construire un flot de conception complet pour MPSoCs adaptatifs. Deuxièmement, ils sont combinés pour présenter la façon dont le gestionnaire d'exécution conçu dans le second cadre peut être intégré dans le premier cadre de sorte que les simulations de haut niveau peuvent être effectuées pour évaluer le gestionnaire d'exécution. / The design of modern embedded systems is getting more and more complex, as more func- tionality is integrated into these systems. At the same time, in order to meet the compu- tational requirements while keeping a low level power consumption, MPSoCs have emerged as the main solutions for such embedded systems. Furthermore, embedded systems are be- coming more and more adaptive, as the adaptivity can bring a number of benefits, such as software flexibility and energy efficiency. This thesis targets the safe design of such adaptive MPSoCs. First, each system configuration must be analyzed concerning its functional and non- functional properties. We present an abstract design and analysis framework, which allows for faster and cost-effective implementation decisions. This framework is intended as an intermediate reasoning support for system level software/hardware co-design environments. It can prune the design space at its largest, and identify candidate design solutions in a fast and efficient way. In the framework, we use an abstract clock-based encoding to model system behaviors. Different mapping and scheduling scenarios of applications on MPSoCs are analyzed via clock traces representing system simulations. Among properties of interest are functional behavioral correctness, temporal performance and energy consumption. Second, the reconfiguration management of adaptive MPSoCs must be addressed. We are specially interested in MPSoCs implemented on reconfigurable hardware architectures (i.e., FPGA fabrics), which provide a good flexibility and computational efficiency for adap- tive MPSoCs. We propose a general design framework based on the discrete controller syn- thesis (DCS) technique to address this issue. The main advantage of this technique is that it allows the automatic controller synthesis w.r.t. a given specification of control objectives. In the framework, the system reconfiguration behavior is modeled in terms of synchronous parallel automata. The reconfiguration management computation problem w.r.t. multiple objectives regarding e.g., resource usages, performance and power consumption is encoded as a DCS problem. The existing BZR programming language and Sigali tool are employed to perform DCS and generate a controller that satisfies the system requirements. Finally, we investigate two different ways of combining the two proposed design frame- works for adaptive MPSoCs. Firstly, they are combined to construct a complete design flow for adaptive MPSoCs. Secondly, they are combined to present how the designed run-time manager by the second framework can be integrated into the first framework so that high level simulations can be performed to assess the run-time manager.

Made available in DSpace on 2015-03-26T14:01:05Z (GMT). No. of bitstreams: 1 texto completo.pdf: 3204429 bytes, checksum: bb0afea4fc4ece0c42828bf3aa84a915 (MD5) Previous issue date: 2010-07-08 / This work shows the results using of advanced control algorithm and soft-sensor to increase the efficiency of the stage of pre-vaporization in the cooking plant process of extracting pulp, by optimizing the level of the Diamondback® chip bin. The extraction system chips presents several obstacles to effective control, such as: (1) points without stack of chips during the transition movement of the extraction system bin in the storage chips and consequently sudden decrease in the volume of chip bin, (2) compaction and uneven stack height causing high variability in the volume of chip bin, (3) without information in real time position of the threads in the operating display (4) high travel time between the extraction system and measurement points (volume of the silo and the balance volume). To eliminating the section without chips were available eight virtual switches limits, positioned by operator, on the operation screen, limiting the transition movement of the extraction system chips. The new control strategy the measurement is performed by a soft-sensor that predicts the volume of chips, using multiple linear regression. Using soft-sensor to measurement volume, so the retention time of the system was eliminate and decrease the variability of volume of chips bin. Using this new control strategy allied with soft-sensor proved to be adequate to solve the problem, the system became able to request of the Andritz company (70% + / - 10% of measurement section), The new control algorithm efficiency depends of the adjustments, tuning and learning with the system in operation.´ / Este trabalho mostra os resultados da utilização de algoritmo avançado de controle e sensores virtuais para aumentar a eficiência da etapa de pré-vaporização do digestor contínuo no processo de extração de polpa celulósica, através da otimização do nível do silo de cavacos. O sistema de extração de cavacos apresenta vários obstáculos para um controle eficaz, tais como: (1) pontos sem pilha de cavacos durante o movimento de translação das roscas provocando queda repentina do volume de cavacos e consequentemente queda repentina do nível de cavacos; (2) compactação e altura da pilha desuniforme provocando alta variabilidade do nível de cavacos; (3) inexistência de informação em tempo real da posição das roscas na tela de operação (4) elevado atraso de medição de vazão e nível de cavacos devido a distância das roscas ao pontos de medições (nível do silo e a balança volumétrica). Para eliminar os pontos sem pilhas de cavacos foram elaboradas oito chaves de fim de curso virtuais, cujo posicionamento é realizado pelo operador na tela de operação para limitar o curso de translação das roscas. Na nova estratégia de controle a medição é realizada por um sensor virtual que prediz já na saída das roscas o volume deslocado, empregando regressão linear múltipla. Com a utilização dos sensores virtuais de volume deslocado, eliminou-se o tempo de retenção do sistema, tornando mais uniforme o volume de cavacos para o silo. A utilização desta nova estratégia de controle aliadas aos sensores virtuais mostrou-se adequada para a resolução do problema, tornou-se o sistema capaz de atender a solicitação do fabricante Andritz (70% do volume de medição +/- 10%). A eficiência do novo algoritmo de controle depende de ajustes, sintonia e de aprendizado com o sistema em operação.

CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / CNPq - Conselho Nacional de Desenvolvimento Científico e Tecnológico / FAPEMIG - Fundação de Amparo a Pesquisa do Estado de Minas Gerais / O aumento crescente da procura por produtos que necessitam de componentes cada vez menores impulsiona o desenvolvimento da microusinagem, considerada altamente necessária para os avanços tecnológicos na área metal mecânica. Neste contexto, o microfresamento é uma alternativa viável para a fabricação destes microcomponentes, permitindo a usinagem de geometrias complexas em diversos materiais tais como: metais e ligas, compósitos, polímeros, cerâmicas e alguns aços inoxidáveis, sendo que estes últimos despertam grande interesse para a indústria devido à sua característica de grande resistência à corrosão e à oxidação. No entanto, adaptar o conhecimento do fresamento de aços inoxidáveis em escala convencional para a microescala exige o entendimento dos fenômenos específicos que surgem com a redução das dimensões envolvidas nas operações. Diante desse contexto, este trabalho tem como principal objetivo a investigação da usinabilidade do aço inoxidável duplex UNS S32205 no microfresamento. Para tanto, foram realizados ensaios para fabricação de microcanais, utilizando uma microfresadora CNC de quatro eixos, rotação máxima de 60 000 rpm e resolução de 0,1 μm, usando microfresas de metal duro com diâmetro de 200 µm e 400 µm. A partir dos dados experimentais, foram analisados a evolução do desgaste, as formas e mecanismos de desgaste da ferramenta, a formação de rebarba, a superfície microusinada, a rugosidade superficial e a formação de cavaco. Os resultados mostram que a ferramenta com diâmetro de 200 µm apresentou um excelente desempenho em relação ao comprimento usinado, no entanto o aumento da velocidade de corte levou a um desgaste excessivo e altas rebarbas. Na usinagem utilizando ferramentas de diâmetro 400 µm, o desgaste e altura das rebarbas foi atenuado através da utilização do fluído de corte. E por fim, as ferramentas com maior diâmetro apresentaram rebarbas muito menores quando comparadas às de menor diâmetro, formando cavacos contínuos, além de apresentarem um menor grau de recalque. / The increasing demand for products requiring increasingly smaller components drives the development of micromachining, which is considered to be highly necessary for technological advances in the field of mechanical engineering. In this context, micromilling is a viable alternative for the manufacture of these microcomponents, allowing the machining of complex geometries in various materials such as: metals and alloys, composites, polymers, ceramics and some stainless steels, the latter of which arouse great interest for the industry due to its characteristic of great resistance to corrosion and oxidation. However, adapting the knowledge of milling of stainless steels on a conventional scale to the microscale requires an understanding of the specific phenomena that arise with the reduction of operations. Considering this context, this work has as main objective the investigation of the machinability of duplex stainless steel UNS S32205 in the micromilling operation. For that, tests were made to manufacture microchannels, using a 4-axis CNC micromill machine tool, with maximum spindle rotation of 60 000 rpm and resolution of 0.1 μm, using 200 µm and 400 µm diameter tools. From the experimental data, it was investigated the evolution of tool wear, the forms and mechanisms of tool wear, burr formation, machined surface quality, surface roughness and chip formation. The results show that the tool with diameter 200 µm presented an excellent performance in relation to the machined length, however the increased cutting speed led to excessive wear and high burrs. In the machining tests using tools with diameter 400 µm, the wear and height of the burrs was attenuated through the use of cutting fluid. Finally, the tools with the largest diameter presented minor burrs when compared to the smaller diameter, forming continuous chips, in addition to presenting a lower chip thickness ratio of the chips. / Dissertação (Mestrado)

Este trabalho consiste em um estudo acerca dos efeitos da radiação em circuitos programáveis e sistemas em chip, do inglês System-on-Chip (SoC), baseados em FPGAs (Field-Programmable Gate Array). Dentre os diversos efeitos que podem ensejar falhas nos circuitos integrados, destacam-se a ocorrência de Single Event Effects (SEEs), Efeitos Transitórios em tradução livre, e a Dose Total Ionizante, do inglês Total Ionizing Dose (TID). SEEs podem ocorrer em razão da incidência de nêutrons originários de interações de raios cósmicos com a atmosfera terrestre, íons pesados provenientes do espaço e prótons originários do Sol (vento solar) e dos cinturões de Van Allen. A Dose Total Ionizante diz respeito à exposição prolongada de um circuito integrado à radiação ionizante e cuja consequência é a alteração das características elétricas de partes do dispositivo em razão das cargas elétricas induzidas pela radiação e acumuladas nas interfaces dos semicondutores. Dentro desse contexto, este trabalho descreve em detalhes a caracterização do SoC-FPGA baseado em memória FLASH e de sinais mistos SmartFusion A2F200-FG484, da empresa Microsemi, quando exposto à radiação (SEEs e TID) através do uso da técnica de Redundância Diversificada visando a detecção de erros. Também, uma arquitetura que utiliza um esquema baseado em Redundância Modular Tripla e Diversificada é testada através da sua implementação no FPGA baseado em memória SRAM da família Spartan-6, modelo LX45, da empresa Xilinx, visando a detecção e correção de erros causados pela radiação (SEEs). Os resultados obtidos mostram que os diversos blocos funcionais que compõe SoC SmartFusion apresentam diferentes níveis de tolerância à radiação e que o uso das técnicas de Redundância Modular Tripla e Redundância Diversificada em conjunto mostrou-se extremamente eficiente no que se refere a tolerância a SEEs. / This work consists in a study about the radiation effects in programmable circuits and System-on-Chips (SoCs) based on FPGAs (Field-Programmable Gate Arrays). Single Event Effects (SEEs) and Total Ionizing Dose (TID) are the two main effects caused by the radiation incidence, and both can imply in the occurrence of failures in integrated circuits. SEEs are due to the incidence of neutrons derived from the interaction of the cosmic rays with the terrestrial atmosphere, as well as heavy ions coming from the space and protons provided from the solar wind and the Van Allen belts. Total Ionizing Dose regards the prolonged exposure of an integrated circuit to the ionizing radiation, which deviates the standard electrical characteristics of the device due to radiation-induced electrical charges accumulated in the semiconductors’ interfaces. In this context, this work aims to describe in details the characterization of Microsemi’s mixed-signal SoC-FPGA SmartFusion A2F200-FG484 when exposed to radiation (SEEs and TID), using a Diverse Redundancy approach for error detection. As well, an architecture using a Diversified Triple Modular Redundancy scheme was tested (SEEs) through its implementation in a Xilinx’s Spartan-6 LX45 FPGA, aiming error detection and correction. The results obtained show that several functional blocks from SmartFusion have different radiation tolerance levels and that the use of the Triple Modular Redundancy together with Diversified Redundancy proved to be extremely efficient in terms of SEEs tolerance.