Αντικείμενο της παρούσας Ειδικής Επιστημονικής Εργασίας είναι η ανάπτυξη φίλτρων στο πεδίο της τετραγωνικής ρίζας με τη μέθοδο του γραμμικού μετασχηματισμού (Linear Transformation). Ως παράδειγμα, δίνεται η σχεδίαση, η εξομοίωση και τέλος η φυσική σχεδίαση ενός ελλειπτικού βαθυπερατού φίλτρου 3ης τάξης στο πεδίο της τετραγωνικής ρίζας (Square-Root Domain). Για λόγους σύγκρισης, η σχεδίαση του φίλτρου γίνεται με τέσσερις διαφορετικές μεθόδους εξομοίωσης παθητικών φίλτρων (Leapfrog, Topologic, Wave και Linear Trasformation method) και η ανάλυση κάθε μεθόδου παρουσιάζεται σε αντίστοιχο κεφάλαιο. / The subject of this master thesis is the design of analog filters in square root domain utilizing the method of Linear Transformation. As a design example a third order elliptic lowpass filter transfer function will be realized. For comparison results we are using four different design methods (Leapfrog, Topologic, Wave and Linear Trasformation)in order to realize such filter. Each synthesis method is demonstrated in different chapter.

Thesis (M. App. Sc.)--Carleton University, 2005. / Includes bibliographical references (p. 79-82). Also available in electronic format on the Internet.

Um novo circuito amplificador de 50 MHz - 1 GHz com alta linearidade para o padrão IEEE 802.22 “wireless regional area” (WRAN) é apresentado. Ele foi implementado sem nenhum indutor e oferece uma saída diferencial para ser utilizada como balun. Técnicas de cancelamento de ruído e aumento de linearidade foram usadas para melhorar a performace do amplificador de modo que eles pudessem ser otimizados separadamente. A linearidade foi melhorada utilizando transistores conectados como diodo. O amplificador foi implementado em um processo CMOS 130 nm, em uma área compacta de 136 m x 71 m. As simulações são apresentadas para esquemáticos pós-leiaute para duas classes diferentes de projeto: um visando a melhor linearidade e o outro a melhor Figura de Ruído (FR). Quando otimizado para melhor linearidade, os resultados de simulação atingem um ganho de tensão > 23.7 dB (ganho de potência > 19.1 dB), uma figura de ruído < 3.6 dB na banda inteira (com 2.4 dB min), um ponto de intersecção de terceira ordem (IIP3) > 3.3 dBm (7.6 dBm max) e um coeficiente de reflexão de entrada S11 < -16 dB. Quando otimizado para melhor figura de ruído, ele atinge um ganho de tensão > 24.7 dB (ganho de potência > 19.8 dB), uma FR < 2 dB na banda inteira, um IIP3 > -0.3 dBm e um S11 < -11 dB. Resultados de simulação Monte Carlo confirmam baixa sensibilidade à variabilidade de processo. Além disso, uma baixa sensibilidade com a temperatura na faixa de -55 até 125 C foi observada para Ganho, FR e S11. Consumo de potência é 17.6 mA sob fonte de alimentação de 1.2 V. / A new 50 MHz - 1 GHz low-noise amplifier circuit with high linearity for IEEE 802.22 wireless regional area network (WRAN) is presented. It was implemented without any inductor and offers a differential output for balun use. Noise cancelling and linearity boosting techniques were used to improve the amplifier performance in a way they can be separately optimized. Linearity was improved using diode-connected transistors. The amplifier was implemented in a 130 nm CMOS process in a compact 136 m x 71 m area. Simulations are presented for post-layout schematics for two classes of design: one for best linearity, another for best noise figure (NF). When optimized for best linearity, simulation results achieve a voltage gain > 23.7 dB (power gain > 19.1 dB), a NF < 3.6 dB over the entire band (with 2.4 dB min figure), an input third-order intercept point (IIP3) > 3.3 dBm (7.6 dBm max.) and an input power reflection coefficient S11 < -16 dB. When optimized for best NF, it achieves a voltage gain > 24.7 dB (power gain > 19.8 dB), a NF < 2 dB over the entire band, an IIP3 > -0.3 dBm and an S11 < -11 dB. Monte Carlo simulation results confirm low sensitivity to process variations. Also a low sensitivity to temperature within the range -55 to 125 C was observed for Gain, NF and S11. Power consumption is 17.6 mA under a 1.2 V supply.

Um novo circuito amplificador de 50 MHz - 1 GHz com alta linearidade para o padrão IEEE 802.22 “wireless regional area” (WRAN) é apresentado. Ele foi implementado sem nenhum indutor e oferece uma saída diferencial para ser utilizada como balun. Técnicas de cancelamento de ruído e aumento de linearidade foram usadas para melhorar a performace do amplificador de modo que eles pudessem ser otimizados separadamente. A linearidade foi melhorada utilizando transistores conectados como diodo. O amplificador foi implementado em um processo CMOS 130 nm, em uma área compacta de 136 m x 71 m. As simulações são apresentadas para esquemáticos pós-leiaute para duas classes diferentes de projeto: um visando a melhor linearidade e o outro a melhor Figura de Ruído (FR). Quando otimizado para melhor linearidade, os resultados de simulação atingem um ganho de tensão > 23.7 dB (ganho de potência > 19.1 dB), uma figura de ruído < 3.6 dB na banda inteira (com 2.4 dB min), um ponto de intersecção de terceira ordem (IIP3) > 3.3 dBm (7.6 dBm max) e um coeficiente de reflexão de entrada S11 < -16 dB. Quando otimizado para melhor figura de ruído, ele atinge um ganho de tensão > 24.7 dB (ganho de potência > 19.8 dB), uma FR < 2 dB na banda inteira, um IIP3 > -0.3 dBm e um S11 < -11 dB. Resultados de simulação Monte Carlo confirmam baixa sensibilidade à variabilidade de processo. Além disso, uma baixa sensibilidade com a temperatura na faixa de -55 até 125 C foi observada para Ganho, FR e S11. Consumo de potência é 17.6 mA sob fonte de alimentação de 1.2 V. / A new 50 MHz - 1 GHz low-noise amplifier circuit with high linearity for IEEE 802.22 wireless regional area network (WRAN) is presented. It was implemented without any inductor and offers a differential output for balun use. Noise cancelling and linearity boosting techniques were used to improve the amplifier performance in a way they can be separately optimized. Linearity was improved using diode-connected transistors. The amplifier was implemented in a 130 nm CMOS process in a compact 136 m x 71 m area. Simulations are presented for post-layout schematics for two classes of design: one for best linearity, another for best noise figure (NF). When optimized for best linearity, simulation results achieve a voltage gain > 23.7 dB (power gain > 19.1 dB), a NF < 3.6 dB over the entire band (with 2.4 dB min figure), an input third-order intercept point (IIP3) > 3.3 dBm (7.6 dBm max.) and an input power reflection coefficient S11 < -16 dB. When optimized for best NF, it achieves a voltage gain > 24.7 dB (power gain > 19.8 dB), a NF < 2 dB over the entire band, an IIP3 > -0.3 dBm and an S11 < -11 dB. Monte Carlo simulation results confirm low sensitivity to process variations. Also a low sensitivity to temperature within the range -55 to 125 C was observed for Gain, NF and S11. Power consumption is 17.6 mA under a 1.2 V supply.

Um novo circuito amplificador de 50 MHz - 1 GHz com alta linearidade para o padrão IEEE 802.22 “wireless regional area” (WRAN) é apresentado. Ele foi implementado sem nenhum indutor e oferece uma saída diferencial para ser utilizada como balun. Técnicas de cancelamento de ruído e aumento de linearidade foram usadas para melhorar a performace do amplificador de modo que eles pudessem ser otimizados separadamente. A linearidade foi melhorada utilizando transistores conectados como diodo. O amplificador foi implementado em um processo CMOS 130 nm, em uma área compacta de 136 m x 71 m. As simulações são apresentadas para esquemáticos pós-leiaute para duas classes diferentes de projeto: um visando a melhor linearidade e o outro a melhor Figura de Ruído (FR). Quando otimizado para melhor linearidade, os resultados de simulação atingem um ganho de tensão > 23.7 dB (ganho de potência > 19.1 dB), uma figura de ruído < 3.6 dB na banda inteira (com 2.4 dB min), um ponto de intersecção de terceira ordem (IIP3) > 3.3 dBm (7.6 dBm max) e um coeficiente de reflexão de entrada S11 < -16 dB. Quando otimizado para melhor figura de ruído, ele atinge um ganho de tensão > 24.7 dB (ganho de potência > 19.8 dB), uma FR < 2 dB na banda inteira, um IIP3 > -0.3 dBm e um S11 < -11 dB. Resultados de simulação Monte Carlo confirmam baixa sensibilidade à variabilidade de processo. Além disso, uma baixa sensibilidade com a temperatura na faixa de -55 até 125 C foi observada para Ganho, FR e S11. Consumo de potência é 17.6 mA sob fonte de alimentação de 1.2 V. / A new 50 MHz - 1 GHz low-noise amplifier circuit with high linearity for IEEE 802.22 wireless regional area network (WRAN) is presented. It was implemented without any inductor and offers a differential output for balun use. Noise cancelling and linearity boosting techniques were used to improve the amplifier performance in a way they can be separately optimized. Linearity was improved using diode-connected transistors. The amplifier was implemented in a 130 nm CMOS process in a compact 136 m x 71 m area. Simulations are presented for post-layout schematics for two classes of design: one for best linearity, another for best noise figure (NF). When optimized for best linearity, simulation results achieve a voltage gain > 23.7 dB (power gain > 19.1 dB), a NF < 3.6 dB over the entire band (with 2.4 dB min figure), an input third-order intercept point (IIP3) > 3.3 dBm (7.6 dBm max.) and an input power reflection coefficient S11 < -16 dB. When optimized for best NF, it achieves a voltage gain > 24.7 dB (power gain > 19.8 dB), a NF < 2 dB over the entire band, an IIP3 > -0.3 dBm and an S11 < -11 dB. Monte Carlo simulation results confirm low sensitivity to process variations. Also a low sensitivity to temperature within the range -55 to 125 C was observed for Gain, NF and S11. Power consumption is 17.6 mA under a 1.2 V supply.

In this thesis, we present a graphical computer-aided design (CAD) environment for the design, analysis and layout of printed electronic batteries in the first phase and the parasitic extraction of the connecting wires in the second phase. The primary motivation of our work is that this prototyping software tool so far does not exist. Our tool has been integrated within the existing CAD tool which allows quick prototyping and simplifies the interface between the system designer and the device manufacturer. This tools supports the schematic and layout entry, rule checking and netlist generation. The first phase of the device synthesis modelling is based on Enfucell printed batteries, by which using the CAD tool, the shape of the battery is optimized and designed to fit the product and is able to simulate the performance during the optimization, whereas the second phase is the parasitic extraction using an extracting tool named fasthenry, which is integrated to our CAD tool to extract unwanted resistance and inductance within the shared wires between the battery and other devices. We believe that the availability of this tool is useful to the CAD community for novel ideas in the circuit design for flexible hybrid electronics. / +46764354255, +46722694942

L’explosion du marché des télécommunications a donné lieu, lors de ces dernières années, à la multiplication des standards de radiocommunication. De nos jours, l’ensemble de ces moyens de communication utilisés pour le transfert de voix et de données doit être intégré dans les terminaux mobiles. Cependant, cette tendance s’oppose aux contraintes de faible coût qui tendent à diminuer la taille de l’électronique embarquée dans un terminal mobile, mais aussi aux contraintes de diminution de la consommation pour une plus grande autonomie des objets sans fils. C’est donc autour de ces verrous technologiques et techniques que se concentre une part importante des efforts de « R&D » aujourd’hui. Ainsi, l’objectif des travaux présentés repose sur la recherche et le développement d'une architecture contribuant à l’amélioration des performances du bloc central de la chaîne d’émission/réception : l'oscillateur local.L’architecture innovante de synthétiseur de fréquence multistandard réalisée est fondée sur le principe de « conception orientée délai » (DOD - Delay Oriented Design). Une nouvelle technique de stabilisation, issue de la superposition d’une boucle à verrouillage de délai et de phase, est proposée afin d’élargir la bande passante.De l’étude système à la mesure en passant par l’étude comportementale et la réalisation du circuit, les différentes étapes de conception de ce système fractionnaire sont présentées. Les simulations et les mesures ont démontré la capacité du synthétiseur à couvrir une bande comprise entre 1,6 et 3,5GHz avec un signal de référence à 500MHz, mais aussi à stabiliser une architecture très large bande. / The explosion of the wireless communication market is largely responsible of the expansion for RF communication standards for voice and data. Nowadays, each one of them must be integrated in one mobile terminal.However, this trend is opposed to the constraints of low cost, which tend to reduce the size of the electronics in a mobile terminal, but also the constraints of reduced consumption for greater autonomy for wireless systems. It is then around these technological and technical barriers that focus an important part of efforts to « R & D » today. Thus, the objective of the work presented is based on research and development of an architecture that contributes to improve the performances of the central block of transceivers: the local oscillator.The innovative architecture of multistandard synthesizer realized is based on the principle of Delay Oriented Design (DOD). A new technique of stabilization, based on the superposition of a delay and a phase locked loop, is proposed to expand the bandwidth. From study system to measurements through the behavioral comportment and implementation of the circuit, the various stages when designing an RF system are presented. Simulations and measurements have demonstrated the ability of the synthesizer to cover a frequency band between 1.6 and 3.5 GHz with a reference signal at 500MHz, but also to stabilize a broadband architecture.

Ces travaux de thèse portent sur l'accélération de calculs de la cryptographie sur courbes elliptiques (ECC) grâce à une représentation peu habituelle des nombres, appelée représentation modulaire des nombres (ou RNS pour residue number system). Après un état de l'art de l'utilisation du RNS en cryptographie, plusieurs nouveaux algorithmes RNS, plus rapides que ceux de l'état de l'art, sont présentés. Premièrement, nous avons proposé un nouvel algorithme d'inversion modulaire en RNS. Les performances de notre algorithme ont été validées via une implantation FPGA, résultant en une inversion modulaire 5 à 12 fois plus rapide que l'état de l'art, pour les paramètres cryptographiques testés. Deuxièmement, un algorithme de multiplication modulaire RNS a été proposé. Cet algorithme décompose les valeurs en entrée et les calculs, afin de pouvoir réutiliser certaines parties lorsque c'est possible, par exemple lors du calcul d'un carré. Il permet de réduire de près de 25 % le nombre de pré-calculs à stocker et jusqu'à 10 % le nombre de multiplications élémentaires pour certaines applications cryptographiques (p. ex. le logarithme discret). Un algorithme d'exponentiation reprenant les mêmes idées est aussi présenté, réduisant le nombre de multiplications élémentaires de 15 à 22 %, contre un surcoût en pré-calculs à stocker. Troisièmement, un autre algorithme de multiplication modulaire RNS est proposé, ne nécessitant qu'une seule base RNS au lieu de 2 pour l'état de l'art, et utilisable uniquement dans le cadre ECC. Cet algorithme permet, pour certains corps bien spécifiques, de diviser par 2 le nombre de multiplications élémentaires et par 4 les pré-calculs à stocker. Les premiers résultats FPGA donnent des implantations de notre algorithme jusqu'à 2 fois plus petites que celles de l'algorithme de l'état de l'art, pour un surcoût en temps d'au plus 10 %. Finalement, une méthode permettant des tests de divisibilités multiples rapides est proposée, pouvant être utilisée en matériel pour un recodage de scalaire, accélérant certains calculs pour ECC. / The main objective of this PhD thesis is to speedup elliptic curve cryptography (ECC) computations, using the residue number system (RNS). A state-of-art of RNS for cryptographic computations is presented. Then, several new RNS algorithms, faster than state-of-art ones, are proposed. First, a new RNS modular inversion algorithm is presented. This algorithm leads to implementations from 5 to 12 times faster than state-of-art ones, for the standard cryptographic parameters evaluated. Second, a new algorithm for RNS modular multiplication is proposed. In this algorithm, computations are split into independant parts, which can be reused in some computations when operands are reused, for instance to perform a square. It reduces the number of precomputations by 25 % and the number of elementary multiplications up to 10 %, for some cryptographic applications (for example with the discrete logarithm). Using the same idea, an exponentiation algorithm is also proposed. It reduces from 15 % to 22 % the number of elementary multiplications, but requires more precomputations than state-of-art. Third, another modular multiplication algorithm is presented, requiring only one RNS base, instead of 2 for the state-of-art. This algorithm can be used for ECC and well-chosen fields, it divides by 2 the number of elementary multiplications, and by 4 the number of precomputations to store. Partial FPGA implementations of our algorithm halves the area, for a computation time overhead of, at worse, 10 %, compared to state-of-art algorithms. Finally, a method for fast multiple divisibility tests is presented, which can be used in hardware for scalar recoding to accelerate some ECC computations.

This thesis presents the design, construction, and control of a two-wheeled inverted pendulum (TWIP) robotic walker prototype for assisting mobility-impaired users with balance and fall prevention. A conceptual model of the robotic walker is developed and used to illustrate the purpose of this study. A linearized mathematical model of the two-wheeled system is derived using Newtonian mechanics. A control strategy consisting of a decoupled LQR controller and three state variable controllers is developed to stabilize the platform and regulate its behavior with robust disturbance rejection performance. Simulation results reveal that the LQR controller is capable of stabilizing the platform and rejecting external disturbances while the state variable controllers simultaneously regulate the system’s position with smooth and minimum jerk control. A prototype for the two-wheeled system is fabricated and assembled followed by the implementation and tuning of the control algorithms responsible for stabilizing the prototype and regulating its position with optimal performance. Several experiments are conducted, confirming the ability of the decoupled LQR controller to robustly balance the platform while the state variable controllers regulate the platform’s position with smooth and minimum jerk control.

This thesis is concerned with the utilization of formal verification techniques in the design of the functional approximations of combinational circuits. We thoroughly study the existing formal approaches for the approximate equivalence checking and their utilization in the approximate circuit development. We present a new method that integrates the formal techniques into the Cartesian Genetic Programming. The key idea of our approach is to employ a new search strategy that drives the evolution towards promptly verifiable candidate solutions. The proposed method was implemented within ABC synthesis tool. Various parameters of the search strategy were examined and the algorithm's performance was evaluated on the functional approximations of multipliers and adders with operand widths up to 32 and 128 bits respectively. Achieved results show an unprecedented scalability of our approach.