General propose processor (GPP) are demanded high performance in dataintensive applications, such as deep learning, high performance computation (HPC), where algorithm kernels like GEMM (general matrix-matrix multiply) and SPMV (sparse matrix-vector multiply) kernels are intensively used. The performance of these data-intensive applications are bounded with memory bandwidth, which is limited by computing & memory access coupling and memory wall effect. Recent works proposed streaming ISA extensions to maximum memory bandwidth, which decouple computation and memory access, prefetching data by memory access pattern, hiding architecture latency. However, the performance of irregular memory access still suffers from low bus utilization when transferring narrow stream elements on wide memory buses. To solve this problem, the project proposes a new on-chip bus protocol - AXI-PACK, extended from Advance eXtensible Interface4 (AXI4) on-chip protocol, which enables high bandwidth end-to-end irregular memory streaming. Next, an on-chip multi-banked SRAM memory system is designed for supporting AXI-PACK, and AXI-PACK is evaluated under an open-source RISC-V vector processor system. AXI-PACK demonstrates high bus utilization and bandwidth in irregular access, which helps speedup GEMM(element size = 32bits) kernel 6.1 times and SpMV(element size = 32bits) kernel 3.0 times under bus data width of 256 bits, comparing to standard AXI4 bus. / General propose processor (GPP) efterfrågas hög prestanda i dataintensiva applikationer, såsom djupinlärning, högpresterande beräkningar (HPC), där algoritmkärnor som GEMM (generell matris-matris multiplicera) och SPMV (sparse matrix-vector multiply) kärnor används intensivt. Prestandan för dessa dataintensiva applikationer är begränsade till minnesbandbredd, som begränsas av dator & minnesåtkomstkoppling och minnesväggeffekt. Nya arbeten föreslog strömning av ISA-förlängningar till maximal minnesbandbredd, som frikopplar beräkning och minnesåtkomst, förhämtning av data genom minnesåtkomstmönster, döljer arkitekturlatens. Emellertid lider prestandan för oregelbunden minnesåtkomst fortfarande av låg bussanvändning vid överföring av smala strömelement på breda minnesbussar. För att lösa detta problem föreslår projektet ett nytt on-chip-bussprotokoll - AXIPACK, utvidgat från Advance eXtensible Interface4 (AXI4) on-chip-protokoll, vilket möjliggör oregelbunden minnesströmning med hög bandbredd ändetill-ände. Därefter är ett SRAM-minnessystem med flera banker på chip designat för att stödja AXI-PACK, och AXI-PACK utvärderas under ett RISC-V vektorprocessorsystem med öppen källkod. AXI-PACK visar hög bussanvändning och bandbredd vid oregelbunden åtkomst, vilket hjälper till att snabba upp GEMM (elementstorlek = 32 bitar) kärnan 6,1 gånger och SpMV (elementstorlek = 32 bitar) kärnan 3,0 gånger under bussdatabredden på 256 bitar, jämfört med standard AXI4-buss .

This thesis presents the design of a mixed-signal CMOS multiplier implemented with short-channel PMOS transistors. The multiplier presented here forms the product of a differential input voltage and a five-bit digital code. A TSMC 0.18 µm MOSFET model is used to simulate the circuit in Cadence Design Systems. The research presented in this thesis reveals a configuration that allows the multiplier to run at a speed of 8.2 GHz with end-point nonlinearity less than 5%. The high speed and low nonlinearity make this circuit ideal for applications such as filtering and digital to analog conversion.

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Rail à rail entrée - sortie, classe AB, faible consommation sont autant de critères que le concepteur d'amplificateur opérationnel (AOP) intègre pour réaliser une cellule analogique performante. Pour un AOP standard, l'accent n'est pas porté sur une caractéristique particulière mais sur l’ensemble de celle-ci. Dans le but d'augmenter le nombre de fonction par circuit intégré, la tension d'alimentation des AOPs ainsi que leur consommation en courant tendent à diminuer. L'objectif des circuits réalisés est de doubler le facteur de mérite des circuits déjà présents dans le portefeuille de STMicroelectronics. Le facteur de mérite est un indice qui compare des circuits équivalents. Il est défini par le rapport entre le produit capacité de charge x produit gain bande-passante et le produit courant de consommation x tension d'alimentation. L'état de l'art des structures d'AOPs a orienté l'étude vers des structures analogiques possédant au moins trois étages de gain. Un niveau de gain statique supérieur à la centaine de décibel est nécessaire pour utiliser ces amplificateurs dans des systèmes contre-réactionnés. Puisque chaque étage de gain introduit un noeud haute impédance et que chaque noeud haute impédance est à l'origine d'un pôle, l'étude de la compensation fréquentielle s'est avérée indispensable pour obtenir des structures optimisées. Pour simplifier l'étude de ces AOPs, le développement d'outils d'aide à la conception analogique a contribué à l'automatisation de plusieurs tâches.. Ces différents travaux ont été ponctués par la réalisation et la caractérisation de six circuits. Les compensations fréquentielles utilisées dans ces circuits sont la compensation nested miller , la compensation reversed nested miller et la compensation multipath nested miller . Parmi les six circuits, une moitié a été réalisée uniquement dans le but de valider des concepts de compensation fréquentielle et l'autre moitié avec toutes les contraintes d'une documentation technique propre à la famille d'AOP standard. / To be in line with the standard of operational amplifier (opamp), designer integrates in his circuit several functionalities like a Rail to rail input and output, class AB output stage and low power consumption. For standard products, there is no outstanding performance but the average of all of them has to be good. In order to increase the number of functions on an integrated circuit, the power supply and current consumption are permanently decreasing. The aim of the designed circuits is to double the figure of merit (FOM) of the actual ST portfolio products. The FOM allows the comparison of similar opamps. It is defined by the ratio of the product of capacitive load x gain-bandwith product over the power consumption. The opamps’ state of the art has led this study to three stages analog cells. A DC gain higher than hundreds of decibel is required to use opamps in feedback configuration. As each stage of the structure introduces a high impedance node and as each high impedance node introduces a pole, the study of frequency compensation technics became essential for well optimized structures. To simplify the study of the opamps, three tools have been developed to help in the design of the frequency compensation network and to automate some tasks. This work has been followed by the realization of six cells. Three of them were designed to validate frequency compensation structure and the other three to satisfy a standard opamp datasheet. Nested Miller, Reversed Nested Miller and Multipath Nested Miller compensations were used in these circuits.

Dans les années à venir, l’industrie de la microélectronique doit développer de nouvelles filières technologiques qui pourront devenir des successeurs ou des compléments de la technologie CMOS ultime. Parmi ces technologies émergentes relevant du domaine ‘‘Beyond CMOS’’, ce travail de recherche porte sur les transistors mono-électroniques (SET) dont le fonctionnement est basé sur la quantification de la charge électrique, le transport quantique et la répulsion Coulombienne. Les SETs doivent être étudiés à trois niveaux : composants, circuits et système. Ces nouveaux composants, utilisent à leur profit le phénomène dit de blocage de Coulomb permettant le transit des électrons de manière séquentielle, afin de contrôler très précisément le courant véhiculé. Ainsi, le caractère granulaire de la charge électrique dans le transport des électrons par effet tunnel, permet d’envisager la réalisation de transistors et de cellules mémoires à haute densité d’intégration, basse consommation. L’objectif principal de ce travail de thèse est d’explorer et d’évaluer le potentiel des transistors mono-électroniques double-grille métalliques (DG-SETs) pour les circuits logiques numériques. De ce fait, les travaux de recherches proposés sont divisés en trois parties : i) le développement des outils de simulation et tout particulièrement un modèle analytique de DG-SET ; ii) la conception de circuits numériques à base de DGSETs dans une approche ‘‘cellules standards’’ ; et iii) l’exploration d’architectures logiques versatiles à base de DG-SETs en exploitant la double-grille du dispositif. Un modèle analytique pour les DG-SETs métalliques fonctionnant à température ambiante et au-delà est présenté. Ce modèle est basé sur des paramètres physiques et géométriques et implémenté en langage Verilog-A. Il est utilisable pour la conception de circuits analogiques ou numériques hybrides SET-CMOS. A l’aide de cet outil, nous avons conçu, simulé et évalué les performances de circuits logiques à base de DG-SETs afin de mettre en avant leur utilisation dans les futurs circuits ULSI. Une bibliothèque de cellules logiques, à base de DG-SETs, fonctionnant à haute température est présentée. Des résultats remarquables ont été atteints notamment en terme de consommation d’énergie. De plus, des architectures logiques telles que les blocs élémentaires pour le calcul (ALU, SRAM, etc.) ont été conçues entièrement à base de DG-SETs. La flexibilité offerte par la seconde grille du DG-SET a permis de concevoir une nouvelle famille de circuits logiques flexibles à base de portes de transmission. Une réduction du nombre de transistors par fonction et de consommation a été atteinte. Enfin, des analyses Monte-Carlo sont abordées afin de déterminer la robustesse des circuits logiques conçus à l'égard des dispersions technologiques. / In this work, we have presented a physics-based analytical SET model for hybrid SET-CMOS circuit simulations. A realistic SET modeling approach has been used to provide a compact SET model that takes several conduction mechanisms into account and closely matches experimental SET characteristics. The model is implemented in Verilog-A language, and can provide suitable environment to simulate hybrid SET-CMOS architectures. We have presented logic circuit design technique based on double gate metallic SET at room temperature. We have also shown the flexibility that the second gate can bring in order to configure the SET into P-type and N-type. Given that the same device is utilized, the circuit design approach exhibits regularity of the logic gate that simplifies the design process and leads to reduce the increasing process variations. Afterwards, we have addressed a new Boolean logic family based on DG-SET. An evaluation of the performance metrics have been carried out to quantify SET technology at the circuit level and compared to advanced CMOS technology nodes. SET-based static memory was achieved and performances metrics have been discussed. At the architectural level, we have investigated both full DG-SET based arithmetic logic blocks (FA and ALU) and programmable logic circuits to emphasize the low power aspect of the technology. The extra power reduction of SETs based logic gates compared to the CMOS makes this technology much attractive for ultra-low power embedded applications. In this way, architectures based on SETs may offer a new computational paradigm with low power consumption and low voltage operation. We have also addressed a flexible logic design methodology based on DG-SET transmission gates. Unlike conventional design approach, the XOR / XNOR behavior can be efficiently implemented with only 4 transistors. Moreover, this approach allows obtaining reconfigurable XOR / XNOR gates by swapping the cell biasing. Given that the same device is utilized, the structure can be physically implemented and established in a regular manner. Finally, complex logic gates based on DG-SET transmission gates offer an improvement in terms of transistor device count and power consumption compared to standard complementary SETs implementations.Process variations are introduced through our model enabling then a statistical study to better estimate the SET-based circuit performances and robustness. SET features low power but limited operating frequency, i.e. the parasitics linked to the interconnects reduce the circuit operating frequency as the SET Ion current is limited to the nA range. In term of perspectives: i) detailed studying the impact on SET-based logic cells of process variation and random back ground charge ii) considering multi-level computational model and their associate architectures iii) investigating new computation paradigms (neuro-inspired architectures, quantum cellular automata) should be considered for future works.

The present work is dedicated to the development of high performance integrated circuits for wireless communications, by acting of three different levels: technologies, devices, and circuits. Silicon-on-Insulator (SOI) CMOS technology is used in the frame of this work. Micromachining technologies are also investigated for the fabrication of three-dimensional tunable capacitors. The reliability of micromachined thin-film devices is improved by the coating of silanes in both liquid- and vapor-phases. Since in telecommunication applications, distortion is responsible for the generation of spurious frequency bands, the linearity behavior of different SOI transistors is analyzed. The validity range of the existing low-frequency nonlinear characterization methods is discussed. New simple techniques valid at both low- and high-frequencies, are provided, based on the integral function method and on the Volterra series. Finally, the design of a crucial nonlinear circuit, the voltage-controlled oscillator, is introduced. The describing function formalism is used to evaluate the oscillation amplitude and is embedded in a design methodology. The frequency tuning by SOI varactors is analyzed in both small- and large-signal regimes.

Finding an optimal solution for the logic circuit design problem is challenging and time-consuming especially for complex logic circuits. As the number of logic gates increases the task of designing optimal logic circuits extends beyond human capability. A number of evolutionary algorithms have been invented to tackle a range of optimisation problems, including logic circuit design. This dissertation explores two of these evolutionary algorithms i.e. Gene Expression Programming (GEP) and Multi Expression Programming (MEP) with the aim of integrating their strengths into a new Genetic Programming (GP) algorithm. GEP was invented by Candida Ferreira in 1999 and published in 2001 [8]. The GEP algorithm inherits the advantages of the Genetic Algorithm (GA) and GP, and it uses a simple encoding method to solve complex problems [6, 32]. While GEP emerged as powerful due to its simplicity in implementation and exibility in genetic operations, it is not without weaknesses. Some of these inherent weaknesses are discussed in [1, 6, 21]. Like GEP, MEP is a GP-variant that uses linear chromosomes of xed length [23]. A unique feature of MEP is its ability to store multiple solutions of a problem in a single chromosome. MEP also has an ability to implement code-reuse which is achieved through its representation which allow multiple references to a single sub-structure. This dissertation proposes a new GP algorithm, Improved Gene Expression Programming (IGEP) which im- proves the performance of the traditional GEP by combining the code-reuse capability and simplicity of gene encoding method from MEP and GEP, respectively. The results obtained using the IGEP and the traditional GEP show that the two algorithms are comparable in terms of the success rate when applied on simple problems such as basic logic functions. However, for complex problems such as one-bit Full Adder (FA) and AND-OR Arithmetic Logic Unit (ALU) the IGEP performs better than the traditional GEP due to the code-reuse in IGEP / Mathematical Sciences / M. Sc. (Applied Mathematics)

Process variability is a major challenge for the design of nano scale MOSFETs due to fundamental physical limits as well as process control limitations. As the size of the devices is scales down to improve performance, the circuit becomes more sensitive to the process variations. Thus, it is necessary to have a device model that can predict the variations of device characteristics. Statistical modeling method is a potential solution for this problem. The novelty of the work is that we connect BSIM parameters directly to the underlying process parameters. This is very useful for fabs to optimize and control the specific processes to achieve certain circuit metric. This methodology and framework is extendable to any future technologies, because we used a device independent, but process depended frame work In the first part of this thesis, presents the design of nominal MOS devices with 28 nm physical gate length. The device is optimized to meet the specification of low standby power technology specification of International Technology Roadmap for Semiconductors ITRS(2012). Design of experiments are conducted and the following parameters gate length, oxide thickness, halo concentration, anneal temperature and title angle of halo doping are identified as the critical process parameters. The device performance factors saturation current, sub threshold current, output impendence and transconductance are examined under process variabilty. In the subsequent sections of the thesis, BSIM parameter extraction of MOS devices using the software ICCAP is presented. The variability of the spice parameters due to process variation is extracted. Using the extracted data a new BSIM interpolated model for a variability aware circuit design is proposed assume a single process parameter is varying. The model validation is done and error in ICCAP extraction method for process variability is less than 10% for all process variation condition in 3σ range. In the next section, proposes LUT model and interpolated method for a variability aware circuit design for single parameter variation. The error in LUT method for process variability reports less than 3% for all process variation condition in 3σ range. The error in perdition of drain current and intrinsic gain for LUT model files are very close to the result of device simulation. The focus of the work was to established effective method to interlink process and SPICE parameters under variability. This required generating a large number of BSIM parameter ducks. Since there could be some inaccuracy in large set of BSIM parameters, we used LUT as a golden standard. We used LUT modeling as a benchmark for validation of our BSIM3 model In the final section of thesis, impact of multi parameter variation of the processes in device performance is modelled using RSM method; the model is verified using ANOVA method. Models are found to be sufficient and stable. The reported error is less than 1% in all cases. Monte Carlo simulation confirms stability and repeatability of the model. The model for random variabilty of process parameters are formulated using BSIM and compared with the LUT model. The model was tested using a benchmark circuit. The maximum error in Monte Carlo simulation is found to be less than 3% for output current and less than 8% for output impedance.

A scheme for Built-in-Self-Test (BIST) of analog signals with minimal area overhead, for measuring on-chip voltages in an all-digital manner is presented in this thesis. With technology scaling, the inverter switching times are becoming shorter thus leading to better resolution of edges in time. This time resolution is observed to be superior to voltage resolution in the face of reducing supply voltage and increasing variations as physical dimensions shrink. In this thesis, a new method of observability of analog signals is proposed, which is digital-friendly and scalable to future deep sub-micron (DSM) processes. The low-bandwidth analog test voltage is captured as the delay between a pair of clock signals. The delay thus setup is measured digitally in accordance with the desired resolution. Such an approach lends itself easily to distributed manner, where the routing of analog signals over long paths is minimized. A small piece of circuitry, called sampling head (SpH) placed near each test voltage, acts as a transducer converting the test voltage to a delay between a pair of low-frequency clocks. A probe clock and a sampling clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head, present at each test node consists of a pair of delay cells and a pair of flip-flops, giving rise to as many sub-sampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding sub-sampled signal pair is fed to a Delay Measurement Unit (DMU) to measure the skew between this pair. The concept is validated by designing a test chip in UMC 130 nm CMOS process. Sub-mV accuracy for static signals is demonstrated for a measurement time of few milliseconds and ENOB of 5.29 is demonstrated for low bandwidth signals in the absence of sample-and-hold circuitry. The sampling clock is derived from the probe clock using a PLL and the design equations are worked out for optimal performance. To validate the concept, the duty-cycle of the probe clock, whose ON-time is modulated by a sine wave, is measured by the same DMU. Measurement results from FPGA implementation confirm 9 bits of resolution.

Disertační práce je zaměřena na výzkum nejběžnějších metod, které se využívají při návrhu analogových obvodů s využití nízkonapěťových (LV) a nízkopříkonových (LP) struktur. Tyto LV LP obvody mohou být vytvořeny díky vyspělým technologiím nebo také využitím pokročilých technik návrhu. Disertační práce se zabývá právě pokročilými technikami návrhu, především pak nekonvenčními. Mezi tyto techniky patří využití prvků s řízeným substrátem (bulk-driven - BD), s plovoucím hradlem (floating-gate - FG), s kvazi plovoucím hradlem (quasi-floating-gate - QFG), s řízeným substrátem s plovoucím hradlem (bulk-driven floating-gate - BD-FG) a s řízeným substrátem s kvazi plovoucím hradlem (quasi-floating-gate - BD-QFG). Práce je také orientována na možné způsoby implementace známých a moderních aktivních prvků pracujících v napěťovém, proudovém nebo mix-módu. Mezi tyto prvky lze začlenit zesilovače typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za účelem potvrzení funkčnosti a chování výše zmíněných struktur a prvků byly vytvořeny příklady aplikací, které simulují usměrňovací a induktanční vlastnosti diody, dále pak filtry dolní propusti, pásmové propusti a také univerzální filtry. Všechny aktivní prvky a příklady aplikací byly ověřeny pomocí PSpice simulací s využitím parametrů technologie 0,18 m TSMC CMOS. Pro ilustraci přesného a účinného chování struktur je v disertační práci zahrnuto velké množství simulačních výsledků.