Programmable devices require flexible control techniques. The ability the customize settings of the equipment reduces the cost and time of the design phases. On testing phases are commonly used commercial software or spent lot of time on developing hardware and software to specific control. This work proposes a methodology for flexible or configurable control, applied in equipments powered by stepper motors, which are widely used in academic projects and equipments with dedicated applications in industries. The methodology comprises characteristics considered fundamental to the parameterization of the equipment and the environment of operation. To facilitate future applications, the technique is presented using flowcharts and some behavioral diagrams of UML (Unified Modeling Language). To validate the proposed technique were developed a digital circuit and control software, implemented in the programming language C++, according to the characteristics presented in the methodology. The communication performed by USB protocol (Universal Serial Bus) follows the current trend of using this interface to control equipments through computers. / O desenvolvimento de equipamentos programáveis requer técnicas de controle flexível. A possibilidade de parametrização nas configurações do equipamento resulta em menores custos e agilidade nas fases de projeto. Nas fases de testes comumente são usados softwares comerciais fechados ou é gasto tempo dispendioso no desenvolvimento de hardware e software de controle específico. Este trabalho propõe uma metodologia de controle flexível ou configurável, que possibilita o controle de equipamentos acionados por motores de passo, os quais são amplamente usados no projeto e desenvolvimento de equipamentos com aplicações dedicadas nas indústrias. A metodologia contempla características consideradas fundamentais para a parametrização do equipamento e do ambiente de atuação. A técnica é apresentada e descrita por meio de fluxogramas e diagramas comportamentais da linguagem UML (Linguagem de Modelagem Unificada) para facilitar aplicações futuras. Para demonstrar a viabilidade da técnica proposta foram desenvolvidos um circuito digital e um software de controle, implementado na linguagem de programação C++, seguindo as características apresentadas na metodologia. A comunicação realizada pelo protocolo USB (Universal Serial Bus) acompanha a tendência atual de utilização dessa interface, no acionamento de equipamentos através de microcomputadores.

Esta dissertação propõe a utilização da técnica de filtragem adaptativa de pulsos transientes de modo a proteger os circuitos integrados sob efeito da radiação ionizante. Para garantir o uso desta técnica é necessária a utilização de um flip-flop tolerante à radiação que possua a capacidade de ter um ajuste de atraso configurável. O objetivo do uso do flip-flop programável é ter a opção de selecionar o atraso mais apropriado para filtragem temporal de pulsos de SET para cada circuito. Sendo assim, cada flip-flop pode filtrar SETs pelo uso de diferentes atrasos, baseado no atraso de propagação de cada caminho lógico. A variação nos atrasos de propagação entre múltiplos caminhos combinacionais pode ser usada para aumentar ou reduzir o atraso da filtragem de SET. Esta abordagem foi validada com o estudo de caso através de simulação elétrica e pela injeção de milhares de pulsos de SET com diferentes larguras em um circuito com filtragem adaptativa de pulsos tolerantes, os quais foram injetados de forma randômica no circuito. Os resultados mostraram o uso eficiente desta técnica de filtragem de SET em circuitos integrados. De modo a maximizar os resultados, um novo elemento de atraso programável foi desenvolvido e inserido no flip-flop. Para validação deste novo elemento, um segundo estudo de caso, utilizando o conjunto de circuitos dos benchmarks do ISCAS'85 foi também avaliado com a injeção de falhas. Os resultados mostraram que o uso do método proposto, reduz o número de erros sem perda de desempenho e com baixo incremento de área. / This dissertation proposes the use of an adaptive filtering technique of transient pulses in order to protect the integrated circuit under the effect of radiation. To ensure this technique it is necessary to use a tolerant radiation flip-flop having the ability to have a configurable delay adjustment. The purpose of the use a programmable radiation hardened flip-flop is having option of to select the most appropriate delay in the SET temporal filtering for each flip-flop in a circuit. Thus, each flip-flop can filter SETs by using different delays based on the propagation-delay of its logical path. The propagation-delay variances among multiple paths can be used to increase or reduce the delay of the SET filtering. This approach was validated in a case-study by electrical simulation with injection of thousands of SET pulses of different widths, which were randomly injected in a circuit with adaptive filtering technique and the results showed efficient use of this SET filtering technique in integrated circuits. In order to maximize the results of this technique a new programmable delay element was developed and inserted into the flip-flop. This approach of the new element was validated in a second case-study, using a set of benchmark circuits from ISCAS’85 was also evaluated by injecting faults. Results showed that using the proposed method, the number of errors can be reduced without decreasing the performance and with low area overhead.

Esta dissertação propõe a utilização da técnica de filtragem adaptativa de pulsos transientes de modo a proteger os circuitos integrados sob efeito da radiação ionizante. Para garantir o uso desta técnica é necessária a utilização de um flip-flop tolerante à radiação que possua a capacidade de ter um ajuste de atraso configurável. O objetivo do uso do flip-flop programável é ter a opção de selecionar o atraso mais apropriado para filtragem temporal de pulsos de SET para cada circuito. Sendo assim, cada flip-flop pode filtrar SETs pelo uso de diferentes atrasos, baseado no atraso de propagação de cada caminho lógico. A variação nos atrasos de propagação entre múltiplos caminhos combinacionais pode ser usada para aumentar ou reduzir o atraso da filtragem de SET. Esta abordagem foi validada com o estudo de caso através de simulação elétrica e pela injeção de milhares de pulsos de SET com diferentes larguras em um circuito com filtragem adaptativa de pulsos tolerantes, os quais foram injetados de forma randômica no circuito. Os resultados mostraram o uso eficiente desta técnica de filtragem de SET em circuitos integrados. De modo a maximizar os resultados, um novo elemento de atraso programável foi desenvolvido e inserido no flip-flop. Para validação deste novo elemento, um segundo estudo de caso, utilizando o conjunto de circuitos dos benchmarks do ISCAS'85 foi também avaliado com a injeção de falhas. Os resultados mostraram que o uso do método proposto, reduz o número de erros sem perda de desempenho e com baixo incremento de área. / This dissertation proposes the use of an adaptive filtering technique of transient pulses in order to protect the integrated circuit under the effect of radiation. To ensure this technique it is necessary to use a tolerant radiation flip-flop having the ability to have a configurable delay adjustment. The purpose of the use a programmable radiation hardened flip-flop is having option of to select the most appropriate delay in the SET temporal filtering for each flip-flop in a circuit. Thus, each flip-flop can filter SETs by using different delays based on the propagation-delay of its logical path. The propagation-delay variances among multiple paths can be used to increase or reduce the delay of the SET filtering. This approach was validated in a case-study by electrical simulation with injection of thousands of SET pulses of different widths, which were randomly injected in a circuit with adaptive filtering technique and the results showed efficient use of this SET filtering technique in integrated circuits. In order to maximize the results of this technique a new programmable delay element was developed and inserted into the flip-flop. This approach of the new element was validated in a second case-study, using a set of benchmark circuits from ISCAS’85 was also evaluated by injecting faults. Results showed that using the proposed method, the number of errors can be reduced without decreasing the performance and with low area overhead.

Submitted by Fabio Sobreira Campos da Costa (fabio.sobreira@ufpe.br) on 2016-03-15T15:21:11Z No. of bitstreams: 2 license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) TESE_SABRINA.pdf: 1152470 bytes, checksum: a89ffc94cb3ee813cf52ca2c043171ba (MD5) / Made available in DSpace on 2016-03-15T15:21:11Z (GMT). No. of bitstreams: 2 license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) TESE_SABRINA.pdf: 1152470 bytes, checksum: a89ffc94cb3ee813cf52ca2c043171ba (MD5) Previous issue date: 2015-03-31 / Software Product Lines (SPLs) allow engineers to systematically build families of software products, defined by a unique combination of features—increments in functionality, improving both the efficiency of the software development process and the quality of the software developed. However, testing these kinds of systems is challenging, as it may require running each test against a combinatorial number of products. We call this problem the High Dimensionality Problem. Another obstacle to product line testing is the absence of Feature Models (FMs), making it difficult to discover the real causes for test failures. We call this problem the Lack of Feature Model Problem. The High Dimensionality Problem is associated to the large space of possible configurations that an SPL can reach. If an SPL has n boolean features, for example, there are 2n possible feature combinations. Therefore, systematically testing this kind of system may require running each test against all those combinations, in the worst case. The Lack of Feature Model Problem is related to the absence of feature models. The FM enables accurate categorization of failing tests as failures of programs or the tests themselves, not as failures due to inconsistent combinations of features. For this reason, the lack of FM presents a huge challenge to discover the true causes for test failures. Aiming to solve these problems, we propose two lightweight techniques: SPLat and SPLif. SPLat is a new approach to dynamically prune irrelevant configurations: the configurations to run for a test can be determined during test execution by monitoring accesses to configuration variables. As a result, SPLat reduces the number of configurations. Consequently, SPLat is lightweight compared to prior works that used static analysis and heavyweight dynamic execution. SPLif is a technique for testing SPLs that does not require a priori availability of feature models. Our insight is to use a profile of passing and failing test runs to quickly identify test failures that are indicative of a problem (in test or code) as opposed to a manifestation of execution against an inconsistent combination of features. Experimental results show that SPLat effectively identifies relevant configurations with a low overhead. We also apply SPLat on two large configurable systems (Groupon and GCC), and it scaled without much engineering effort. Experimental results demonstrate that SPLif is useful and effective to quickly find tests that fail on consistent configurations, regardless of how complete the FMs are. Furthermore, we evaluated SPLif on one large extensively tested configurable system, GCC, where it helped to reveal 5 new bugs, 3 of which have been fixed after our bug reports. / Software Product Lines (SPLs) allow engineers to systematically build families of software products, defined by a unique combination of features—increments in functionality, improving both the efficiency of the software development process and the quality of the software developed. However, testing these kinds of systems is challenging, as it may require running each test against a combinatorial number of products. We call this problem the High Dimensionality Problem. Another obstacle to product line testing is the absence of Feature Models (FMs), making it difficult to discover the real causes for test failures. We call this problem the Lack of Feature Model Problem. The High Dimensionality Problem is associated to the large space of possible configurations that an SPL can reach. If an SPL has n boolean features, for example, there are 2n possible feature combinations. Therefore, systematically testing this kind of system may require running each test against all those combinations, in the worst case. The Lack of Feature Model Problem is related to the absence of feature models. The FM enables accurate categorization of failing tests as failures of programs or the tests themselves, not as failures due to inconsistent combinations of features. For this reason, the lack of FM presents a huge challenge to discover the true causes for test failures. Aiming to solve these problems, we propose two lightweight techniques: SPLat and SPLif. SPLat is a new approach to dynamically prune irrelevant configurations: the configurations to run for a test can be determined during test execution by monitoring accesses to configuration variables. As a result, SPLat reduces the number of configurations. Consequently, SPLat is lightweight compared to prior works that used static analysis and heavyweight dynamic execution. SPLif is a technique for testing SPLs that does not require a priori availability of feature models. Our insight is to use a profile of passing and failing test runs to quickly identify test failures that are indicative of a problem (in test or code) as opposed to a manifestation of execution against an inconsistent combination of features. Experimental results show that SPLat effectively identifies relevant configurations with a low overhead. We also apply SPLat on two large configurable systems (Groupon and GCC), and it scaled without much engineering effort. Experimental results demonstrate that SPLif is useful and effective to quickly find tests that fail on consistent configurations, regardless of how complete the FMs are. Furthermore, we evaluated SPLif on one large extensively tested configurable system, GCC, where it helped to reveal 5 new bugs, 3 of which have been fixed after our bug reports.

Variability in complex systems offering rich set of features is a seriouschallenge to their users in term of flexibility with many possible variants fordifferent application contexts and maintainability. During the long period oftime, much effort has been made to deal with these issues. An effort in thisregard is developing and implementing different variability modelingtechniques.This thesis argues the explanation of three modeling techniques namedconfigurable components, feature models and function-means trees. The maincontribution to the research includes:• A comparison of above mentioned variability modeling techniques in asystematic way,• An attempt to find the integration possibilities of these modelingtechniques based on literature review, case studies, comparison,discussions, and brainstorming.The comparison is based on three case studies each of which is implemented inall above mentioned three modeling techniques and a set of generic aspects ofthese techniques which are further divided into characteristics. At the end, acomprehensive discussion on the comparison is presented and in final sectionsome integration possibility are proposed on the basis of case studies,characteristics, commonalities and experience gained through theimplementation of case studies and literature review.

This work deals with the design and implementation of a hardware unit that is capable of playing MPEG-1 Layer III files, compliant with ISO/IEC 11172-3. There are given the benefits of using the MP3 format and principles that make it possible to compress the size of the resulting music recordings. The file format and all parts of the header are thoroughly studied as well as the method of encoding information. The process of the data decoding is divided into several consecutive, more or less discrete functional units and these units are designed and described in a hardware description language VHDL. There are also discussed features of FPGA chips - programmable gate arrays. Those are used for physical realization of the MP3 player. A development board is selected, including such an FPGA chip and other resources that allow synthesis of the entire circuit and playback in real time.

Configurable computing machines (CCMs) offer high-performance application acceleration with custom hardware. They are also dynamically reconfigurable and give significant internal visibility. Such features are useful throughout the design, debug, and deploy stages of CCM-based application development. However traditional, monolithic design tools do not offer adequate support for all of these development stages. This thesis describes a specification for a reconfigurable computing application framework (RCAF) which is more suitable for CCM application development. It also describes an implementation of such an RCAF. This RCAF improves the efficiency of application design and debugging. It also establishes an application architecture framework which helps to build up not only the hardware design, but also the application software and user interface. Applications built using this small, deployable RCAF may also perform significantly better due to the dynamic hardware reconfiguration features included with the RCAF.

Reconfigurable computing architectures are well suited for the dynamic data flow processing requirements of software-defined radio. The software radio concept has quickly evolved to include spectrum sensing, awareness, and cognitive algorithms for machine learning resulting in the cognitive radio model. This work explores the application of reconfigurable hardware to the physical layer of cognitive radios using non-contiguous multi-carrier radio techniques. The practical tasks of spectrum sensing, frame detection, synchronization, channel estimation, and mutual interference mitigation are challenges in the communications and the computing fields that are addressed to optimally utilize the capacity of opportunistically allocated spectrum bands. FPGA implementations of parameterizable OFDM and filter bank multi-carrier (FBMC) radio prototypes with spectrum awareness and non-contiguous sub-carrier allocation were completed and tested over-the-air. Sub-carrier sparseness assumptions were validated under practical implementation and performance considerations. A novel algorithm for frame detection and synchronization with mutual interference rejection applicable to the FBMC case was proposed and tested. / Ph. D.

Industrial Control Systems (ICSs) manage critical infrastructures such as water treatment facilities, petroleum refineries, and power plants. ICSs are networked through Information Technology (IT) infrastructure for remote monitoring and control of physical processes. As ICSs integrate with IT infrastructure, IT vulnerabilities are carried over to the ICS environment. Previously proposed process controller security architectures maintain safe and stable plant operation even in the presence of attacks that exploit ICS vulnerabilities. Security architectures are process control system-level solutions that leverage isolated and trusted hardware (secure enclaves) for ICS security. Upon detecting an intrusion, the secure enclave switches control of the physical process to a high assurance controller, making a fail-safe plant operation. The process control loop components have an average lifespan of several decades. During this time, electromechanical components of process control loop may undergo aging that alters their characteristics and affects control loop performance. To deal with component aging and to improve control algorithm flexibility, updates to control loop parameters are required. Plant model, process control loop system specifications, and control algorithm-based security mechanisms at the secure enclave require parameter updates. ICSs have hundreds of process control components that may need be installed in hazardous environments and distributed across hundreds of square kilometers. Updating each component physically may lead to accidents, expensive travel, and increased downtime. Some ICS have allowable downtime of only 5 minutes per year. Hence, remote updates are desirable. A proposed dedicated and isolated hardware module at the secure enclave provides authentication of the update and ensures safe storage in a non-volatile memory. A protocol designed for update transmission through an untrusted ICS network provides resilience against network integrity attacks such as replay attacks. Encryption and authentication of the updates maintain integrity and confidentiality. During the normal plant operation, the hardware module is invisible to the other modules of the process control loop. The proposed solution is implemented on Xilinx Zynq-7000 programmable System-on-Chip to provide secure enclave updates. / Master of Science / Industrial Control Systems (ICSs) manage critical infrastructures such as water treatment facilities, petroleum refineries, and power plants. ICS process controllers interpret sensor output and depending on the set point, generate input signals for the actuator to control physical processes. The process controllers receive set points and periodically send process state to the supervisory network. For remote monitoring and control of physical processes, ICSs are networked through Information Technology (IT) infrastructure. As ICSs integrate with IT infrastructure, IT vulnerabilities are carried over to the ICS environment. Previously proposed process controller security architectures maintain safe and stable plant operation even in the presence of attacks that exploit ICS vulnerabilities. Security architectures are process control system-level solutions that leverage isolated and trusted hardware (secure enclaves) for ICS security. Upon detecting an intrusion, the secure enclave switches control of the physical process to a high assurance controller, making a fail-safe plant operation. The process control loop components have an average lifespan of several decades. During this time, electromechanical components of process control loop may undergo aging that alters their characteristics and affects control loop performance. To deal with component aging and to improve control algorithm flexibility, updates to control loop parameters are required. Plant model, process control loop system specifications, and control algorithm-based security mechanisms at the secure enclave require parameter updates. ICSs have hundreds of process control components that may need be installed in hazardous environments and distributed across hundreds of square kilometers. Updating each component physically may lead to accidents, expensive travel, and increased downtime. Some ICS have allowable downtime of only 5 minutes per year. Hence, remote updates are desirable. A proposed dedicated and isolated hardware module at the secure enclave provides authentication of the update and ensures safe storage in a non-volatile memory. A protocol designed for update transmission through an untrusted ICS network provides resilience against network integrity attacks such as replay attacks. Encryption and authentication of the updates maintain integrity and confidentiality. During the normal plant operation, the hardware module is invisible to the other modules of the process control loop. The proposed solution is implemented on Xilinx Zynq-7000 programmable System-on-Chip to provide secure enclave updates.

La complexité des systèmes sur puce s'accentue pour supporter les nouvelles applications dans le domaine des télécommunications et du multimédia. La tendance actuelle des nouvelles architectures matérielles converge vers des plateformes multi-cœurs à plusieurs unités de calcul (processeurs, DSP, IP) interconnectées par un réseau sur puce qui peut être configurable au niveau de ses interfaces réseau. Pour ce genre d'architectures, les environnements de génération de code classiques ne sont plus adaptés. Cette thèse propose un flot de génération de code de configuration pour le déploiement des applications de type flots de données sur les architectures à base d'IPs interconnectés à travers un réseau sur puce configurable. Le flot commence par un modèle de haut niveau de l'application et de l'architecture et propose une méthodologie de partitionnement des ressources. Le processus de génération de code passe par plusieurs étapes modélisées par diverses représentations intermédiaires du système. Le flot a été développé par la suite dans un environnement basé sur le standard IEEE 1685 (IP-XACT). Le flot proposé a été appliqué pour la génération et la validation du code de configuration en vue de déployer une application 3GPP-LTE de télécommunication sur la plateforme Magali. Le flot a ensuite été généralisé pour supporter, en plus de la génération du code de configuration, la génération du code logiciel exécutable par les processeurs.