Os requisitos de linearidade e ruído em aplicações multi-banda e multi-protocolo fazem que o projeto de misturadores RF seja uma tarefa muito desafiadora. Nesta dissertação dois misturadores com base na topologia célula de Gilbert são propostas. Linearidade e ruído foram as principais figuras de mérito consideradas para o misturadores propostos. Para aumento linearidade, foi utilizada uma técnica de cancelamento de harmônicas pós-distorção (PDHC). E, para redução de ruído, foi utilizado um circuito de redução dinâmica de corrente combinada com um filtro LC sintonizado na frequência do LO e cancelamento de ruído térmico. A análise por séries Volterra do estágio transcondutância do misturador proposto é reportada para mostrar a eficácia da técnica de cancelamento de harmônicos com pósdistorção. O circuito de linearização adicionado não aumenta o tamanho do misturador, nem degrada ganho de conversão, figura de ruído, ou consumo de potência. Simulações elétricas foram realizadas em nível de pós-layout para a primeira topologia e nível esquemático para a segunda topologia, usando processo CMOS de 0.13 mm da IBM. As melhorias em IIP2 e IIP3 são apresentadas em comparação com o misturador do tipo célula de Gilbert convencional. Para a primeira topologia, foi obtido um ganho de conversão de 10.2 dB com uma NF de 12 dB para o misturador projetado funcionando a 2 GHz, com uma frequência intermediária de 500 kHz. E um IIP2 e IIP3 de 55 dBm e 10.9 dBm, respectivamente, consumindo apenas 5.3 mW de uma fonte de 1.2 V. Para a segunda topologia, foram obtidos um ganho de conversão de [13.8 ~11] dB, um coeficiente de reflexão na entrada (S11) de [-18 ~-9.5] dB e um NF de [8.5 ~11] dB no intervalo de 1 a 6 GHz. Para as especificações de linearidade, um valor médio de IIP3 de 0 dBm foi alcançado para toda a faixa de frequência, consumindo 19.3 mW a partir de uma fonte de 1.2 V. Especificações adequadas para operação multi-banda e multi-protocolo. / The linearity and noise requirements in multi-band multi-standard applications make the design of RF CMOS mixers a very challenging task. In this dissertation two downconversion mixers based on the Gilbert-cell topology are proposed. Linearity and noise were the principal figures of merit for the proposed mixers. For linearity improvement, post distortion harmonic cancellation (PDHC) was employed. And, for noise reduction, dynamic current injection combined with an LC filter tuned at the LO frequency and thermal-noise cancellation were used. A Volterra series analysis of the transconductance stage is reported to show the effectiveness of the post-distortion harmonic cancellation technique. The added linearization circuitry does not increase the size of the mixer, nor does it degrade conversion gain, noise figure, or power consumption. Electrical simulations were performed on extracted layout level from the first topology and schematic level from the second topology. Using an IBM 0.13 mm CMOS process improvements on IIP3 and IIP2 in comparison to the conventional Gilbert-cell mixer are demonstrated. For the first topology, we achieved a conversion gain of 10.2 dB with a NF of 12 dB for the designed mixer working at 2 GHz, with a low-IF of 500 kHz and an IIP2 and IIP3 of 55 dBm and 10.9 dBm, respectively, while consuming only 5.3 mW from a 1.2 V supply. For the second topology, we achieved a conversion gain range of [13.8 ~11] dB, an input reflection coefficient (S11) of [-18 ~-9.5] dB and a NF of [8.5 ~11] dB in the frequency range of 1 to 6 GHz. For the linearity specs, an IIP3 of 0 dBm was achieved for the whole frequency range, while consuming 19.3 mW from a 1.2 V supply, making the second topology well suited for multi-band and multi-standard operation.

Os requisitos de linearidade e ruído em aplicações multi-banda e multi-protocolo fazem que o projeto de misturadores RF seja uma tarefa muito desafiadora. Nesta dissertação dois misturadores com base na topologia célula de Gilbert são propostas. Linearidade e ruído foram as principais figuras de mérito consideradas para o misturadores propostos. Para aumento linearidade, foi utilizada uma técnica de cancelamento de harmônicas pós-distorção (PDHC). E, para redução de ruído, foi utilizado um circuito de redução dinâmica de corrente combinada com um filtro LC sintonizado na frequência do LO e cancelamento de ruído térmico. A análise por séries Volterra do estágio transcondutância do misturador proposto é reportada para mostrar a eficácia da técnica de cancelamento de harmônicos com pósdistorção. O circuito de linearização adicionado não aumenta o tamanho do misturador, nem degrada ganho de conversão, figura de ruído, ou consumo de potência. Simulações elétricas foram realizadas em nível de pós-layout para a primeira topologia e nível esquemático para a segunda topologia, usando processo CMOS de 0.13 mm da IBM. As melhorias em IIP2 e IIP3 são apresentadas em comparação com o misturador do tipo célula de Gilbert convencional. Para a primeira topologia, foi obtido um ganho de conversão de 10.2 dB com uma NF de 12 dB para o misturador projetado funcionando a 2 GHz, com uma frequência intermediária de 500 kHz. E um IIP2 e IIP3 de 55 dBm e 10.9 dBm, respectivamente, consumindo apenas 5.3 mW de uma fonte de 1.2 V. Para a segunda topologia, foram obtidos um ganho de conversão de [13.8 ~11] dB, um coeficiente de reflexão na entrada (S11) de [-18 ~-9.5] dB e um NF de [8.5 ~11] dB no intervalo de 1 a 6 GHz. Para as especificações de linearidade, um valor médio de IIP3 de 0 dBm foi alcançado para toda a faixa de frequência, consumindo 19.3 mW a partir de uma fonte de 1.2 V. Especificações adequadas para operação multi-banda e multi-protocolo. / The linearity and noise requirements in multi-band multi-standard applications make the design of RF CMOS mixers a very challenging task. In this dissertation two downconversion mixers based on the Gilbert-cell topology are proposed. Linearity and noise were the principal figures of merit for the proposed mixers. For linearity improvement, post distortion harmonic cancellation (PDHC) was employed. And, for noise reduction, dynamic current injection combined with an LC filter tuned at the LO frequency and thermal-noise cancellation were used. A Volterra series analysis of the transconductance stage is reported to show the effectiveness of the post-distortion harmonic cancellation technique. The added linearization circuitry does not increase the size of the mixer, nor does it degrade conversion gain, noise figure, or power consumption. Electrical simulations were performed on extracted layout level from the first topology and schematic level from the second topology. Using an IBM 0.13 mm CMOS process improvements on IIP3 and IIP2 in comparison to the conventional Gilbert-cell mixer are demonstrated. For the first topology, we achieved a conversion gain of 10.2 dB with a NF of 12 dB for the designed mixer working at 2 GHz, with a low-IF of 500 kHz and an IIP2 and IIP3 of 55 dBm and 10.9 dBm, respectively, while consuming only 5.3 mW from a 1.2 V supply. For the second topology, we achieved a conversion gain range of [13.8 ~11] dB, an input reflection coefficient (S11) of [-18 ~-9.5] dB and a NF of [8.5 ~11] dB in the frequency range of 1 to 6 GHz. For the linearity specs, an IIP3 of 0 dBm was achieved for the whole frequency range, while consuming 19.3 mW from a 1.2 V supply, making the second topology well suited for multi-band and multi-standard operation.

As distorções de forma de componentes mecânicos, que ocorrem durante a fabricação, constituem um sério problema enfrentado pela indústria metal-mecânica. Neste trabalho, avaliou-se uma rota de fabricação de barras de aço ABNT 1045 envolvendo os processos de trefilação, alívio de tensões e têmpera por indução utilizando-se uma visão holística do processo. Após um estudo detalhado, variou-se 5 parâmetros do processo, sendo eles: corrida, ângulo de fieira, ângulo de endireitamento, temperatura de alívio de tensões e profundidade de camada temperada. Caracterizou-se as tensões residuais, em todas as etapas do processo, utilizando-se as técnicas de difração de raios-X, difração de nêutrons e difração de radiação Síncrotron, bem como, a microestrutura do material. Após as etapas de trefilação combinada e tratamento térmico avaliou-se as distorções de forma, utilizando-se um equipamento de medição por coordenadas e posteriormente calculou-se os vetores distorção. Os dados obtidos foram analisados utilizando-se o software Minitab® através da montagem de uma matriz DoE (Design of Experiments). A partir dos resultados obtidos, avaliou-se quais etapas do processo induzem maior "potencial de distorção" nos componentes. A partir das medições de tensões residuais foi obtida uma visão detalhada de como estas tensões residuais se distribuem no material após cada etapa do processo, os dados mostram diferenças significativas ao longo das posições periféricas nas etapas de pré-endireitamento e trefilação. Dados apontam que a distribuição da zona de segregação é responsável pelo comportamento diferente nas duas corridas analisadas em relação às distorções. As tensões residuais geradas no endireitamento do fio-máquina são responsáveis por causar heterogeneidades no material e induzem um alto “potencial de distorção”. Nos parâmetros de processo estudados as deformações induzidas no processo de trefilação não foram capazes de eliminar as distribuições heterogêneas de tensões residuais geradas no pré-endireitamento, porém utilizando-se o ângulo de fieira de 15º houve uma diminuição da distorção após a têmpera por indução. Após o processo de endireitamento por rolos cruzados (PERC) a distribuição das tensões residuais na superfície é mais homogênea para os ângulos de ferramenta avaliados neste trabalho (16º e 18º), entretanto existem diferenças significativas na distribuição de tensões residuais no núcleo do material, e estas diferenças são umas das causadoras das distorções após o processo de têmpera por indução. / Shape distortions are a serious problem in the metalworking industry, distortion due to heat treatment is responsible for additional and cost machining operations. Minimizing or even avoiding heat treatment distortion is one of the key factors to minimize production costs. In the past, investigations had focused on single effects or isolated parameters steps in a manufacturing chain. It is well established now that each step of the process chain generates a “distortion potential” and a new global approach, treating distortion as a system attribute, analyzing the entire manufacturing chain from steelmaking to heat treatment process is necessary. The main idea of distortion engineering is that all steps of the manufacturing chain together contribute to the final distortion behavior. In this work, a steel route of combined cold-drawing process to induction hardening of ABNT 1045 steel bars was investigated. The residual stresses characterizations were carried out using X-ray diffraction, neutron diffraction and synchrotron diffraction methods. The identification and interaction between factors on distortion behavior was carried out using statistical analysis, with the aid of DoE (Design of Experiments). For the DoE method the number of causes that can be considered were 5 parameters of the process, including: different batches, drawing angle, PERC angle, stress relief temperature and induction hardening depth. From the results obtained, the evaluation of which steps in the process induce higher "distortion potential" during the various steps of the process was carried out. From the measurements of residual stresses a detailed view of how these residual stresses are distributed for material in each step of the process was obtained, the results show significant differences along the peripheral positions in the pre-straightening and drawing stages. The experimental results indicate the microstructure of the material, wire rod geometry and the die angle process parameters as main "distortion potentials".

This thesis presents a multiscale investigation and characterization of additive manufactured Polyamide material using fused deposition modelling technique. Manufacturing was performed using Markforgeds – Mark one 3D printer.  A multiscale investigation dedicated to minimizing the effect of shape distortion during 3D printing are presented, focusing on both molecular alignment in microstructure and implementing internal structures in mesostructure. Characterization on samples investigating microstructure was performed with coefficient of linear thermal expansion measurement and 3-point bending experiment. Different samples with varying infill patterns are tested and results indicates an isotropic behaviour through the manufactured samples and implies no molecular alignment due to printing pattern. In meso-structure, an implemented internal pattern is investigated. All samples are measured with 3D scanning equipment to localize and measure the magnitude of shape distortion. Attempts to find relationships in shape distortion and porosity between the samples resulted in no observed trends. Compressive experiments where performed on samples in axial- and transverse directions resulting in anisotropic behaviour. The largest compressive stiffness is recorded in axial direction reaching 0,33 GPa. The study is done in collaboration with Swerea SICOMP and Luleå University of Technology.

The aim of this Master’s thesis is to develop a theoretical introduction to the issue of the image flow time sampling, taking into account the various factors that affect sampling. Furthermore, there is proposed idea diagram of the model, which will simulate the events described, and created the model in the programming environment Matlab. Finally, there are defined the labs that will support teaching dealing with the imaging systems.

The transition from the 5G to the 6G era is a pivotal juncture in contemporary wireless communication. Under such a circumstance, Digital Pre-Distortion (DPD) technology has established its significance as an effective method to linearize Power Amplifiers. However, DPD is facing a series of challenges, notably the increased bandwidth which necessitates more complex modeling techniques. This thesis focuses on the fact that the DPD requires multi-ported memories for the Look-Up-Tables to store correction coefficients, where two research questions are identified. Firstly, this thesis analyses the power, area, and delay-performance trade-offs with an increase in the number of read and write ports of Flip-Flop (FF)-based memories. Secondly, this thesis evaluates and compares the performance of the conventional FF-based multi-ported memories and algorithmic FF-based multi-ported memories. As a Master’s thesis project, this research utilizes the knowledge and practice skills expected of a Master’s student specializing in Embedded Systems. In this thesis, conventional and algorithmic multi-ported memories are implemented and evaluated after studying related works. Subsequently, an industrial Application-Specific Integrated Circuit (ASIC) design flow is executed, undergoing iterative refinements. And in the end, the conclusions are drawn based on an analysis of the software reports. The results underscore that area and power consumption exhibit linear growth alongside increased port numbers within conventional multi-ported memories. Also, the algorithmic multi-ported memory presents a promising alternative, engendering improvements across all three dimensions of delay, area, and power consumption. The implemented memories can be integrated into DPD forward path with customized port numbers in the future, offering adaptability in terms of port configuration and better performance in terms of timing, area and power. Additionally, these implemented memories stand as a valuable point of reference for engineers engaged in the development of FF-based multi-ported memories within the context of ASIC. / Övergången från den 5G- till den 6G- eran är en avgörande tidpunkt inom samtida trådlös kommunikation. Under sådana omständigheter har DPDtekniken etablerat sin betydelse som en effektiv metod för att linjärisera effektförstärkare. Dock står DPD inför en rad utmaningar, särskilt den ökade bandbredden som kräver mer komplexa modelleringstekniker. Denna avhandling fokuserar på det faktum att DPD kräver flerportsminnen för att Look-Up-Tables ska lagra korrigeringskoefficienter, där två forskningsfrågor identifieras. För det första analyserar denna avhandling effekt- , area- och fördröjningsprestanda-avvägningar med en ökning av antalet läs- och skrivportar för FF-baserade minnen. För det andra utvärderar och jämför denna avhandling prestandan hos konventionella FF-baserade multiportade minnen och algoritmiska FF-baserade multiportade minnen. Som ett masteruppsatsprojekt använder denna forskning de kunskaper och övningsfärdigheter som förväntas av en masterstudent som specialiserar sig på inbyggda system. I denna avhandling implementeras och utvärderas konventionella och algoritmiska flerportade minnen efter att ha studerat relaterade arbeten. Nästa steg är att genomföra en industriell ASIC-designflöde som genomgår iterativa förbättringar. Och till slut dras slutsatserna baserat på en analys av mjukvarurapporterna. Denna avhandling understryker att area och strömförbrukning ökar linjärt med ökade portnummer inom konventionella flerportade minnen. Å andra sidan presenterar det algoritmiska flerportade minnet ett lovande alternativ och ger förbättringar inom alla tre dimensioner av fördröjning, area och strömförbrukning. De implementerade minnena kan integreras i DPD-signalförloppet med anpassade portnummer i framtiden och erbjuda anpassningsbarhet när det gäller portkonfiguration och bättre prestanda vad gäller tid, area och ström. Dessutom utgör dessa implementerade minnen en värdefull referenspunkt för ingenjörer som är engagerade i utvecklingen av FF-baserade flerportade minnen inom ramen för ASIC.

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ITC/USA 2006 Conference Proceedings / The Forty-Second Annual International Telemetering Conference and Technical Exhibition / October 23-26, 2006 / Town and Country Resort & Convention Center, San Diego, California / Many satellite payloads require wide-band channels for transmission of large amounts of data to users on the ground. These channels typically have substantial distortions, including bandlimiting distortions and high power amplifier (HPA) nonlinearities that cause substantial degradation of bit error rate performance compared to additive white Gaussian noise (AWGN) scenarios. An adaptive equalization algorithm has been selected as the solution to improving bit error rate performance in the presence of these channel distortions. This paper describes the design and implementation of an adaptive baseband equalizer (ABBE) utilizing the latest FPGA technology. Implementation of the design was arrived at by first constructing a high fidelity channel simulation model, which incorporates worst-case signal impairments over the entire data link. All of the modem digital signal processing functions, including multirate carrier and symbol synchronization, are modeled, in addition to the adaptive complex baseband equalizer. Different feedback and feed-forward tap combinations are considered as part of the design optimization.

ITC/USA 2007 Conference Proceedings / The Forty-Third Annual International Telemetering Conference and Technical Exhibition / October 22-25, 2007 / Riviera Hotel & Convention Center, Las Vegas, Nevada / Historically, aircraft power monitoring has required the use of multiple signal conditioning functions to measure various parameters including voltage, current, frequency and phase. This information was then post processed to determine the characteristics of the 3-phase power quality on the aircraft. Recent developments in embedded DSP processors within signalconditioning systems provide the instrumentation engineer with expanded capabilities for realtime on-board power quality monitoring. Advantages include reduced space and bandwidth requirements and minimal wiring intrusion. For each phase, output data may include peak positive and negative voltages and currents, peak-to-peak, average and RMS voltages and currents, phase power (real and apparent), phase power factor, phase period (frequency), phase shift measurement from phase 1 (the reference phase) to phase 2, and from phase 1 to phase 3. In addition, a Fast Fourier Transform (FFT) is performed on each phase voltage to provide Total Harmonic Distortion measurements. This paper describes the methods employed in the implementation of these functions on a single signal-conditioning card in order to provide detailed information about the power quality of a three-phase aircraft power source.