The focus of this thesis is on specialising the configuration of a field-programmable gate array (FPGA) to allow dynamic reconfiguration of real-time applications. The dynamic reconfiguration of an application has numerous advantages, but due to the overhead introduced by this process, it is only advantageous if the execution time exceeds reconfiguration time. This implies that dynamic reconfiguration is more suited to quasi-static applications, and real-time applications are therefore typically not reconfigured. A method proposed in the literature to ameliorate the overhead from the configuration process is to use a block-RAM (BRAM) based, hardware-controlled reconfiguration architecture, eliminating the need for a processor bus by storing the configuration in localised memory. The drawback of this architecture is the limited size of the BRAM, implying only a subset of configurations can be stored. The work presented in this thesis aim to address this size limitation by proposing a specialiser capable of adapting the configuration stored in the BRAM to represent different sets of hardware. This is done by directly manipulating the bits in the configuration using passive hardware. This not only allows the configuration to be specialised practically immediately, but also allows this specialiser to be device independent. By incorporating this specialiser into the BRAM-based architecture, this study sets out to establish that it is possible to reduce the overhead of the reconfiguration process to such an extent that dynamic reconfiguration can be used for real-time applications. Since the composition of the configuration is not publicly available, a method had to be found to parse and analyse the configuration in order to map the configuration space of the device. The approach used was to compare numerous different configurations and mapping the differences. By analysing these differences, it was found that there is a logical relationship between the slice coordinates and the configuration space of the device. The encoding of the lookup tables was also determined from their initialisation parameters. This allows the configuration of any lookup table to be changed by simply changing the corresponding bits in the configuration. Using this proposed reconfiguration architecture, a distributed multiply-accumulate was reconi figured and its functional density measured. The reason for selecting this specific application is because the multiply-accumulate instruction can be found at the heart of many real-time applications. If the functional density of the reconfigured application is comparable to those of its static equivalent, a strong case can be made for real-time reconfiguration in general. Functional density is an indication of the composite benefits dynamic reconfiguration obtains above its static generic counterpart. Due to the overhead of the reconfiguration process, the functional density of reconfigured applications is traditionally significantly lower than those of static applications. If the functional density of the reconfigured application can rival those of the static equivalent, the overhead from the reconfiguration process becomes negligible. Using this metric, the functional density of the distributed multiply-accumulate was compared for different reconfiguration implementations. It was found that the reconfiguration architecture proposed in this thesis yields a significant improvement over other reconfiguration methods. In fact, the functional density of this method rivalled that of its static equivalent, implying that it is possible to dynamically reconfigure a real-time application. It was also found that the proposed architecture reduces specialisation and reconfiguration time to such an extent that it is possible complete the reconfiguration process within strict time constraints. Even though the proposed method is only capable of reconfiguring the LUTs of a real-time application, this is the first step towards allowing full reconfiguration of applications with dynamic characteristics. The first contribution this thesis makes is a novel method to parse and analyse the configuration of a XilinxR VirtexR -5 FPGA. It also successfully maps the configuration space to the configuration data. Even though this method is applied to a specific device, it is device independent and can easily be applied to any other FPGA. The second contribution comes from using the information obtained from this analysis to design and implement a configuration specialiser, capable of adapting lookup tables in real time. Lastly, the third contribution combines this specialiser with the BRAM-based architecture to allow the reconfiguration of applications typically not reconfigured. / PhD (Computer and Electronic Engineering), North-West University, Potchefstroom Campus, 2015

La complexité croissante de notre environnement socio-économique se traduit en génie logiciel par une augmentation de la taille des systèmes et par conséquent de leur complexité. Les systèmes actuels sont le plus souvent concurrents, distribués à grande échelle et composés d’autre systèmes. Ils sont alors appelés Systèmes de Systèmes (SdS). La complexité des systèmes de systèmes réside dans leurs cinq caractéristiques intrinsèques qui sont : l’indépendance opérationnelle des systèmes constituants, leur indépendance managériale, la distribution géographique, l’existence de comportements émergents, et enfin un processus de développement évolutionnaire. Les SdS évoluent dans des environnements non prévisibles et intègrent constamment de nouveaux systèmes. Nous avons traité la problématique du développement évolutionnaire d’un SdS en utilisant la reconfiguration dynamique. Nous avons défini un processus pour élaborer des modèles de configurations et un processus de conception de la reconfiguration intégrant le concept de patron de reconfiguration. Pour la validité et la faisabilité de notre approche, nous avons développé un framework d’expérimentation basé sur notre cas d’étude réel d’organisation des systèmes de secours français. / The growing complexity of our socio-economic environment is reflected in software engineering by an increase of the size of systems and therefore their complexity. Current systems are mostly concurrent, widely distributed and composed of other systems. They are then called Systems of Systems (SoS). The complexity of systems of systems lies in five intrinsic characteristics: the operational independence of the constituent systems, their managerial independence, the geographical distribution, the existence of emerging behaviours, and finally an evolutionary development process.SoS evolve in unpredictable environment and are constantly integrating new systems. We deal with the problem of the evolutionary development of a SoS by using dynamic reconfiguration. We have defined a process for developing configuration models and a reconfiguration design process incorporating the concept of reconfiguration pattern. For the validity and feasibility of our approach, we have developed an experimental framework based on our real case study of organization of the French emergency service.

With increasing number of applications in Internet and mobile environments, distributed software systems are demanded to be more powerful and flexible, especially in terms of dynamism and security. This dissertation describes my work concerning three aspects: dynamic reconfiguration of component software, security control on middleware applications, and web services dynamic composition. <br><br> Firstly, I proposed a technology named Routing Based Workflow (RBW) to model the execution and management of collaborative components and realize temporary binding for component instances. The temporary binding means component instances are temporarily loaded into a created execution environment to execute their functions, and then are released to their repository after executions. The temporary binding allows to create an idle execution environment for all collaborative components, on which the change operations can be immediately carried out. The changes on execution environment will result in a new collaboration of all involved components, and also greatly simplifies the classical issues arising from dynamic changes, such as consistency preserving etc. <br><br> To demonstrate the feasibility of RBW, I created a dynamic secure middleware system - the Smart Data Server Version 3.0 (SDS3). In SDS3, an open source implementation of CORBA is adopted and modified as the communication infrastructure, and three secure components managed by RBW, are created to enhance the security on the access of deployed applications. SDS3 offers multi-level security control on its applications from strategy control to application-specific detail control. For the management by RBW, the strategy control of SDS3 applications could be dynamically changed by reorganizing the collaboration of the three secure components. <br><br> In addition, I created the Dynamic Services Composer (DSC) based on Apache open source projects, Apache Axis and WSIF. In DSC, RBW is employed to model the interaction and collaboration of web services and to enable the dynamic changes on the flow structure of web services. <br><br> Finally, overall performance tests were made to evaluate the efficiency of the developed RBW and SDS3. The results demonstrated that temporary binding of component instances makes slight impacts on the execution efficiency of components, and the blackout time arising from dynamic changes can be extremely reduced in any applications. / Heutige Softwareanwendungen fuer das Internet und den mobilen Einsatz erfordern bezueglich Funktionalitaet und Sicherheit immer leistungsstaerkere verteilte Softwaresysteme. Diese Dissertation befasst sich mit der dynamischen Rekonfiguration von Komponentensoftware, Sicherheitskontrolle von Middlewareanwendungen und der dynamischen Komposition von Web Services. <br><br> Zuerst wird eine Routing Based Workflow (RBW) Technologie vorgestellt, welche die Ausfuehrung und das Management von kollaborierenden Komponenten modelliert, sowie fuer die Realisierung einer temporaeren Anbindung von Komponenteninstanzen zustaendig ist. D.h., Komponenteninstanzen werden zur Ausfuehrung ihrer Funktionalitaet temporaer in eine geschaffene Ausfuehrungsumgebung geladen und nach Beendigung wieder freigegeben. Die temporaere Anbindung erlaubt das Erstellen einer Ausfuehrungsumgebung, in der Rekonfigurationen unmittelbar vollzogen werden koennen. Aenderungen der Ausfuehrungsumgebung haben neue Kollaborations-Beziehungen der Komponenten zufolge und vereinfachen stark die Schwierigkeiten wie z.B. Konsistenzerhaltung, die mit dynamischen Aenderungen verbunden sind. <br><br> Um die Durchfuehrbarkeit von RBW zu demonstrieren, wurde ein dynamisches, sicheres Middleware System erstellt - der Smart Data Server, Version 3 (SDS3). Bei SDS3 kommt eine Open Source Softwareimplementierung von CORBA zum Einsatz, die modifiziert als Kommunikationsinfrasturkutur genutzt wird. Zudem wurden drei Sicherheitskomponenten erstellt, die von RBW verwaltet werden und die Sicherheit beim Zugriff auf die eingesetzten Anwendungen erhoehen. SDS3 bietet den Anwendungen Sicherheitskontrollfunktionen auf verschiedenen Ebenen, angefangen von einer Strategiekontrolle bis zu anwendungsspezifischen Kontrollfunktionen. Mittels RBW kann die Strategiekontrolle des SDS3 dynamisch durch Reorganisation von Kollabortions-Beziehungen zwischen den Sicherheitskomponenten angepasst werden. <br><br> Neben diesem System wurde der Dynamic Service Composer (DSC) implementiert, welcher auf den Apache Open Source Projekten Apache Axis und WSIF basiert. Im DSC wird RBW eingesetzt, um die Interaktion und Zusammenarbeit von Web Services zu modellieren sowie dynamische Aenderungen der Flussstruktur von Web Services zu ermoeglichen. <br><br> Nach der Implementierung wurden Performance-Tests bezueglich RBW und SDS3 durchgefuehrt. Die Ergebnisse der Tests zeigen, dass eine temporaere Anbindung von Komponenteninstanzen nur einen geringen Einfluss auf die Ausfuehrungseffizienz von Komponeten hat. Ausserdem bestaetigen die Testergebnisse, dass die mit der dynamischen Rekonfiguration verbundene Ausfallzeit extrem niedrig ist.

Notre objectif principal est de permettre l’utilisation de propriétés temporelles dans une politique d’adaptation en tenant compte des spécificités de la vérification à l’exécution.Pour y répondre, nous définissons un modèle de système à composants supportant les reconfigurations dynamiques. Nous introduisons les reconfigurations gardées qui nous permettent d’utiliser des opérations primitives en tant que “briques” pour construire des reconfigurations plus élaborées impliquant des constructions, non seulement, séquentielles, mais aussi alternatives ou répétitives, tout en garantissant la consistance des configurations du système.En outre, nous étendons (aux événements externes) la logique temporelle utilisée précédemment pour exprimer des contraintes architecturales sur des configurations. Avec une sémantique, dite progressive, nous pouvons, dans la plupart des cas, évaluer (de fac¸on centralisée ou décentralisée)une expression temporelle pour une configuration donnée `a partir d’ évaluations déjà réalisées à la seule configuration précédente. Nous utilisons cette logique dans des politiques d’adaptation permettant de guider et contrôler les reconfigurations de systèmes à composants à l’exécution.Enfin, l’implémentation de politiques d’adaptation a été expérimentée dans divers cas d’ études sur les plateformes Fractal et FraSCAti. Nous utilisons notamment le fuzzing comportemental afin de pouvoir tester des aspects spécifiques d’une politique d’adaptation. / Our main goal is to allow the usage of temporal properties within an adaptation policy while takinginto account runtime verification specificities.In order to reach it, we define a component-based system model that supports dynamicreconfigurations. We introduce guarded reconfigurations in order to use primitive operations as“building blocks” to craft more elaborated reconfigurations involving, not only sequential, but also,alternate and repetitive constructs while ensuring the system’s configurations consistency.Furthermore, we extend (to external events) the temporal logic previously used to expressarchitectural constraints on configurations. Using, so called, progressive semantics, we can, in mostof the cases, evaluate (in a centralised or decentralised fashion) a temporal expression for a givenconfiguration using evaluations performed only at the previous configuration. We use this logic withinadaptation policies enabling the steering and control of dynamic reconfigurations at runtime.Finally, we implemented such adaptation policies in various case studies using frameworks such asFractal and FraSCAti. We also use behavioural fuzzing to test various specific aspects of a givenadaptation policy.

Cette thèse porte premièrement sur la reconfiguration dynamique et la simulation hétérogène dans les Réseaux des Capteurs sans Fil. Ces réseaux sont constitués d’une multitude de systèmes électroniques communicants par radio-fréquence, très contraints en énergie. La partie de communication radio entre ces nœuds est la plus consommatrice. C’est pourquoi la minimisation du temps effectif est désirée. On a implémenté une solution qui consiste à envoyer au nœud un fichier de reconfiguration codé utilisant un langage de programmation haut niveau (MinTax). Le nœud sera capable de compiler ce fichier et générer le code object associé à son architecture, in-situ. Grâce au caractère abstrait du MinTax, plusieurs architectures matérielles et systèmes d’exploitation sont visés. Dans un deuxième temps, ce travail de thèse est lié au simulateur de réseaux de capteurs IDEA1TLM.IDEA1TLM permet de prédire quels circuits et configurations sont les plus adéquats à une application sans fil donnée. Ce simulateur a été amélioré pour permettre la simulation rapide des systèmes électroniques matériellement différents dans le même réseau ainsi que le logiciel présent sur les nœuds. / This PhD thesis concerns the dynamic reconfiguration and simulation of heterogeneous Wireless Sensor Networks. These networks consist of a multitude of electronic units called ?nodes ?, which communicate through a radio interface. The radio interface is the most power-consuming on the node. This is why the minimisation of the radio-time would lead to improved energy efficiency. We have implemented a software solution which consists in sending an update to a node which is coded in a high-level language (MinTax). This file is compiled by the node and machine code is generated for the target hardware architecture. Owing to the abstract nature of MinTax, multiple hardware architectures. as well as operating systems are supported. As a second part of this PhD, work has been focused on a network simulator called IDEATLM.IDEA1TLM allows us to predict which circuits and configurations are the most appropriate for a given task. This solution has been improved to allow a faster simulation of electronic systems which are different from a hardware standpoint, yet part of the same network, as well as to model the actual software running on them.

In recent years, reconfigurable devices are developing fast because of its flexibility and less development cost. But intrinsic shortcomings of reconfigurable devices, for example, high power, low speed, etc. induce difficulties in complex designs realizations. So people began to consider combination of ASIC (Application-Specific Integrated Circuit) and reconfigurable device on a single chip, which is SOPC (System on Programmable Chip). SOPC can not only decrease development risk and timing to market, but also be used in different applications, especially of products that keep varying, for example, communication and network products. Dynamically reconfiguration means reconfigurable device of the chip can be reconfigured repeatable, and performs different functions at different times. Compared with static reconfiguration, dynamic reconfiguration can use the reconfigurable device more thoroughly. It‟s a hot spot of research in the world, especially in reconfigurable computing. This paper mainly concludes my research work in reconfigurable SOPC in 3 major parts: hardware, software and application. The following works and innovations are completed: 1. SOPC hardware system architecture design and discussion. Helps to define the system architecture and design goals. The design of EBI controller which is used in the SOPC. The integration of the blocks in the system. 2. The building-up of the SOPC system-level verification and block-level verification environment. The set-up of the hardware-software co-simulation environment. The post-layout simulation and formal verification tasks. We propose an innovative automated regression system. The system helps to achieve the same simulation coverage (95%) and the total simulation time is reduced by approximately 30%. 3. SOPC software design, including the OS kernel porting, drivers design and application design. The design of the PowerPC initialization program and UART (Universal Asynchronous Receiver/Transmitter), reconfiguring communication driver programs. Writing the test-cases which are specialized for the system verification and hardware testing. 4. Being the co-designer of the novel bus macro based on the FDP reconfigurable logic core. And we realize the whole reconfigurable system based on this bus macro. 5. The reconfigurable application research based on Reconfigurable Logic Core. The reconfigurable image filter designed implemented on FDP300K Reconfigurable Logic Core device. Using self-design Reconfigurable Logic Core internal bus macro to implement the partial reconfigurable system. The test results showed that the reconfigurable filter has the feature of fast configuration speed and good output image quality.

Composição de serviços é um tópico que tem atraído cada vez mais o interesse por parte de pesquisadores na área de sistemas distribuídos. Além disso, o interesse por ambientes baseados em nuvem tem crescido significativamente conforme o seu uso aumenta e se firma como um importante modelo de negócios. Coreografias são formas de composições de serviços em que não há pontos centrais de falha; a responsabilidade da sua execução é distribuída entre os vários serviços componentes. Devido à natureza distribuída do fluxo de informações e dados de controle, o cumprimento de \\textit{Service Level Agreements} (SLAs) depende estritamente do monitoramento da Qualidade de Serviços (QoS), recursos virtuais da nuvem e mecanismos de reconfiguração dinâmica, capazes de automaticamente adaptar composições a mudanças de estado no sistema. Nesta dissertação, abordamos o estudo do gerenciamento de QoS em coreografias de serviços. Para isso desenvolvemos um sistema de middleware capaz de implantar e gerenciar o QoS de composições. Este teve seu desempenho avaliado utilizando o serviço Amazon EC2. Os resultados da avaliação mostram que com pouco esforço por parte dos desenvolvedores de composições, é possível cumprir o SLA de composições dentro do esperado utilizando escalabilidade horizontal ou vertical provida pelo middleware automaticamente. Adicionalmente, a nossa proposta traz economias em relação ao custo de implantação pois diminui a quantidade de recursos subutilizados. / Service composition has been a hot topic that has attracted the interesting of researchers in the distributed system area. Moreover, the interesting in cloud computing based environment has grown significantly. Its use has grown and it became to be a important business model. Choreographies are an specific kind of service composition that has no single point of failure; the responsibility of execution is distributed among the services. Due to the distributed nature of the these systems, the fulfilment of Service Level Agreements (SLAs) depends strictly on and automatic way to monitoring Quality of Service (QoS) and virtual computional resources as well as dinamic reconfiguration mechanisms, to be capable of automatically adapting compositions to changing environment. In this work, we studied QoS management in service choreographies. In order, we devised a middleware system capable of deploy service compositions and manage QoS of them. The middleware was evaluated using the Amazon EC2 cloud provider. The results shows that with less effort from the composition providers, it is possible to fulfil SLAs using horizontal or vertical scalability provided by the middleware automatically. Additionaly, our proposal brings up a cost reduction of deploy by decreasing the amount of underused resources.

Sistemas baseados em processadores de uso geral caracterizam-se pela flexibilidade a mudanças de projeto, porém com desempenho computacional abaixo daqueles baseados em circuitos dedicados otimizados. A implementação de algoritmos em dispositivos reconfiguráveis, conhecidos como Field Programmable Gate Arrays - FPGAs, oferece uma solução de compromisso entre a flexibilidade dos processadores e o desempenho dos circuitos dedicados, pois as FPGAs permitem que seus recursos de hardware sejam configurados por software, com uma granularidade menor que a do processador de uso geral e flexibilidade maior que a dos circuitos dedicados. As versões atuais de FPGAs apresentam um tempo de reconfiguração suficientemente pequeno para viabilizar sua reconfiguração dinâmica, i.e., mesmo com o dispositivo executando um algoritmo, a forma como seus recursos são dispostos pode ser alterada, oferecendo a possibilidade de particionar temporalmente um algoritmo. Novas linhas de FPGAs já são fabricadas com opção de reconfiguração dinâmica parcial, i.e., é possível reconfigurar áreas selecionadas de uma FPGA enquanto o restante continua em operação. No entanto, para que esta nova tecnologia se torne largamente difundida é necessário o desenvolvimento de uma metodologia própria, que ofereça soluções eficazes aos novos desdobramentos do projeto digital. Em particular, uma das principais dificuldades apresentadas por esta abordagem refere-se à maneira de particionar o algoritmo, de forma a minimizar o tempo necessário para completar sua tarefa. Este manuscrito oferece uma metodologia de projeto para dispositivos dinamicamente reconfiguráveis, com ênfase no problema do particionamento temporal de circuitos, tendo como aplicação alvo uma família de algoritmos, utilizados principalmente em Bioinformática, representada pelo classificador binário conhecido como Support Vector Machine. Algumas técnicas de particionamento para FPGA Dinamicamente Reconfigurável, especificamente aplicáveis ao particionamento de FSM, foram desenvolvidas para garantir que um projeto dominado por fluxo de controle seja mapeado numa única FPGA, sem alterar sua funcionalidade. / Systems based on general-purpose processors are characterized by a flexibility to design changes, although with a computational performance below those based on optimized dedicated circuits. The implementation of algorithms in reconfigurable devices, known as Field Programmable Gate Arrays, FPGAs, offers a solution with a trade-off between the processor\'s flexibility and the dedicated circuit\'s performance. With FPGAs it is possible to have their hardware resources configured by software, with a smaller granularity than that of the general-purpose processor and greater flexibility than that of dedicated circuits. Current versions of FPGAs present a reconfiguration time sufficiently small as to make feasible dynamic reconfiguration, i.e., even with the device executing an algorithm, the way its resources are displayed can be modified, offering the possibility of temporal partitioning of an algorithm. New lines of FPGAs are already being manufactured with the option of partial dynamic reconfiguration, i.e. it is possible to reconfigure selected areas of an FPGA anytime, while the remainder area continue in operation. However, in order for this new technology to become widely adopted the development of a proper methodology is necessary, which offers efficient solutions to the new stages of the digital project. In particular, one of the main difficulties presented by this approach is related to the way of partitioning the algorithm, in order to minimize the time necessary to complete its task. This manuscript offers a project methodology for dynamically reconfigurable devices, with an emphasis on the problem of the temporal partitioning of circuits, having as a target application a family of algorithms, used mainly in Bioinformatics, represented by the binary classifier known as Support Machine Vector. Some techniques of functional partitioning for Dynamically Reconfigurable FPGA, specifically applicable to partitioning of FSMs, were developed to guarantee that a control flow dominated design be mapped in only one FPGA, without modifying its functionality.

La radio logicielle est une technologie prometteuse pour répondre aux exigences de flexibilité des nouvelles générations de standards de communication. Elle peut être facilement reprogrammée au niveau logiciel pour implémenter différentes formes d'onde. En s'appuyant sur une technologie dite logicielle telle que les microprocesseurs, cette approche est particulièrement flexible et assez facile à mettre en œuvre. Cependant, ce type de technologie conduit généralement à une faible capacité de calcul et, par conséquent, à des débit faibles. Pour résoudre ce problème, la technologie FPGA s'avère être une bonne alternative pour la mise en œuvre de la radio logicielle. En effet, les FPGAs offrent une puissance de calcul élevée et peuvent être reconfigurés. Ainsi, inclure des FPGAs dans le concept de radio logicielle peut permettre de prendre en charge plus de formes d'onde avec des exigences plus strictes qu'une approche basée sur la technologie logicielle. Cependant, les principaux inconvénients d’une conception à base de FPGAs sont le niveau du langage de description d'entrée qui doit typiquement être le niveau matériel, et le temps de reconfiguration qui peut dépasser les exigences d'exécution si le FPGA est entièrement reconfiguré. Pour surmonter ces problèmes, cette thèse propose une méthodologie de conception qui exploite à la fois la synthèse de haut niveau et la reconfiguration dynamique. La méthodologie proposée donne un cadre pour construire une radio flexible pour la radio logicielle à base de FPGAs et qui peut être reconfigurée pendant l'exécution. / Software defined radio (SDR) is a promising technology to tackle flexibility requirements of new generations of communication standards. It can be easily reprogrammed at a software level to implement different waveforms. When relying on a software-based technology such as microprocessors, this approach is clearly flexible and quite easy to design. However, it usually provides low computing capability and therefore low throughput performance. To tackle this issue, FPGA technology turns out to be a good alternative for implementing SDRs. Indeed, FPGAs have both high computing power and reconfiguration capacity. Thus, including FPGAs into the SDR concept may allow to support more waveforms with more strict requirements than a processor-based approach. However, main drawbacks of FPGA design are the level of the input description language that basically needs to be the hardware level, and, the reconfiguration time that may exceed run-time requirements if the complete FPGA is reconfigured. To overcome these issues, this PhD thesis proposes a design methodology that leverages both high-level synthesis tools and dynamic reconfiguration. The proposed methodology is a guideline to completely build a flexible radio for FPGA-based SDR, which can be reconfigured at run-time.

[pt] Algumas características básicas das redes de sensores sem fio (RSSF) dificultam as tarefas de criação e reconfiguração de aplicações. Nesse trabalho apresentamos um modelo de programação que pretende simplificar essas tarefas. O modelo se baseia no uso conjunto de funções parametrizáveis e de máquinas de estados finitos, e permite a implementação de diferentes tipos de aplicações para redes de sensores sem fio e a configuração remota dessas aplicações. Descrevemos alguns testes para avaliar o quanto esse modelo pode facilitar o desenvolvimento de novas aplicações, o quanto é fácil aplicar novas alterações sobre as aplicaçõesem execuçãos, e o impacto na quantidade de mensagens na rede por conta do uso da configuração remota. / [en] Some basic characteristics of wireless sensor networks (WSN) make application creation and reconfiguration dificult tasks. A programming model is presented to simplify these tasks. This model is based on a set of parametrized components and on a Finite State Machine, and allows the remote configuration of different applications over the same set of installed components. We describe some tests to evaluate its impact on the development process, and the ease of applying modifications to a running application. We also measure the additional impact of remote configuration on network activity.