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I det här arbetet har en emulator till DeLavals inbyggda system IOM 200 utvecklats i en Linuxmiljö. Konceptet har varit att implementera en emulator i DeLavals testprocess för mjukvaran i ett inbyggt system. Syftet med emulatorimplementationen var att underlätta utvecklingen av mjukvaran genom att ta bort beroendet av hårdvaran. Baserat på studier av olika metoder, tillgängliga verktyg och tidigare arbeten skapades en emulatormodell för IOM 200 och ett koncept för hur den ska implementeras. Arbetet har även skapat en fungerande prototyp som kan exekvera ett mindre kodsegment från IOM 200 och därigenom validerar emulatormodellen. Emulatormodellen utformades på den redan befintliga FreeRTOS-simulatorn som finns tillgänglig i Linux. Anledningen är att FreeRTOS används i IOM 200, den är gratis att använda och den möter emulatorns abstraktionskrav. Utöver FreeRTOS-simulatorn implementerades stubbar och wrapper-funktioner som tillhandahöll gränssnitt som gjorde IOM 200 applikationen exekverbar i emulatorn. / In this work an emulator for DeLaval’s embedded system IOM 200 has been developed in a Linux environment. The concept was to implement the emulator in DeLaval’s software test process for embedded systems. The purpose of creating an emulator was to ease the development of the embedded software by removing the dependency on embedded hardware. An emulator model and a concept for its implementation was created through the studies of various methods, available tools, and existing works in the emulator field. Based on the model the work created a working prototype that can execute a smaller code segment from the IOM 200 application. The emulator model was designed on the already existing FreeRTOS simulator that is available forLinux. The motive being that FreeRTOS is the operating system running on IOM 200, it is open source, free to use and it has the perfect level of abstraction for the emulator. Stubs and wrappers were implemented to the emulator in addition to the FreeRTOS simulator. These stubs and wrappers provided the interfaces needed for the IOM 200 application to be executable in the emulator.

Många gamla spel som spelades på gamla konsoler och datorer kördes på sammamaskin med två eller flera spelare anslutna med egna individuella kontroller. Idag ärinternet väl utspritt och många spel erbjuder multiplayer-spel via internet. Detta varförstås inte möjligt på de gamla konsolerna och datorerna, men med hjälp av deemulatorer som finns för många gamla plattformar idag kan man skapa möjlighetenatt spela över internet i de gamla spelen genom att skicka varje knapptryckning enspelare utför mellan spelarnas datorer och på det sättet emulera det existerandeflerspelarläget i spelet.Kaillera-protokollet, som är baserat Client-server-arkitekturen, är ett protokolldesignat för att spela gamla spel genom emulatorer över nätverk. Det harimplementerats i ett antal populära emulatorer med hjälp av ett tredjepartsbibliotekmed samma namn. Kaillera fungerar genom att synkronisera spelarnas input for eachbild som visas i spelet. Kaillera-protokollet har ett antal tillkortakommanden, tillexempel:• Protokollet är enbart Client-server, och det finns ingen peer-to-peer-variant.• Protokollet är stängt och inte dokumenterat.• Protokollet använder UDP för alla överföringar, vilket gör det svårt att föraöver kritisk data.• Programmerargränssnittet som tillhör Kaillera-biblioteket är mycket begränsatoch ger inte emulatorutvecklaren mycket utrymme närKkaillera skaimplementeras.Den här rapporten beskrver en ny öppen implementation av Kaillera-protokollet ochen ny variant av Kaillera-protokollet som är peer-to-peer-baserat. Rapporten består tillstörsta del av en teknisk beskrivning av ett nytt mjukvarubibliotek som är öppenkällkod (LGPL), Plattformsoberoende och med ett mer flexibelt utvecklargränssnittjämfört med den officiella implementationen av Kaillera-protokollet. Slutligenbeskrivs också ett experiment för att testa hur den nya Kaillera-implementationen stårsig emot det nya peer-to-peer-protokollet med avseende på prestanda, där man kundevisa att den mellanliggande servern kan vara ett prestandaproblem. / Program: Systemarkitekturutbildningen

In the System-on-Chip (SoC) era, common industry estimates are that functional verification takes approximately 70% of the total effort on a project. For the time-to-market constrain, it¡¦s a challenge to reduce the SoC verification/debugging time efficiently. In an SoC, a microprocessor is an essential part of it. First, we focus the debugging problem on microprocessors. An in-circuit emulation (ICE) module that can be embedded with a microprocessor core. The ICE module, based on the IEEE 1149.1 JTAG architecture, supports typical debugging and testing mechanisms, including boundary scan paths, partial scan paths, single stepping, internal resource monitoring and modification, breakpoint detection, and mode switching between debugging and normal modes. The architecture of the ICE module is parameterized and retargetable to different microprocessors. It has been successfully integrated with two microprocessors with significantly different architectures: one 8-bit industrial embedded microcontroller HT48x00 and one 32-bit ARM7-like embedded microprocessor. FPGA prototypes and chip implementation have been accomplished. Experiments show that real-time (on-line) debugging at full speed is possible with the embedded ICE at a minor gate count overhead. Collecting the program execution traces at full speed is essential to the analysis and debugging of real-time software behavior of a complex system. However, the generation rate and the size of real time program traces are so huge such that real-time program tracing is often infeasible without proper hardware support. This paper presents a hardware approach to compress program execution traces in real time in order to reduce the trace size. The approach consists of three modularized phases: (1) branch/target filtering, (2) branch/target address encoding and (3) Lempel-Ziv-based data compression. A synthesizable RTL code for the proposed hardware is constructed to analyze the hardware cost and speed and typical multimedia benchmarks are used to measure the compression results. The results show that our hardware is capable of real time compression and achieving compression ratio of 454:1, far better than 5:1 achieved by typical existing hardware approaches. Furthermore, our modularized approach makes it possible to trade off between the hardware cost (typically from 1K to 50K gates) and the achievable compression ratio (typically from 5:1 to 454:1). For SoC debugging, bus signal tracing represents that the information which is generated from the system can be collected for later observation, debugging and analysis. However, the generation rate and the size of real time system traces are so huge such that a mechanism for system tracing that can reduce trace size efficiently is needed. In this paper, we propose a multi-resolution bus trace approach. The hardware bus tracer consists of two major stages: (1) signal monitor & tracing stage, and (2) trace compression stage. In the first stage, designer can trace the signals in detail or in rough depends on the debug purpose. In other word, the multi-resolution trace approach provides the trade-off between trace accuracy and trace depth. In the second stage, the bus tracer compresses the trace size efficiently; therefore the capability of on-chip storage is increased. In the host, the analyzer tool decompresses the trace data for future observation and debugging.

With the advanced of the technique, we can design more IP in the same area space chip. The embedded system has more powerful about its application. We need to have a more efficient core processor to support the whole embedded system in complex system environment. The main purpose of this paper is increased the calculated speed, memory management and debugging for SYS32TME III, which is designed by our lab as an ARM10 like processor. We integrate the cache/MMU and EICE( Embedded in-circuit emulator ) into the embedded processor core. Using the cache/MMU, we can not only speed up the processor which access external memory time but also use the virtual address for Operating System. In order to keep the correctness of the system and speed up the system integration time, we use five functional (cache off, cache on and MMU off with cache hit/miss, cache on and MMU on with cach hit/cache miss and TLB hit/cache miss and TLB miss) tests to verify the cache/MMU and six coprocessor instructions (LDC, MCR, MCRR, MRC, MRRC, STC ) to verify the EICE. After that, we also use the regression test about the microprocessor, cache/MMU and EICE system integration. In the end, we turned the performance about the integrated cache/MMU and EICE, so that we can support an 200MHz ARM 10-like processor by 0.18£gm.

OpenGL ES 2.0 is the newest 3D graphics technology for hand-held devices established by Khronos. Users need a shading language compiler and a graphics card which is supportive for OpenGL ES 2.0 to develop their application on OpenGL ES 2.0. Without a graphcis processing unit and a corresponding compiler, one can not develop a 3D graphics application based on OpenGL ES 2.0. In order to solve these problems, we proposed an emulator for OpenGL ES 2.0 based on C-language compiler. The proposed emulator applies C-language compiler and CPU to fulfill the specification of OpenGL ES 2.0. With the proposed emulator, application developers can develop a 3D graphics application for OpenGL ES 2.0 without a specific hardware and a corresponding compiler and hardware designers also can compare and debug when designing their own graphics processing unit.

In recent years there has been a predominant increase in multimedia services such as live streaming, Video on Demand (VoD), video conferencing, videos for the learning. Streaming of high quality videos has become a challenge for service providers to enhance the user’s watching experience. The service providers cannot guarantee the perceived quality. In order to enhance the user’s expectations, it is also important to estimate the quality of video perceived by the user. There are different video streaming protocols that are used to stream from server to client. In this research, we aren’t focused on the user’s experience. We are mainly focused on the performance behavior of the protocols. In this study, we investigate the performance of the HTTP, RTSP and WebRTC protocols when streaming is carried out for H.265 encoder. The study addresses for the objective assessment of different protocols over VoD streaming at the network and application layers. Packet loss and delay variations are altered at the network layer using network emulator NetEm when streaming from server to client. The metrics at the network layer and application layer are collected and analyzed. The video is streamed from server to a client, the quality of the video is checked by some of the users. The research method has been carried out using an experimental testbed. The metrics such as packet counts at network layer and stream bitrate at application layer are collected for HTTP, RTSP and WebRTC protocols. Variable delays and packet losses are injected into the network to emulate real world. Based on the results obtained, it was found at the application layer that, out of the three protocols, HTTP, RTSP and WebRTC, the stream bitrate of the video transmitted using HTTP was less when compared to the other. Hence, HTTP performs better in the application layer. At the network layer, the packet counts of the video transmitted were collected using TCP port for HTTP and UDP port for RTSP and WebRTC protocols. The performance of HTTP was found to be stable in most of the scenarios. On comparing RTSP and WebRTC, the number of packet counts collected were more in number for RTSP when compared to WebRTC. This is because, the protocol and also the streamer are using more resources to transmit the video. Hence, both the protocols RTSP and WebRTC are performing better relatively.

Zugl.: Chemnitz, Techn. Univ., Diss., 2008

This thesis analyzes the design and performance of a photovoltaic (PV) emulator. With increasing interest in renewable energies, large amounts of money and effort are being put into research and development for photovoltaic systems. The larger interest in PV systems has increased demand for appropriate equipment with which to test PV systems. A photovoltaic emulator is a power supply with similar current and voltage characteristics as a PV panel. This work uses an existing power supply which is manipulated via Labview to emulate a photovoltaic panel. The emulator calculates a current-voltage (I-V) curve based on the user specified parameters of panel model, irradiance and temperature. When a load change occurs, the power supply changes its current and voltage to track the calculated I-V curve, so as to mimic a solar panel. Over 250 different solar panels at varying irradiances and temperatures are able to be accurately emulated. A PV emulator provides a controlled environment that is not affected by external factors such as temperature and weather. This allows repeatable conditions on which to test PV equipment, such as inverters, and provides a controlled environment to test an overall PV system.

Eight-bit computer ZX Spectrum has been created 30 years ago. It was extremely popular in its time and it has many fans till now, which still developing new application and games. There are also many new hardware extensions like IDE HDD driver, SD/MMC memory driver etc. The aim of this thesis is the design and develop of ZX Spectrum emulator, which will be based on modern PFGA technology and it will use modern periphery like VGA monitor, SD/MMC memory cards etc.