Silicon photonics is emerging as a potential field to achieve optical interconnects towards the realization of ultra high bandwidth. The indirect band-gap property of silicon still remains as a big challenge to incorporate silicon photonic active device, for example, silicon-based laser. In the Laboratory of Semiconductor Materials at KTH, a monolithic integration platform based on nano-epitaxial lateral overgrowth (nano-ELOG) technique has been proposed to integrate III-V semiconductor materials with silicon for light source application. The integration process involves uneven surface morphology at different stages. The surfaces of the indium phosphide seed layer on silicon used for ELOG, the mask deposited on it (the silicon/silicon dioxide waveguide) and the ELOG indium phosphide layer grown on it prior to laser growth are often rough. In this thesis work, we have optimized chemical mechanical polishing (CMP) technique in order to achieve an even surface. The same procedure is also necessary to reach the optimal thickness of different layers to enable effective coupling of light from the laser source into the waveguide. CMP of indium phosphide to obtain an average surface roughness of < 1 nm has been optimized by a two-step polishing using different slurries; it results in a step height of ca 3 nm. Similarly the surface of silicon/silicon dioxide “waveguide” has also been optimized with the roughness of ~ 0.5 nm. In the latter case, a step height of 40 nm is retained and this increase with respect to InP is identified to be mainly due to limitations of the polishing machine which is different from that used for indium phosphide. The reduction in step heights with polishing time is analyzed and compared with an existing theoretical model. Our results are in good qualitative agreement with the model. The optimized surface morphology obtained in this work was tested for its suitability for integration. For this evaluation, InP was grown by ELOG in a hydride vapour phase epitaxy reactor with and without CMP of the involved surfaces. The surface after CMP yields layers of better surface morphology with fewer defects as revealed by atomic force microscopy, surface profilometer and cathodoluminescence analysis. The results indicate that the CMP process is useful for monolithic integration for silicon photonics.

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第18982号 / 工博第4024号 / 新制||工||1620(附属図書館) / 31933 / 京都大学大学院工学研究科材料工学専攻 / (主査)教授 田中 功, 教授 酒井 明, 教授 邑瀬 邦明 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第19187号 / 工博第4064号 / 新制||工||1627(附属図書館) / 32179 / 京都大学大学院工学研究科物質エネルギー化学専攻 / (主査)教授 陰山 洋, 教授 阿部 竜, 教授 田中 勝久 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DGAM

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第19720号 / 工博第4175号 / 新制||工||1644(附属図書館) / 32756 / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 川上 養一, 教授 田中 勝久, 准教授 掛谷 一弘 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第19721号 / 工博第4176号 / 新制||工||1644(附属図書館) / 32757 / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 藤田 静雄, 教授 髙岡 義寛, 准教授 須田 淳 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

While investigations of semiconductor nanowires (NWs) has a long history, a significant progress is yet to be made in silicon carbide (SiC) NW technologies before they are ready to be utilized in electronic applications. In this dissertation work, SiC NW polytype control, NW axis orientation with respect to the growth substrate and other issues of potential technological importance are investigated. A new method for growing SiC NWs by vapor-liquid-solid mechanism was developed. The method is based on an in-situ vapor phase delivery of a metal catalyst to the growth surface during chemical vapor deposition. This approach is an alternative to the existing seeded catalyst method based on ex-situ catalyst deposition on the target substrate. The new SiC NW growth method provided an improved control of the NW density. It was established that the NW density is influenced by the distance from the catalyst source to the substrate and is affected by both the gas flow rate and the catalyst diffusion in the gas phase. An important convenience of the new method is that it yields NW growth on the horizontal substrate surfaces as well as on titled and vertical sidewalls of 4H-SiC mesas. This feature facilitates investigation of the NW growth trends on SiC substrate surfaces having different crystallographic orientations simultaneously, which is very promising for future NW device applications. It was established that only certain orientations of the NW axes were allowed when growing on a SiC substrate. The allowed orientations of NWs of a particular polytype were determined by the crystallographic orientation of the substrate. This substrate-dependent (i.e., epitaxial) growth resulted in growth of 3C-SiC NWs in total six allowed crystallographic orientations with respect to the 4H-SiC substrate. This NW axis alignment offers an opportunity to achieve a limited number of NW axis directions depending on the surface orientation of the substrate. The ease of controlling the NW density enabled by the vapor-phase catalyst delivery approach developed in this work, combined with the newly obtained knowledge about how to grow unidirectional (wellaligned) NW arrays, offer new opportunities for developing novel SiC NW electronic and photonic devices.

<p> This thesis presents an investigation of the electron-voltaic effect using epitaxial P-N junctions. The effect is manifested in the direct energy conversion of beta particles emitted from a radioisotope promethium^147 source by single and multi-junction devices. The purpose of the investigation is to determine the power outputs of the devices which may be combined in series and parallel combinations in the construction of an atomic battery with a small size and long lifetime (approximately 5 -10 years). </p> / Thesis / Master of Science (MSc)

GaN holds significant potential as a material for vertical p-n diodes, enabling the realization of devices with reverse breakdown voltages of 5 kV or higher. Carbon serves as the primary compensating dopant in the growth process, incorporated into GaN during metalorganic chemical vapor deposition (MOCVD) growth. The level of carbon incorporation depends on several factors, including growth rate, ammonia flow, temperature, pressure, and trimethylgallium (TMGa) flow. Through guided empirical modeling, it was demonstrated that the carbon incorporation in GaN growth could be predicted using a single parameter based on the ratio of ammonia flow to the growth rate. This model accurately predicts carbon concentrations ranging from 1x1017 to 5x1014 cm-3 while allowing for maximized growth rates. Other extrinsic dopants have either been reduced below the threshold of consideration or modeled using similar single-parameter relationships. By identifying the dominant extrinsic dopants and accounting for them, an intrinsic defect with a concentration of 2.2x1015 cm-3 was identified. By combining these relationships, growth conditions for n-GaN were optimized, resulting in electron concentrations as low as 1x1015 cm-3. Leveraging these techniques, p-n diodes were grown, achieving a reverse breakdown voltage as high as 3.1 kV. / Doctor of Philosophy / Power electronic devices based on vertical GaN have the potential to revolutionize applications such as electric vehicles, solar charging systems, and the smart grid. However, there are significant materials challenges that need to be addressed in order to realize these devices. They must be extremely pure and extremely thick. Unfortunately, the primary source of these materials also contains carbon, which can negatively impact purity. To overcome this challenge, an empirical model for the growth process has been developed. This model enables independent control over the carbon source and the removal of carbon, using a single parameter. By leveraging this model, it becomes possible to optimize the trade-off between high purity, high growth rates, and ideal electronic properties. Using these techniques, devices were grown with next-generation levels of performance at minimal time and cost.

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