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The aim for this thesis is to design a software library responsible for preventing, detecting, handling and logging faults caused by radiation in a representable flight computer system based on the Cobham Gaisler GR740 quad-core LEON4FT processor chip. The LEON processor family is commonly used in space applications and it is based on the open SPARC instruction set and has been extended with fault tolerant features to cope with both on-chip radiation effects as well as upsets in external memory. The new GR740 device introduces a new computer architecture with multiple buses as compared to previous chips, Level-2 cache and a memory scrubber accelerating fault mitigation in external SDRAM memories. As the processor system design keeps getting more complex it also requires software to handle more hardware and new events, including central handling and logging routines of faults. The report describes the analysis performed to identify sources of faults and proposed suitable mitigation techniques, the established software requirements and how they are translated into a software architecture, then implemented and finally demonstrated on hardware. Along with this, it is shown how the developed demonstrator application software library can be integrated into the RTEMS real-time operating system commonly used in European space missions. The results are based on the demonstrator execution, and the results show that the software is functionally working and validates that the performance of the scrubber matches the derived scrubbing timings. After the project is completed, the software library design will be evaluated for use in Cobham Gaisler’s payload computer platform for the GOMX-5 mission. Radiation upsets will be emulated by injecting faults while running the developed API on demonstrator applications. Furthermore, implementation of software into NASA cFS/cFE will be analysed.

The company Ericsson is taking steps towards embracing automating techniques and applying them to their product development cycle. Ericsson wants to apply machine learning techniques to automate the evaluation of a text categorization problem of error reports, or trouble reports (TRs). An excess of 100,000 TRs are handled annually. This thesis presents two possible solutions for solving the routing problems where one technique uses traditional classifiers (Multinomial Naive Bayes and Support Vector Machines) for deciding the route through the company hierarchy where a specific TR belongs. The other solution utilizes a Convolutional Neural Network for translating the TRs into low-dimensional word vectors, or word embeddings, in order to be able to classify what group within the company should be responsible for the handling of the TR. The traditional classifiers achieve up to 83% accuracy and the Convolutional Neural Network achieve up to 71% accuracy in the task of predicting the correct class for a specific TR.

Les techniques de gestion dynamique de la tension (DVS) sont principalement utilisés dans la conception de circuits numériques pour en améliorer l'efficacité énergétique. Cependant, la réduction de la tension d'alimentation augmente l'impact de la variabilité et des erreurs temporelles dans les technologies nano-métriques. L'objectif principal de cette thèse est de gérer les erreurs temporelles et de formuler un cadre pour estimer la consommation d'énergie d'applications résistantes aux erreurs dans le contexte du régime proche du seuil (NTR) des transistors. Dans cette thèse, la détection et la correction d'erreurs basées sur la spéculation dynamique sont explorées dans le contexte de l'adaptation de la tension et de la fréquence d‘horloge. Outre la détection et la correction des erreurs, certaines erreurs peuvent être également tolérées et les circuits peuvent calculer au-delà de leurs limites avec une précision réduite pour obtenir une plus grande efficacité énergétique. La méthode de détection et de correction d'erreur proposée atteint 71% d'overclocking avec seulement 2% de surcoût matériel. Ce travail implique une étude approfondie au niveau des portes logiques pour comprendre le comportement des portes sous l'effet de modification de la tension d'alimentation, de la tension de polarisation et de la fréquence d'horloge. Une approche ascendante est prise en étudiant les tendances de l'énergie par rapport a l'erreur des opérateurs arithmétiques au niveau du transistor. En se basant sur le profilage des opérateurs, un flot d'outils est formulé pour estimer les paramètres d'énergie et d'erreur pour différentes configurations. Nous atteignons une efficacité énergétique maximale de 89% pour les opérateurs arithmétiques comme les additionneurs 8 bits et 16 bits au prix de 20% de bits défectueux en opérant en NTR. Un modèle statistique est développé pour que les opérateurs arithmétiques représentent le comportement des opérateurs pour différents impacts de variabilité. Ce modèle est utilisé pour le calcul approximatif dans les applications qui peuvent tolérer une marge d'erreur acceptable. Cette méthode est ensuite explorée pour unité d'exécution d'un processeur VLIW. L'environnement proposé fournit une estimation rapide des indicateurs d'énergie et d'erreurs d'un programme de référence par compilation simple d'un programme C. Dans cette méthode d'estimation de l'énergie, la caractérisation des opérateurs se fait au niveau du transistor, et l'estimation de l'énergie se fait au niveau fonctionnel. Cette approche hybride rend l'estimation de l'énergie plus rapide et plus précise pour différentes configurations. Les résultats d'estimation pour différents programmes de référence montrent une précision de 98% par rapport à la simulation SPICE. / Dynamic voltage scaling (DVS) technique is primarily used in digital design to enhance the energy efficiency by reducing the supply voltage of the design. However reduction in Vdd augments the impact of variability and timing errors in sub-nanometer designs. The main objective of this work is to handle timing errors, and to formulate a framework to estimate energy consumption of error resilient applications in the context of near-threshold regime (NTR). In this thesis, Dynamic Speculation based error detection and correction is explored in the context of adaptive voltage and clock overscaling. Apart from error detection and correction, some errors can also be tolerated or, in other words, circuits can be pushed beyond their limits to compute incorrectly to achieve higher energy efficiency. The proposed error detection and correction method achieves 71% overclocking with 2% additional hardware cost. This work involves extensive study of design at gate level to understand the behaviour of gates under overscaling of supply voltage, bias voltage and clock frequency (collectively called as operating triads). A bottom-up approach is taken: by studying trends of energy vs. error of basic arithmetic operators at transistor level. Based on the profiling of arithmetic operators, a tool flow is formulated to estimate energy and error metrics for different operating triads. We achieve maximum energy efficiency of 89% for arithmetic operators like 8-bit and 16-bit adders at the cost of 20% faulty bits by operating in NTR. A statistical model is developed for the arithmetic operators to represent the behaviour of the operators for different variability impacts. This model is used for approximate computing of error resilient applications that can tolerate acceptable margin of errors. This method is further explored for execution unit of a VLIW processor. The proposed framework provides quick estimation of energy and error metrics of a benchmark programs by simple compilation in a C compiler. In the proposed energy estimation framework, characterization of arithmetic operators is done at transistor level, and the energy estimation is done at functional level. This hybrid approach makes energy estimation faster and accurate for different operating triads. The proposed framework estimates energy for different benchmark programs with 98% accuracy compared to SPICE simulation.

付記する学位プログラム名: デザイン学大学院連携プログラム / 京都大学 / 0048 / 新制・課程博士 / 博士(情報学) / 甲第21217号 / 情博第670号 / 新制||情||115(附属図書館) / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 五十嵐 淳, 教授 石田 亨, 教授 山本 章博 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

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Dagens applikationer är alltmer byggda enligt en mikrotjänstarkitektur istället för den klassiska monolitiska formen. I en mikrotjänstarkitektur har tjänster beroenden av varandra. Detta betyder att systemet måste kunna hantera situationer där dessa beroenden inte kan mötas. För att lösa de problemen som kan uppstå krävs ett felhanteringssystem som försäkrar att viktiga delar inte korrumperas eller går förlorad. Denna studie tar fram en modell på ett felhanteringssystem, och föreslår ett flertal teknologier som kan användas för en praktisk implementation av felhanteringssystemet. En fallstudie genomförs för att visa att teknologierna kan användas för att realisera modellen i en simulerad produktionsmiljö. Undersökningen föreslår en plattformsoberoende modell av Saga-mönstret som förhindrar korrumperad data, och ett återhämtningssystem som med hjälp av en meddelandekö kan återskapa förlorad data. Det framtagna felhanteringssystemet utvärderas utifrån de krav och begränsningar som ställs av beställaren, Asteria AB. Studien ger en generell lösning för de problem, som uppstår i en mikrotjänstarkitektur vid störningar och avbrott. Detta gör det möjligt att återanvända lösningen i olika kontext med minimala ändringar. / Today's applications are increasingly built according to a microservice architecture instead of the classic monolithic pattern. In a microservice architecture, services are interdependent. This means that the system must be able to handle situations where these dependencies cannot be met. To solve the problems that may arise, an error handling system is required that ensures that important parts are not corrupted or lost. This study develops a model of a fault management system, and proposes several technologies that can be used for a practical implementation of the fault management system. A case study is conducted to show that the technologies can be used to realize the model in a simulated production environment. The study proposes a platform-independent model of the Saga pattern that prevents corrupted data, and a recovery system that can recover lost data using a message queue. The developed error handling system is evaluated on the basis of the requirements and limitations set by the customer, Asteria AB. The study provides a general solution to the problems that arise in a microservice architecture in the event of disruptions and interruptions. This makes it possible to reuse the solution in different contexts with minimal changes.

Student motivation and achievement are often low for students from low socioeconomic status households and may decline when children from all walks of life enter middle school. Despite years of studies describing these declines and efforts to improve learning outcomes, the trends continue. Motivation has been studied from several theoretical standpoints, among them, self-efficacy, beliefs, goal orientations, and emotions. This dissertation introduces error orientation: how teachers and students react to and use errors in the classroom. A positive error orientation, one that views errors as opportunities to learn rather than punishments, may help improve students* emotions, self-efficacy, and future goal orientations, while aligning their beliefs in a more adaptive direction, thus reducing maladaptive academic motivation. A professional development design is proposed here to train teachers in using errors to the advantage of the learner by creating a positive error climate in their classrooms.

In web forms, feedback can be provided to users at different points in time. This study investigates these three ways of providing feedback to find which results in the shortest completion time, which results in the lowest number of gaze revisits to input fields, and which type of feedback the users prefer. This was investigated through development of prototypes that were tested with 30 participants in a within-group design after which they were interviewed about their experiences. Providing feedback instantly or after form submission resulted in significantly shorter completion times than providing feedback after users left a field. Providing feedback instantly also resulted in significantly fewer revisits to input fields compared to providing feedback after leaving a field. Through a thematic analysis, users’ experiences were shown to be the most negative when given feedback after form submission, while the most positive experiences occurred when users were given feedback immediately. The results indicate that providing feedback immediately may be an equally good or better alternative to earlier research recommendations to provide feedback after form submission and that revisits to areas of interest may, with further research, be a measurement of optimal scanpath disruption.

Das Softwarewerkzeug FUP Blockbibliothek wurde für Entwurf, Simulation, Echtzeitkodegenerierung und Dokumentation von ereignisgesteuerten Systemen, speziell in Maschinenbau, Mechatronik und Elektrotechnik entwickelt. Es stellt eine Erweiterung zu MATLAB /Simulink dar und bietet eine umfangreiche Entwurfsunterstützung einschließlich Werkzeugen zur Erkennung von Eingabe- und Strukturfehlern. Die graphische Darstellung (Blockikonen) lehnt sich an die VDI / VDE - Richtlinie 3684 "Beschreibung ereignisgesteuerter Bewegungsabläufe mit Funktionsplänen" an.