The purpose of this thesis is to clarify the reasons and consequences of failed implementations and poor adoption of CRM / SFA tools in sales teams, that have been recorded in recent years. Almost 70% of initiatives to introduce new technologies for sales teams have failed in the return on investments. The goal of the thesis is to create requirements for a new CRM / SFA, which will support salesmen and sales teams in a better way. It describes the way the sales team work, it describes business cases and determinates its key activities. Using perceived usefulness, I create a set of system requirements for CRM / SFA tool, which will support salesmen and improve their sales performance.

The basic aim of this work is to improve existing model of rotational inverted pendulum by adding new mechanical features, implement the control algorithm to dsPIC microcontroller and develop related control electronics thus extending the functionality of current model while making it more compact. The work contains derivation of dynamic equations both by means of analytical methods and multi-body formalism of SimMechanics. These are used to design a state controller stabilizing the pendulum in inverse position. In addition, parameters of the system are being estimated experimentally. Swing-up controller is developed to drive the pendulum to unstable position. Various state estimators are added to controller to improve the control process while comparing their overall performance. The last point is devoted to development of superior state-automaton designed to switch between different regulating modes including fail-detection algorithms providing smooth operation of the model.

Software development is an area in which companies not only need to keep up with the latest technology, but they additionally need to continuously increase their productivity to stay competitive in the industry. One company currently facing these challenges is Storytel - one of the strongest players on the Swedish audiobook market - with about a fourth of all employees involved with software development, and a rapidly growing workforce. With the purpose of understanding how the Storytel Tech Department is performing, this thesis maps Storytel’s productivity defined through the Four Key Metrics - Deployment Frequency, Delivery Lead Time, Mean Time To Restore and Change Fail Rate. A classification is made into which performance category (Low, Medium, High, Elite) the Storytel Tech Department belongs to through a deep-dive into the raw system data existing at Storytel, mainly focusing on the case management system Jira. A survey of the Tech Department was conducted, to give insights into the connection between human and technical factors influencing productivity (categorized into Culture, Environment, and Process) and estimated productivity. Along with these data collections, interviews with Storytel employees were performed to gather further knowledge about the Tech Department, and to understand potential bottlenecks and obstacles. All Four Key Metrics could be determined based on raw system data, except the metric Mean Time To Restore which was complemented by survey estimates. The generalized findings of the Four Key Metrics conclude that Storytel can be minimally classified as a ‘medium’ performer. The factors, validated through factor analysis, found to have an impact on the Four Key Metrics were Generative Culture, Efficiency (Automation and Shared Responsibility) and Number of Projects. Lastly, the major bottlenecks found were related to Architecture, Automation, Time Fragmentation and Communication. The thesis contributes with interesting findings from an expanding, middle-sized, healthy company in the audiobook streaming industry - but the results can be beneficial for other software development companies to learn from as well. Performing a similar study with a greater sample size, and additionally enabling comparisons between teams, is suggested for future research.

In the pursuit for ever-increasing compute power, and with Moore's law slowly coming to an end, high-performance computing started to scale-out to larger systems. Alongside the increasing system size, the interconnection network is growing to accommodate and connect tens of thousands of compute nodes. These networks have a large influence on total cost, application performance, energy consumption, and overall system efficiency of the supercomputer. Unfortunately, state-of-the-art routing algorithms, which define the packet paths through the network, do not utilize this important resource efficiently. Topology-aware routing algorithms become increasingly inapplicable, due to irregular topologies, which either are irregular by design, or most often a result of hardware failures. Exchanging faulty network components potentially requires whole system downtime further increasing the cost of the failure. This management approach becomes more and more impractical due to the scale of today's networks and the accompanying steady decrease of the mean time between failures. Alternative methods of operating and maintaining these high-performance interconnects, both in terms of hardware- and software-management, are necessary to mitigate negative effects experienced by scientific applications executed on the supercomputer. However, existing topology-agnostic routing algorithms either suffer from poor load balancing or are not bounded in the number of virtual channels needed to resolve deadlocks in the routing tables. Using the fail-in-place strategy, a well-established method for storage systems to repair only critical component failures, is a feasible solution for current and future HPC interconnects as well as other large-scale installations such as data center networks. Although, an appropriate combination of topology and routing algorithm is required to minimize the throughput degradation for the entire system. This thesis contributes a network simulation toolchain to facilitate the process of finding a suitable combination, either during system design or while it is in operation. On top of this foundation, a key contribution is a novel scheduling-aware routing, which reduces fault-induced throughput degradation while improving overall network utilization. The scheduling-aware routing performs frequent property preserving routing updates to optimize the path balancing for simultaneously running batch jobs. The increased deployment of lossless interconnection networks, in conjunction with fail-in-place modes of operation and topology-agnostic, scheduling-aware routing algorithms, necessitates new solutions to solve the routing-deadlock problem. Therefore, this thesis further advances the state-of-the-art by introducing a novel concept of routing on the channel dependency graph, which allows the design of an universally applicable destination-based routing capable of optimizing the path balancing without exceeding a given number of virtual channels, which are a common hardware limitation. This disruptive innovation enables implicit deadlock-avoidance during path calculation, instead of solving both problems separately as all previous solutions.

Wireless technology has increased in popularity since its invention, being embedded in many devices, such as smartphones, laptops, earphones etcetera. One of those technologies is Bluetooth, which is a short-range technology that is widely used worldwide. While being a popular and important technology, it is not as optimized as it could be, especially the standard Bluetooth 4.2. According to (Bluetooth, 2023)Bluetooth version 5 has four times the range of Bluetooth version 4.2 which is one area of improvement in Bluetooth. While limited Forward Error Correction (FEC)functionality in terms of (15,10) Hamming codes is present in the Bluetooth classic4.2 stack, however, it is not utilized in that version of Bluetooth. This thesis aims to implement a functionality in Bluetooth that uses FEC to increase the range. Before the experiments were conducted, multiple measurements were done in order to check if the hardware, such as the Bluetooth modules, antennas, air sniffer, could provide reliable and valid data. The experiments were conducted by streaming an audio sample of 48 kHz via Bluetooth and increasing the range until a certain percentage of fail rate in data transmission has occurred. FEC was then enabled, and the same experiment was repeated. The results from the experiments show that the range can be increased up to a few meters. Not only that, but the transmission without FEC allows a high level of errors without a connection cut-off. With FEC, the connection does not allow high levels of errors which means that the audio quality would not drop as low as it would have without FEC which means that a certain audio quality is preserved. This also makes the case for the implementation of higher modes of FEC into the Bluetooth stack to potentially increase the range of Bluetooth classic multiple times, but that implementation is beyond the scope of this thesis.

No description available.

The <u>first essay</u> [“Twin Deficits and Free Lunches: Macroeconomic Outcomes In Anticipation of Foreign Aid”] concerns itself with situations in which private agents anticipate a future windfall (free lunch) that will help service the debt resulting from a present fiscal expansion (implemented via a temporary tax cut). Such expectations of a windfall can arise in the context of natural resource discoveries or, more interestingly, due to perceptions by agents in “too important to fail” countries that will be bailed out through higher foreign aid or debt relief. We employ an overlapping generations model featuring credit constraints to study the real effects of such free lunch expectations in a small open economy, drawing contrasts with the standard tax and money finance closure rules. The model is solved analytically and shows that anticipated aid is equivalent to current aid when agents have perfect foresight, so that a temporary tax cut is seen as permanent. Accordingly, agents raise their consumption and indebtedness (at the expense of future generations) by an amount that is an increasing function of their “impatience” (subjective rates of time preference plus probability of death). A worsening of the current account obtains (twin deficits) across a range of plausible closure rules, including those featuring money finance. The introduction of credit constrained households (we study the variant where myopic agents spend their current disposable incomes) does not alter the basic result in the case of full aid finance, but does matter for mixed tax-aid regimes, in more complex settings where agent expectations and donor promises on aid diverge, and when governments face borrowing constraints so that the timing of aid delivery matters. The <u>second essay</u> [“The Role of Domestic Debt in Economic Growth: An Empirical Investigation For Developing Economies”] focuses on the remaining source of government financing, i.e. domestic debt, and the role it can play in mobilizing private savings, facilitating credit intermediation in higher risk settings (i.e. serving a “collateral” function on bank balance sheets), developing financial markets and supporting economic growth in general. To investigate this question empirically, we set up a new domestic debt database covering about 100 developing economies, going back three decades to 1975; explore Granger causality links between domestic debt and key macroeconomic and institutional variables; and estimate the growth impact of domestic debt using panel regressions, allowing for non-linear effects. Domestic debt, as a share of GDP is found to exert a significant positive impact on economic growth, with potential channels including domestic savings mobilization, provision of risk-insurance on banks’ balance sheets; and greater institutional accountability of the state to its citizens. Although this result countervails more established arguments against domestic debt (i.e. that it leads to crowding out and banks to become lazy), there is some evidence that above a ratio of 35 percent of bank deposits, domestic debt does begin to undermine economic growth. The growth payoff also depends on debt quality, with higher payoffs observed for positive interest-rate bearing marketable debt issued to nonbank sectors. The <u>third and final essay</u> [“Why Do Banks in Developing Economies Hold Domestic Government Securities?”] explores demand-side determinants of domestic debt, by focusing on commercial bank holdings of government paper, discriminating carefully between voluntary factors (such as mean-variance portfolio optimization) and statutory ones (cash reserve and capital adequacy requirements). The analysis is made possible by the construction of a dataset on government and private returns (real and nominal) for almost 600 banks from 70 emerging and low-income economies, spanning the (pre-Basel II) period 1995-2005. A battery of structural cross-section regressions indicates that banks’ portfolio decisions are at least as significantly influenced by mean-variance considerations as regulatory factors: the actual portfolio share of government securities (λ) responds intuitively, and sizably, to variations in the moments of the distributions for government and private returns as well as in the minimum-variance portfolio share (λ*). Higher cash reserve requirements tilt portfolios away from government securities toward riskier private lending, while higher capital adequacy requirements work the other way. The association between actual portfolios and the identified determinants is noticeably weaker at lower ends of the λ distribution, suggesting the domination of non-CAPM factors in those contexts.

In der vorliegenden Arbeit werden eine sichere FPGA-Stellwerksplattform und ein Transformationsverfahren entwickelt, mit dem die Schaltungen bestehender Relaisstellwerke in eine FPGA-Logik überführt werden können. Die FPGA-Stellwerksplattform ersetzt die Innenanlage eines Relaisstellwerks. Ihre Schnittstellen entsprechen den bisherigen Schnittstellen am Kabelabschlussgestell und zur Bedien- und Meldeeinrichtung. Damit ist eine einfache Migration bestehender Stellwerke möglich. Das Sicherheitskonzept basiert auf einer zweikanaligen Struktur mit sicherem Vergleicher und zusätzlichen Selbsttests zur schnellen, datenflussunabhängigen Ausfalloffenbarung. Die erreichbare Gefährdungsrate liegt im Bereich von SIL 4 und entspricht damit dem Sicherheitsziel für Stellwerke der Deutschen Bahn. Die Transformation sieht eine Trennung der Stellwerkslogik in Logik- und Leistungsteil vor. Der Logikteil wird auf dem FPGA realisiert. Die im Leistungsteil verbliebenen Kontakte und Überwacherrelais werden durch sichere Stellteile ersetzt. Die logischen Ansteuerbedingungen der Relais werden in Schaltnetze überführt. Die gesteuerten Relais werden durch Instanzen generischer Zustandsmodelle ersetzt. Für jeden verwendeten Relaistyp wurde ein entsprechendes Modell entwickelt, das bei der Transformation als Baustein eingesetzt werden kann. Die generischen Zustandsmodelle berücksichtigen auch die sicherheitsrelevanten konstruktiven Eigenschaften der Relais. So wird bei der Auftrennung einer Schaltung in Logik- und Leistungsteil sichergestellt, dass die in getrennte Schaltungsteile überführten Öffner und Schließer eines Relais nie gleichzeitig geschlossen sein können (Zwangsführung der Kontakte). Dies ist eine Voraussetzung für die Beibehaltung der sicherheitsrelevanten Funktionsbedingungen der Originalschaltung. Das Transformationsverfahren und die implementierten Mechanismen zur Ausfalloffenbarung sind unabhängig von der Anwenderlogik und vom gewählten Schaltkreistyp. Damit kann der generierte VHDL-Code bei Obsoleszenz eines Schaltkreises auch auf andere FPGA-Typen portiert werden. In einer Ressourcenabschätzung wird gezeigt, dass der gewählte Lösungsansatz geeignet ist, die Schaltungen kleinerer Relaisstellwerke vollständig auf einem FPGA zu realisieren. Die Anwendung des vorgestellten Verfahrens wird am Beispiel der Weichengruppe des Stellwerkstyps GS II DR demonstriert. Das Transformationsverfahren ist aber auch für andere Stellwerksbauformen geeignet. Dabei ist es unerheblich, ob diese nach dem tabellarischen Verschlussplanprinzip oder dem Spurplanprinzip arbeiten.

金融犯罪近年來日益受學者與實務界之重視,而我國證券交易 法既以「發展國民經濟、保障投資」為目的,證券市場是否依自然 供需法則自由運作,而不受人為操縱行為破壞價格決定機制,顯得 至為重要。 我國證券交易法明文禁止操縱市場行為,違反者除民事損害賠 償責任外,尚有刑事處罰,且刑度非輕。操縱市場雖屬於相對抽象 之一種禁止類型,但法院實務上已經累積為數不少之判決,然而因 案件內容繁雜、法條構成要件不夠明確......等因素,造成法律見解難 以統一之現象,進而使得辯護工作難度增加。 本文擬從比較法上,參考外國法對操縱市場行為禁止之類型及 方式,檢視我國證券交易法中關於操縱市場之立法過程與構成要 件,並蒐集大量法院判決,整理分析被告提出之各式抗辯,回顧法 院判決中之見解、判斷,期待能更深入問題之核心,裨對實務工作 者能有所助益。 / Financial crimes are increasingly valued by academics and practitioners in recent years. Securities and Exchange Act in Taiwan is securities market operate freely in accordance with the law of natural supply and demand without undermining the mechanism of price determination by human manipulation so important. Securities and Exchange Act in Taiwan expressly prohibited for market manipulation and penalize who breach of regulation. They must bear civil liability for damages and seriously criminal penalties. Although market manipulation may be very abstract sometimes, court practice has accumulated a large number of judgments. However, it’s still a big challenge for attorneys due to the different opinions in practice. The relevant provisions of this order the United States, England and China on different types of legislation about manipulation, in order to find the difference of among the Securities and Exchange Law of Taiwan, as a reference to amend acts of manipulation. By studying cases selected our Court and trying to analyze how the various defenses affect the court decision.

In der vorliegenden Arbeit werden eine sichere FPGA-Stellwerksplattform und ein Transformationsverfahren entwickelt, mit dem die Schaltungen bestehender Relaisstellwerke in eine FPGA-Logik überführt werden können. Die FPGA-Stellwerksplattform ersetzt die Innenanlage eines Relaisstellwerks. Ihre Schnittstellen entsprechen den bisherigen Schnittstellen am Kabelabschlussgestell und zur Bedien- und Meldeeinrichtung. Damit ist eine einfache Migration bestehender Stellwerke möglich. Das Sicherheitskonzept basiert auf einer zweikanaligen Struktur mit sicherem Vergleicher und zusätzlichen Selbsttests zur schnellen, datenflussunabhängigen Ausfalloffenbarung. Die erreichbare Gefährdungsrate liegt im Bereich von SIL 4 und entspricht damit dem Sicherheitsziel für Stellwerke der Deutschen Bahn. Die Transformation sieht eine Trennung der Stellwerkslogik in Logik- und Leistungsteil vor. Der Logikteil wird auf dem FPGA realisiert. Die im Leistungsteil verbliebenen Kontakte und Überwacherrelais werden durch sichere Stellteile ersetzt. Die logischen Ansteuerbedingungen der Relais werden in Schaltnetze überführt. Die gesteuerten Relais werden durch Instanzen generischer Zustandsmodelle ersetzt. Für jeden verwendeten Relaistyp wurde ein entsprechendes Modell entwickelt, das bei der Transformation als Baustein eingesetzt werden kann. Die generischen Zustandsmodelle berücksichtigen auch die sicherheitsrelevanten konstruktiven Eigenschaften der Relais. So wird bei der Auftrennung einer Schaltung in Logik- und Leistungsteil sichergestellt, dass die in getrennte Schaltungsteile überführten Öffner und Schließer eines Relais nie gleichzeitig geschlossen sein können (Zwangsführung der Kontakte). Dies ist eine Voraussetzung für die Beibehaltung der sicherheitsrelevanten Funktionsbedingungen der Originalschaltung. Das Transformationsverfahren und die implementierten Mechanismen zur Ausfalloffenbarung sind unabhängig von der Anwenderlogik und vom gewählten Schaltkreistyp. Damit kann der generierte VHDL-Code bei Obsoleszenz eines Schaltkreises auch auf andere FPGA-Typen portiert werden. In einer Ressourcenabschätzung wird gezeigt, dass der gewählte Lösungsansatz geeignet ist, die Schaltungen kleinerer Relaisstellwerke vollständig auf einem FPGA zu realisieren. Die Anwendung des vorgestellten Verfahrens wird am Beispiel der Weichengruppe des Stellwerkstyps GS II DR demonstriert. Das Transformationsverfahren ist aber auch für andere Stellwerksbauformen geeignet. Dabei ist es unerheblich, ob diese nach dem tabellarischen Verschlussplanprinzip oder dem Spurplanprinzip arbeiten.