Cette thèse fait partie des efforts de recherche pour étudier l’intégration hétérogène sur le substrat souple des nœuds de communicants pour les réseaux de capteurs sans fil dans la bande à 60GHz. Le System in Package (SiP) devrait avoir une consommation d'énergie très faible et être faible coût pour répondre aux exigences des applications telles que la Surveillance de Santé de Structure (Structure Health Monitoring - SHM en anglais) dans le domaine aéronautique par exemple. Chaque nœud est composé des nano-capteurs, des transceivers et des antennes d’émission et de réception. Les nanotechnologies ont permis le développement de nano-capteurs ultra-sensibles à base de nanoparticules. Les transceivers deviennent de plus en plus miniaturisés et donc permettre la possibilité de les reporter sur le substrat flexible. Les antennes peuvent être intégrés sur le substrat flexible avec les nano-capteurs développés et émetteurs miniaturisés, ce qui est l'approche très innovante. Dans cette thèse, nous présenterons les procédés technologiques adaptés pour réaliser les différents circuits passifs (résonateurs, antennes, rectennas, etc…) sur le substrat souple en utilisant la photolithographie conventionnelle. La technique de la puce retournée a été choisie pour l’intégration des transceivers à 60 GHz, la formation des bosses d’interconnexion en or directement sur le substrat souple par les dépôts électrolytiques est présentée ici pour la première fois. La concordance entre les mesures expérimentales et les simulations numériques démontre la fiabilité et la reproductibilité des procédés choisis. De plus, pour une application à volume élevé comme les réseaux de capteurs sans fil, le coût de fabrication par nœud peut être considérablement réduit, et devient comparable avec l’impression jet d'encre qui est un procédé à faible coût. / This thesis is part of research effort to develop a 3D heterogeneous integration of wireless sensor node on flexible substrate for the unlicensed 60GHz band. The System in Package (SiP) should have a very low power consumption and very low cost to meet the requirements of applications like Wireless Sensor Networks (WSNs) for Structure Health Monitoring (SHM). Using a flexible substrate for wireless sensor node integration can offer the advantage of being localized in areas with access difficulty especially in non-planar area. Each node is composed of nano-sensors, transceivers and TX/RX antenna. Nanotechnologies made it possible the development of ultra-sensitive nano-sensors based on nanoparticles deposition. Transceivers become more and more miniaturized and hence enable the possibility of postpone them onto flexible substrate. The antennas can be integrated on the flexible substrate along with the developed nano-sensors and miniaturized transceivers, which is the very innovative approach. In this work, we propose customized photolithography processes to manufacture the passive element circuits (resonators, antennas, rectennas, etc…) on flexible substrate. The technique of flip-chip was used for the integration of 60 GHz transceivers, a novel technique to form Au interconnection bump directly onto the flexible substrate by using electrodeposition process is also presented here for the first time. The concordance between the simulations and the measurements is observed, which proves the reliability and reproducibility of such process technique. Furthermore, for a high-volume application like the node deployment of WSNs, wafer cost reductions can significantly lower the total cost per node and became comparable to a low-cost inkjet printing process.

A common method of cancer treatment is radiation therapy. In radiation therapy, a treatment planning system is made to specify the dose of X-rays needed to eradicate the tumor. To assure the right amount of X-ray dosage a quality assurance is using a phantom containing radiation sensors. The sensors are made of semiconductor materials with heavy metal-based contacts. Irradiating heavy elements with a high-intensity beam such as Xrays causes secondary scattering of electrons, resulting in an additional photocurrent which may distort the signal used in the quality analysis. By exchanging the heavy-metal contact material to a lighter version such as a carbon-based material, preventing secondary scattering, the error obtained from the quality analysis can be minimized.In this thesis, characterization of contacts between radiation diodes and a copper substrate by flip-chip bonding with reduced graphene oxide-based anisotropic conducting adhesive is made. The parameters of the connections are characterized with respect to electrical, thermal and mechanical properties.Analysis of the novel contact material is done by comparing different types of graphene-based anisotropic fillers with a commercial metal-based filler. Results obtained indicate that it is possible to exchange the metal-based fillers in an anisotropic conducting adhesive with reduced graphene oxide coated polymer spheres as a contacting material for radiation sensing technology. / En vanlig metod som används för att behandla cancer är strålningsterapi. I strålningsterapi görs ett behandlingsplaneringssystem för att specificera en exakt dos av röntgenstrålning som krävs för att slå ut en tumör. För att säkerställa att man ger rätt dos av röntgenstrålning utförs en kvalitetssäkring genom att använda en fantom innehållande strålningssensorer. Sensorerna är gjorda av halvledarmaterial men har oftast anslutningar gjorda av tunga metalliska material. När man bestrålar metaller med hög intensitet, exempelvis röntgenstrålning, emitteras en sekundär spridning av elektroner i form av en fotoström som kan störa signalen i kvalitetsäkrningen. Genom att byta ut metallen som används i anslutningarna till ett kontaktmaterial med lägre atomnummer som exempelvis kolbaserade material, förhindras den sekundära spridningen av elektroner, som troligtvis minskar felet som uppstår vid kvalitetssäkringen.I detta arbete har en kartläggning av kontakter mellan stålningsdioder och ett kopparsubstrat, genom en flip-chip-bindning process med ett ledande adhesiv baserat på reducerad grafenoxid gjorts. Kontaktparametrarna som kartlagts är baserade på termiska, elektriska och mekaniska egenskaper.Kartläggningen av kontakterna har i mestadels gjort genom att jämföra olika typer av grafen baserade partiklar ett kommersiellt metalbaserat material gjort för flip-chipbindning. Resultaten från arbetet indikerar att det är möjligt att byta ut det metallbaserade partiklarna i ett anisotropt ledande adhesiv med reducerade grafenoxid-belagda polymersfärer som ett ledande material för strålningsapplikationer.

Conventional tin-lead solder alloys have been widely used in electronics interconnection owing to their properties such as low melting temperature, good ductility and excellent wettability on copper and other substrates. However, due to the worldwide legislation addressing the concern over the toxicity of lead, the usage of lead-containing solders has been phased out, thus stimulating substantial efforts on lead-free alternatives, amongst which eutectic Sn-Ag and Sn-Cu, and particularly Sn-Ag-Cu alloys, are promising candidates as recommended by international parties. To meet the increasing demands of advanced electronic products, high levels of integration of electronic devices are being developed and employed, which is leading to a reduction in package size, but with more and more input/output connections. Flip chip technology is therefore seen as a promising technique for chip interconnection compared with wire bonding, enabling higher density, better heat dissipation and a smaller footprint. This thesis is intended to investigate lead-free (eutectic Sn-Ag, Sn-Cu and Sn-Ag-Cu) wafer level solder bumping through electrodeposition for flip chip interconnection, as well as electroplating lead-free solderable finishes on electronic components. The existing knowledge gap in the electrochemical processes as well as the fundamental understanding of the resultant tin-based lead-free alloys electrodeposits are also addressed. For the electrodeposition of the Sn-Cu solder alloys, a methanesulphonate based electrolyte was established, from which near-eutectic Sn-Cu alloys were achieved over a relatively wide process window of current density. The effects of methanesulphonic acid, thiourea and OPPE (iso-octyl phenoxy polyethoxy ethanol) as additives were investigated respectively by cathodic potentiodynamic polarisation curves, which illustrated the resultant electrochemical changes to the electrolyte. Phase identification by X-ray diffraction showed the electrodeposits had a biphasic structure (β-Sn and Cu6Sn5). Microstructures of the Sn-Cu electrodeposits were comprehensively characterised, which revealed a compact and crystalline surface morphology under the effects of additives, with cross-sectional observations showing a uniform distribution of Cu6Sn5 particles predominantly along β-Sn grain boundaries. The electrodeposition of Sn-Ag solder alloys was explored in another pyrophosphate based system, which was further extended to the application for Sn-Ag-Cu solder alloys. Cathodic potentiodynamic polarisation demonstrated the deposition of noble metals, Ag or Ag-Cu, commenced before the deposition potential of tin was reached. The co-deposition of Sn-Ag or Sn-Ag-Cu alloy was achieved with the noble metals electrodepositing at their limiting current densities. The synergetic effects of polyethylene glycol (PEG) 600 and formaldehyde, dependent on reaching the cathodic potential required, helped to achieve a bright surface, which consisted of fine tin grains (~200 nm) and uniformly distributed Ag3Sn particles for Sn-Ag alloys and Ag3Sn and Cu6Sn5 for Sn-Ag-Cu alloys, as characterised by microstructural observations. Near-eutectic Sn-Ag and Sn-Ag-Cu alloys were realised as confirmed by compositional analysis and thermal measurements. Near-eutectic lead-free solder bumps of 25 μm in diameter and 50 μm in pitch, consisting of Sn-Ag, Sn-Cu or Sn-Ag-Cu solder alloys depending on the process and electrolyte employed, were demonstrated on wafers through the electrolytic systems developed. Lead-free solder bumps were further characterised by material analytical techniques to justify the feasibility of the processes developed for lead-free wafer level solder bumping.

Pour l'intégration 3D, le procédé d'interconnexion par flip chip est très utilisé. Le principal inconvénient de ce procédé est l'utilisation de traitement complémentaire des puces avant leur assemblage. Pour résoudre ce problème, a été développé, un nouveau procédé d'interconnexion par micro-insertion de micro-cylindres de nickel appelés micro-inserts directement dans les zones de connexion des puces en aluminium. Cependant, il existe trop d'interrogations sur la fiabilité des interconnexions réalisées. Afin de répondre à certaines de ces interrogations ce travail de thèse présente une étude localisée de l'insertion d'un micro-insert de nickel isolé dans un film d'aluminium. L'étude de l'insertion a été effectuée grâce à la modification de la technique de nanoindentation. Ceci a permis de mettre en évidence les modes de déformation des matériaux en contact pour différents diamètres et différentes forces maximales et de mesurer en parallèle la résistance de contact électrique.

The generalized theory of thermoelasticity was employed to characterize the coupled thermal and mechanical wave propagation in high performance microelectronic packages. Application of a Gaussian heat source of spectral profile similar to high performance devices was shown to induce rapid thermal and mechanical transient phenomena. The stresses and temporal gradient of stresses (power density) induced by the thermal and mechanical disturbances were analyzed using the Gabor Wavelet Transform (GWT). The arrival time of frequency components and their magnitude was studied at various locations in the package. Comparison of the results from the classical thermoelasticity theory and generalized theory was also conducted. It was found that the two theories predict vastly different results in the vicinity of the heat source but that the differences diminish within a larger time window. Results from both theories indicate that the rapid thermal-mechanical waves cause high frequency, broadband stress waves to propagate through the package for a very short period of time. The power density associated with these stress waves was found to be of significant magnitude indicating that even though the effect, titled short time scale effect, is short lived, it could have significant impact on package reliability. The high frequency and high power density associated with the stress waves indicate that the probability of sub-micron cracking and/or delamination due to short time scale effect is high. The findings demonstrate that in processes involving rapid thermal transients, there is a non-negligible transient phenomenon worthy of further investigation.

Flip-chip underfilling is a technology by which silica-filled epoxy resin is used to fill the micro-cavity between a silicon chip and a substrate, by dispensing the liquid encapsulant at elevated temperatures along the periphery of one or two sides of the chip and then allowing capillary action to draw the material into the gap. Since the chip, underfill material, and substrate solidify together as one unit, thermal stresses on solder joints during the temperature cycling (which are caused by a mismatch in the coefficients of thermal expansion between the silicon chip and the organic substrate) can be redistributed and transferred away from the fragile bump zone to a more strain-tolerant region. Modeling of the flow behaviour of a fluid in the underfill process is the key to this technology. One of the most important drawbacks in the existing models is inadequate treatment of non-Newtonian fluids in the underfill process in the development of both analytical models and numerical models. Another important drawback is the neglect of the presence of solder bumps in the existing analytical models. This thesis describes a study in which a proper viscosity constitutive equation, power-law model, is employed for describing the non-Newtonian fluid behaviour in flip-chip package. Based on this constitutive equation, two analytical models with closed-form solutions for predicting the fluid filling time and fluid flow front position with respect to time were derived. One model is for a setting with two parallel plates as an approximate to flip-chip package, while the other model is for a setting with two parallel plates within which an array of solder bumps are present. Furthermore, a numerical model using a general-purpose finite element package ANSYS was developed to predict the fluid flow map in two dimensions. The superiority of these models to the existing models (primarily those developed at Cornell University in 1997) is confirmed based on the results of the experiments conducted in this study. This thesis also presents a finding of the notion of critical clearance in the design of a flip-chip package through a careful simulation study using the models developed. The flip-chip package design should make the clearance between solder bumps larger than the critical clearance.

Flip-chip underfilling is a technology by which silica-filled epoxy resin is used to fill the micro-cavity between a silicon chip and a substrate, by dispensing the liquid encapsulant at elevated temperatures along the periphery of one or two sides of the chip and then allowing capillary action to draw the material into the gap. Since the chip, underfill material, and substrate solidify together as one unit, thermal stresses on solder joints during the temperature cycling (which are caused by a mismatch in the coefficients of thermal expansion between the silicon chip and the organic substrate) can be redistributed and transferred away from the fragile bump zone to a more strain-tolerant region. Modeling of the flow behaviour of a fluid in the underfill process is the key to this technology. One of the most important drawbacks in the existing models is inadequate treatment of non-Newtonian fluids in the underfill process in the development of both analytical models and numerical models. Another important drawback is the neglect of the presence of solder bumps in the existing analytical models. This thesis describes a study in which a proper viscosity constitutive equation, power-law model, is employed for describing the non-Newtonian fluid behaviour in flip-chip package. Based on this constitutive equation, two analytical models with closed-form solutions for predicting the fluid filling time and fluid flow front position with respect to time were derived. One model is for a setting with two parallel plates as an approximate to flip-chip package, while the other model is for a setting with two parallel plates within which an array of solder bumps are present. Furthermore, a numerical model using a general-purpose finite element package ANSYS was developed to predict the fluid flow map in two dimensions. The superiority of these models to the existing models (primarily those developed at Cornell University in 1997) is confirmed based on the results of the experiments conducted in this study. This thesis also presents a finding of the notion of critical clearance in the design of a flip-chip package through a careful simulation study using the models developed. The flip-chip package design should make the clearance between solder bumps larger than the critical clearance.

The generalized theory of thermoelasticity was employed to characterize the coupled thermal and mechanical wave propagation in high performance microelectronic packages. Application of a Gaussian heat source of spectral profile similar to high performance devices was shown to induce rapid thermal and mechanical transient phenomena. The stresses and temporal gradient of stresses (power density) induced by the thermal and mechanical disturbances were analyzed using the Gabor Wavelet Transform (GWT). The arrival time of frequency components and their magnitude was studied at various locations in the package. Comparison of the results from the classical thermoelasticity theory and generalized theory was also conducted. It was found that the two theories predict vastly different results in the vicinity of the heat source but that the differences diminish within a larger time window. Results from both theories indicate that the rapid thermal-mechanical waves cause high frequency, broadband stress waves to propagate through the package for a very short period of time. The power density associated with these stress waves was found to be of significant magnitude indicating that even though the effect, titled short time scale effect, is short lived, it could have significant impact on package reliability. The high frequency and high power density associated with the stress waves indicate that the probability of sub-micron cracking and/or delamination due to short time scale effect is high. The findings demonstrate that in processes involving rapid thermal transients, there is a non-negligible transient phenomenon worthy of further investigation.

This dissertation aims to evaluate the package effects on the performance of radio frequency integrated circuits (RFICs) for wireless applications. A model-based study is presented to compare the effects between flip-chip and wire-bond packages on a front-end cascode low-noise amplifier (LNA) in a 2.45 GHz CMOS wireless local area network (WLAN) receiver. To construct the package electrical models, specific modeling dies are designed to help extract the equivalent-circuit elements from measured S-parameters for chip-package interconnects. Furthermore, the ground-proximity effect on on-chip spiral inductors in a flip-chip package is first observed and presented in this modeling study. Excellent agreement between modeling and measurement is obtained by up to 20 GHz for a 64-pin flip-chip ball grid array (FC-BGA) package and a 64-pin wire-bond quad flat nonlead (WB-QFN) package. For practical applications, the established package models are used to predict the degradation of the figure of merit for the cascode LNA under packaged condition. Chip-package co-simulations can achieve good agreement with measurements, and thus can persuasively account for the complete effects caused by the two different packages on the cascode LNA. To simultaneously consider the package and board interconnect effects on RFICs, this dissertation also designs and implements a 1.95 GHz upconverter for the wideband code-division multiple-access (W-CDMA) transmitter. Specific ground wire-bonding and board connection are designed to minimize the linearity degradation due to package and board interconnects. Nonlinear analysis technique is also used to evaluate the nonlinear distortion of the upconverter in the chip-package-board co-design phase. The final measurement results have successfully verified the co-design predictions and simulations for this upconverter.

No description available.