Chip-package interaction (CPI) has become a critical reliability issue for flip-chip packaging of Cu/low-k chip with organic substrate. The thermo-mechanical deformation and stress develop inside the package during assembly and subsequent reliability tests due to the mismatch of the coefficients of thermal expansion (CTEs) between the chip and the substrate. The thermal residual stress causes many mechanical reliability issues in the solder joints and the underfill layer between die and substrate, such as solder fatigue failure and underfill delamination. Moreover, the thermo-mechanical deformation of the package can be directly coupled into the Cu/low-k interconnect, inducing large local stresses to drive interfacial crack formation and propagation. The thermo-mechanical reliability risk is further aggravated with the implementation of ultra low-k dielectric for better electrical performance and the mandatory change from Pb-containing solders to Pb-free solders for environmental safety. These CPI-induced reliability issues in flip-chip packaging of Cu/low-k chips are investigated in this dissertation at both chip level and package level using high-resolution Moiré interferometry and Finite Element Analysis (FEA). Firstly, the thermo-mechanical deformation in flip-chip packages is analyzed using high-resolution Moiré interferometry. The effect of underfill properties on package warpage is studied and followed by a strategy study of proper underfill selection to improve solder fatigue life time and reduce the risk of interfacial delamination in underfill and low-k interconnects under CPI. The chip-package interaction is found to maximize at the die attach step during assembly and becomes most detrimental to low-k chip reliability because of the high thermal load generated by the solder reflow process before underfilling. A three-dimensional (3D) multilevel sub-modeling method combined with modified virtual crack closure (MVCC) technique is employed to investigate the CPI-induced interfacial delamination in Cu/low-k interconnects. It is first focused on the effects of dielectrics and solder materials on low-k interconnect reliability and then extended to the scaling effect where the reduction of the interconnect dimension is accompanied with an increased number of metal levels and the implementation of ultralow-k porous dielectrics. Recent studies on CPI-induced crack propagation in the low-k interconnect and the use of crack-stop structures to improve the chip reliability are also discussed. Finally, 3D integration (3DI) with through silicon vias (TSV) has been proposed as the latest solution to increase the device density without down-scaling. The thermo-mechanical reliability issues facing 3DI are analyzed. Three failure modes are proposed and studied. Design optimization of 3D interconnects to reduce the thermal residual stress and the risks of fracture and delamination are discussed. / text

Electromigration (EM) and thermomigration (TM) reliability of Pb-free solder joints are emerging as critical concerns in advanced packages. In this study, EM and TM phenomena in Sn-2.5Ag solder joints with thick Cu or thin Ni under-bump metallurgy (UBM) were investigated. A series of EM tests were performed to obtain activation energy (Q) and current density exponent (n), and to understand failure mechanisms. Joule heating was also taken into account. Q and n values were determined as follows: for Cu UBM solders, Q = 1.0 eV and n = 1.5; for Ni UBM solders, Q = 0.9 and n = 2.2. Important factors limiting EM reliability of Pb-free solder joints were found to be UBM dissolution with extensive intermetallic compound (IMC) growth and current crowding. IMC growth without current stressing was found to follow the parabolic growth law whereas linear growth law was observed for Cu₆Sn₅ and Ni₃Sn₄ under high current stressing. For Cu UBM solders, the apparent activation energy for IMC growth was consistent with the activation energy for EM, which supports that EM failure was closely related to IMC growth. In contrast, for Ni UBM solders the apparent activation energy was higher than the EM activation energy. It was suggested that the EM failure in the Ni UBM solders could be associated with more than one mass transport mechanism. The current crowding effect was analyzed with different thicknesses of Ni UBM. It was found that the maximum current density in solder could represent the current density term in Black's equation better than the average current density. FEM studies demonstrated that current crowding was mainly controlled by UBM thickness, metal trace design, and passivation opening diameter. A large temperature gradient of the order of 10³ °C/cm was generated across the sample to induce noticeable TM and to compare its effect against that of EM. TM-induced voiding was observed in Ni UBM solders while UBM dissolution with IMC formation occurred in Cu UBM solders. However, the relative effect of TM was found to be several times smaller than that of EM even at this large temperature gradient. / text

Este trabalho, desenvolvido junto ao Grupo de Novos Materiais e Dispositivos (GNMD) pertencente ao Laboratório de Microeletrônica (LME) da Universidade de São Paulo, apresenta a modelagem de um defasador passivo miniaturizado com baixas perdas para aplicações em ondas milimétricas (mmW-milimeter waves). Este defasador é baseado em um conceito inovador utilizando sistemas micro-eletromecânicos (MEMS) distribuídos e linhas de transmissão coplanares de ondas lentas. Este conceito é proposto no projeto Jovem Pesquisador FAPESP (Processo no. 2011/18167-3), ao qual este projeto está vinculado. A defasagem neste tipo de dispositivo é conseguida pela liberação das fitas da camada de blindagem de uma linha de transmissão tipo S-CPW (Shielded-Coplanar Waveguide). As fitas liberadas podem ser movimentadas eletrostaticamente, o que praticamente não consome energia. Este projeto pretende projetar um defasador para fabricação com a tecnologia do Laboratório de Microeletrônica da Escola Politécnica da Universidade de São Paulo. Adicionalmente, este trabalho apresenta resultados experimentais de um processo de fabricação IN-HOUSE baseado na metodologia de integração por flip-chip. A tecnologia de integração implementada é baseada na soldagem de um chip sobre um substrato, no qual são construídos uma nova geração de pilares de cobre finos, cujo espaçamento entre pilares é menor que 100 ?m. Essa redução nas dimensões pode ser usada com a nova geração de dispositivos de comunicações na faixa das mmW. Em termos de fabricação, foram obtidos pilares de cobre altamente miniaturizados com uma altura significativa e uniforme que permite a integração com o chip. Além do mais, os resultados obtidos representam avanços significativos no processo de fabricação que será usado como tecnologia de integração híbrida em um interposer baseado em substrato de alumina nanoporosa (MnM-Metallic Nanowire Membrane). Esse interposer desempenha um papel indispensável no GNMD, já que atualmente estão sendo estudadas suas propriedades elétricas e já foram construídos dispositivos sobre o substrato com resultados promissores. / This work, performed at the New Materials and Devices Group (GNMD) of the Microelectronics Laboratory of the Polytechnic School of the University of São Paulo, presents the modeling of a miniaturized passive phase shifter with low losses for applications in millimeter waves. It is based on an innovated concept, which uses distributed MEMS phase shifters and slow-wave coplanar wave guides. Such concept is proposed under the FAPESP Youth Researcher project (Process number 2011/18167-3). The phase shifter on this kind of device is achieved by releasing the shielding layer of the Shielded-Coplanar Waveguide. The released ribbons are electrostatically displaced, which does not consume energy. The aim of this project is to design a phase shifter for fabrication with the technology available at the Microelectronics Laboratory. Additionally, this work presents experimental results of a flip-chip fabrication process. This technology is based on next generation of fine pitch copper pillar bumping, with pillar pitch of less than 100 ?m that support next generation of communication devices at the millimeter wave frequency range. From the fabrication point-of-view, highly miniaturized copper pillars with appropriate thicknesses were obtained. Furthermore, the results obtained represent a significant advance in the fabrication process that will be used as a hybrid integration technology on an interposer based on a nanoporous alumina substrate (MnM-Metallic Nanowire Membrane).

No-flow underfill materials that cure during the solder reflow process is a relatively new technology. Although there are several advantages in terms of cost, time and processing ease, there are several reliability challenges associated with no-flow underfills. When micron-sized filler particles are introduced in no-flow underfills to enhance the solder bump reliability, such filler particles could prevent the solder bumps making reliable electrical contacts with the substrate pads during solder reflow, and therefore, the assembly yield would be adversely affected. The use of nano-sized filler particles can potentially improve assembly yield while offering the advantages associated with filled underfill materials. The objective of this thesis is to study the thermo-mechanical reliability of nano-filled epoxy underfills (NFU) through experiments and theoretical modeling. In this work, the thermo-mechanical properties of NFUs with 20-nm filler particles have been measured. An innovative residual stress test method has been developed to measure the interfacial fracture toughness. Using the developed residual stress method and the single-leg bending test, the mode-mixity-dependent fracture toughness for NFU-SiN interface has been determined. In addition to such monotonic interfacial fracture characterization, the interface crack propagation under thermo-mechanical fatigue loading has been experimentally characterized, and a model for fatigue interface crack propagation has been developed. A test vehicle comprising of several flip chips was assembled using the NFU material and the reliability of the flip-chip assemblies was assessed under thermal shock cycles between -40oC and 125oC. The NFU-SiN interfacial delamination propagation and the solder bump reliability were monitored. In parallel, numerical models were developed to study the interfacial delamination propagation in the flip chip assembly using conventional interfacial fracture mechanics as well as cohesive zone modeling. Predictions for interfacial delamination propagation using the two approaches have been compared. Based on the theoretical models and the experimental data, guidelines for design of NFUs against interfacial delamination have been developed.

L'évolution de la microélectronique suit plusieurs axes notamment la miniaturisation des éléments actifs (réduction de taille des transistors), et l'augmentation de la densité d'interconnexion qui se traduisent par la loi de Gordon Moore qui prédit que la densité d'intégration sur silicium doublerait tous les deux ans. Ces évolutions ont pour conséquence la réduction des prix et du poids des composants. L'hybridation ou flip chip est une technologie qui s'inscrit dans cette évolution, elle consiste en l'assemblage de matériaux hétérogènes. Dans cette étude il s'agit d'un circuit de lecture Silicium et d'un circuit de détection InP ou GaAs assemblés par l'intermédiaire d'une matrice de billes d'indium. La connexion flip chip est basée sur l'utilisation d'une jonction par plots métalliques de faibles dimensions qui permet de diminuer les pertes électriques (faible inductance et faible bruit), une meilleure dissipation thermique, une bonne tenue mécanique. Enfin elle favorise la miniaturisation avec l'augmentation de la compacité et de la densité d'interconnexion.Les travaux de thèse se concentrent sur deux axes principaux. Le premier concerne l'hybridation par brasure avec la technologie des billes d'indium par refusion, et le second concerne l'hybridation par pression à température ambiante (nano-scratch) par l'intermédiaire des nanostructures (Nano-fils d'or, Nano-fils ZnO). Ces travaux ont permis la réalisation d'un détecteur InGaAs avec extension visible de format TV 640*512 pixels au pas de 15 µm. Ces travaux ont également permis la validation mécanique de l'assemblage d'un composant de format double TV 1280*1024 pixels au pas de 10 µm par cette même méthode de reflow. Pour l'axe hybridation à froid, nos travaux ont permis la validation d'une méthode de croissance de nano-fils ZnO par une voix hydrothermique à basse température (<90°C).

La miniaturització de la industria microelectrònica és un fet del tot inqüestionables i la tecnologia CMOS no n'és una excepció. En conseqüència la comunitat científica s'ha plantejat dos grans reptes: En primer lloc portar la tecnologia CMOS el més lluny possible ('Beyond CMOS') tot desenvolupant sistemes d'altes prestacions com microprocessadors, micro - nanosistemes o bé sistemes de píxels. I en segon lloc encetar una nova generació electrònica basada en tecnologies totalment diferents dins l'àmbit de les Nanotecnologies. Tots aquests avanços exigeixen una recerca i innovació constant en la resta d'àrees complementaries com són les d'encapsulat. L'encapsulat ha de satisfer bàsicament tres funcions: Interfície elèctrica del sistema amb l'exterior, Proporcionar un suport mecànic al sistema i Proporcionar un camí de dissipació de calor. Per tant, si tenim en compte que la majoria d'aquests dispositius d'altes prestacions demanden un alt nombre d'entrades i sortides, els mòduls multixip (MCMs) i la tecnologia flip chip es presenten com una solució molt interessant per aquests tipus de dispositiu. L'objectiu d'aquesta tesi és la de desenvolupar una tecnologia de mòduls multixip basada en interconnexions flip chip per a la integració de detectors de píxels híbrids, que inclou: 1) El desenvolupament d'una tecnologia de bumping basada en bumps de soldadura Sn/Ag eutèctics dipositats per electrodeposició amb un pitch de 50µm, i 2) El desenvolupament d'una tecnologia de vies d'or en silici que permet interconnectar i apilar xips verticalment (3D packaging) amb un pitch de 100µm. Finalment aquesta alta capacitat d'interconnexió dels encapsulats flip chip ha permès que sistemes de píxels tradicionalment monolítics puguin evolucionar cap a sistemes híbrids més compactes i complexes, i que en aquesta tesi s'ha vist reflectit transferint la tecnologia desenvolupada al camp de la física d'altes energies, en concret implantant el sistema de bump bonding d'un mamògraf digital. Addicionalment s'ha implantat també un dispositiu detector híbrid modular per a la reconstrucció d'imatges 3D en temps real, que ha donat lloc a una patent. / The scaling down of microelectronic's industry is a fact completely unquestionable and the technology CMOS is not an exception. Consequently, the scientific community has considered two great challenges: In first place to bring the technology CMOS the most far away possible ('Beyond CMOS') while developing advanced systems such as microprocessors, micro - nanosystems or pixel systems. On the other hand to begin a new electronic generation based on technologies totally different inside the Nanotechnologies area.All these advances require a research and constant innovation in the rest of complementary areas such as Packaging. Any packaging system has to satisfy three functions in a basic way: Electrical interface of the system with the exterior, to provide a mechanical support to the system and to provide a way of heat dissipation. In order to satisfy the requirements of advanced systems with high number of I/Os, the multichip modules (MCMs) and the flip chip technology are presented as a very interesting solution.The goal of this thesis consist of developing a multichip module technology based on flip chip interconnections for the integration of hybrid pixel detectors, which includes: 1) The development of a bumping technology based on electrodeposited Sn/Ag eutectic solder bumps with a pitch of 50µm, and 2) The development of a technology of gold vias in silicon that allows to interconnect and to stack chips vertically (3D packaging) with a pitch of 100µm.Finally this high capacity of flip chip interconnection has allowed that traditional monolithic pixel systems can evolve towards hybrid systems more compact and complex, and that in this thesis has been reflected transferring the technology developed in the field of the high energies physics, implanting the bump bonding system of a digital mammography system in particular. Additionally also a modular hybrid detecting device (CMOS Image Sensor) has been implanted for the reconstruction of 3D images in real time, which has caused a patent.

Thesis (Ph. D.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, Thomas J. Watson School of Engineering and Applied Science, 2008. / Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2009. / Includes bibliographical references.

Este trabalho, desenvolvido junto ao Grupo de Novos Materiais e Dispositivos (GNMD) pertencente ao Laboratório de Microeletrônica (LME) da Universidade de São Paulo, apresenta a modelagem de um defasador passivo miniaturizado com baixas perdas para aplicações em ondas milimétricas (mmW-milimeter waves). Este defasador é baseado em um conceito inovador utilizando sistemas micro-eletromecânicos (MEMS) distribuídos e linhas de transmissão coplanares de ondas lentas. Este conceito é proposto no projeto Jovem Pesquisador FAPESP (Processo no. 2011/18167-3), ao qual este projeto está vinculado. A defasagem neste tipo de dispositivo é conseguida pela liberação das fitas da camada de blindagem de uma linha de transmissão tipo S-CPW (Shielded-Coplanar Waveguide). As fitas liberadas podem ser movimentadas eletrostaticamente, o que praticamente não consome energia. Este projeto pretende projetar um defasador para fabricação com a tecnologia do Laboratório de Microeletrônica da Escola Politécnica da Universidade de São Paulo. Adicionalmente, este trabalho apresenta resultados experimentais de um processo de fabricação IN-HOUSE baseado na metodologia de integração por flip-chip. A tecnologia de integração implementada é baseada na soldagem de um chip sobre um substrato, no qual são construídos uma nova geração de pilares de cobre finos, cujo espaçamento entre pilares é menor que 100 ?m. Essa redução nas dimensões pode ser usada com a nova geração de dispositivos de comunicações na faixa das mmW. Em termos de fabricação, foram obtidos pilares de cobre altamente miniaturizados com uma altura significativa e uniforme que permite a integração com o chip. Além do mais, os resultados obtidos representam avanços significativos no processo de fabricação que será usado como tecnologia de integração híbrida em um interposer baseado em substrato de alumina nanoporosa (MnM-Metallic Nanowire Membrane). Esse interposer desempenha um papel indispensável no GNMD, já que atualmente estão sendo estudadas suas propriedades elétricas e já foram construídos dispositivos sobre o substrato com resultados promissores. / This work, performed at the New Materials and Devices Group (GNMD) of the Microelectronics Laboratory of the Polytechnic School of the University of São Paulo, presents the modeling of a miniaturized passive phase shifter with low losses for applications in millimeter waves. It is based on an innovated concept, which uses distributed MEMS phase shifters and slow-wave coplanar wave guides. Such concept is proposed under the FAPESP Youth Researcher project (Process number 2011/18167-3). The phase shifter on this kind of device is achieved by releasing the shielding layer of the Shielded-Coplanar Waveguide. The released ribbons are electrostatically displaced, which does not consume energy. The aim of this project is to design a phase shifter for fabrication with the technology available at the Microelectronics Laboratory. Additionally, this work presents experimental results of a flip-chip fabrication process. This technology is based on next generation of fine pitch copper pillar bumping, with pillar pitch of less than 100 ?m that support next generation of communication devices at the millimeter wave frequency range. From the fabrication point-of-view, highly miniaturized copper pillars with appropriate thicknesses were obtained. Furthermore, the results obtained represent a significant advance in the fabrication process that will be used as a hybrid integration technology on an interposer based on a nanoporous alumina substrate (MnM-Metallic Nanowire Membrane).

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