Thesis (Ph. D.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2007. / Includes bibliographical references.

No description available.

This thesis presents the low cost process for UBM formation on aluminum pads of single die/dice for Flip Chip applications. The UBM (Under Bump Metallurgy) is required in solder bump structure to provide adhesion/diffusion barrier layer, solder wettable layer, and oxidation barrier layer between the bonding pads of the die and the bumps. Typically, UBM is deposited on the whole wafers by sputtering, evaporation, or electroless plating. These deposition techniques are not practical for UBM formation on single die/dice, thus preventing Flip Chip technology to be applied in applications where the whole wafers are not available. The process presented in this thesis has been developed to overcome this problem. The developed UBM formation process allows the UBM layer to be deposited on a single die, thus eliminating the requirement to have the whole wafer in the deposition process. With the combination of the UBM formation process developed in this work and a suitable bump formation technique, solder bumping on a single die can be achieved, thus making Flip Chip technology available for use in low volume applications and prototyping stages. The developed UBM formation process consists of two major steps; temporary die attach process and UBM deposition process. The first process is developed using thermoplastic adhesive film. The second process is developed using electroless nickel plating, followed by gold immersion. It has been demonstrated in this thesis that the developed process can be used to form the UBM layer on the die successfully regardless of the die size and the complexity of the die pattern, and that this process does not damage nor affect electrically the sensitive die. / Master of Science

Flip chip interconnections have superior performance for microwave applications compared to wire bond interconnections because of their reduced parasitics, more compact architecture, and flexibility in laying out flip chip bond pads. Reduction in interconnect parasitics enables these interconnects to support broadband signals, therefore increasing the bandwidth capabilities of flip chip-assembled systems. Traditional flip chip designs provide mechanical and electrical connections from a top chip to a carrier substrate with rigid solder joints. For heterogeneous assemblies, flip chip connections suffer from thermo-mechanical failures caused by coefficient of thermal expansion mismatches. As an alternative, flexible flip chip interconnections incorporating a metal, which is liquid at room temperature, mitigates the possibility of such thermo-mechanical failures. Additionally, liquid metal, flip chip interconnections allow for room temperature assembly, simplifying assembly and rework processes. This dissertation focuses on the design and characterization of liquid metal interconnections, specifically using Galinstan, an alloy of gallium indium and tin, for the heterogeneous assembly of active monolithic microwave integrated circuits (MMICs) onto a CTE mismatched substrate. Carrier substrates designed for liquid metal transitions were fabricated on high resistivity Si and on three dimensional copper structures. The three dimensional copper structures were fabricated in the PolyStrata™ process. Individual MMIC chips were post-processed to mate with carrier substrates in a liquid metal, flip chip configuration. S-parameter measurements of prototype MMIC assemblies with liquid metal, flip chip interconnections showed an average transition loss of 0.7dB over the MMIC's frequency of operation (4.9 - 8.5 GHz). Passive assemblies were also fabricated to characterize the power and temperature performance of liquid metal transitions. Liquid metal interconnections show excellent power handling, maintaining consistent RF performance while transmitting 100W of continuous wave power for an hour. Liquid metal interconnections were also tested following 200 temperature cycles over the -140°C – 125°C range. A comparison of S parameter measurements taken before and after temperature cycling, over a frequency range of 10MHz - 40GHz showed no significant changes in performance. These passive assemblies were also used to develop a lumped element model of the interconnection which is useful for the verification the interconnection\'s performance and for comparison of liquid metal interconnection parasitic to wire bond and flip chip interconnect parasitics. The experimental results presented in this dissertation confirm that liquid metal interconnect are viable for wider use in military and commercial applications. In the future, additional environmental testing and further refinement of the processing flow, such as improved contact metallurgy, are needed to make this interconnect approach more viable for large volume manufacturing. / Ph. D.

L’entreprise IBM a lancé en 2014 un projet de recherche pour introduire de l’intelligence, c’est-à-dire des capteurs, dans des modules micro-électroniques. Le projet vise l’amélioration, à partir des données des capteurs, des procédés d’assemblage de puce qui serviront dans des serveurs pour du calcul haute performance ou les télécommunications.Mon projet consiste à concevoir, caractériser, puis intégrer 109 micro-capteurs, de dimensions 1 x 100 x 100 µm3, de température, humidité et contrainte sur une puce électronique de 2 x 2 cm2. L’objectif est d’obtenir en temps réel la répartition de l’humidité, la température et la contrainte dans l’assemblage, en environnement sévère.Les capteurs à base de nanotubes de carbone réalisés sont très sensibles à l’humidité et la température, avec par exemple une variation de 50% de la grandeur de sortie du capteur pour une variation de -40 à 140 °C. J’ai proposé une méthode novatrice à partir des propriétés de l’impédance du capteur permettant la séparation de la réponse à la température de celle à l’humidité. / IBM is combining forces with the Université de Sherbrooke to introduce intelligency, which are sensors, in microelectronics module. The project is to make the assembly process of a chip more robust thanks to the sensor data. These microelectronics module are used in high-performance computing servers or telecommunications. The objectives are to design, characterize and embed 109 micro-sensors, having dimensions below 1 x 100 x 100 µm3. These micro-sensors will be on chip and measure temperature, moisture and strain. Thus these micro-sensors will give the spatial distribution of temperature, moisture and strain into the microelectronics module in severe environments. The carbon nanotube-based sensor realized are very sensitive to moisture and temperature, as example the output quantity value of the sensors is reduced by 50 per cent with a temperature excursions from -40 to 140 ℃. I developed a novel method to separate the temperature response from the moisture one, using the impedance properties of the sensor.

Neste trabalho é apresentada a análise de técnicas para a integração de ISFETs (Ion Selective Field Effect Transitors), através do método de montagem por viragem (Flip-chip) usando pasta de solda livre de chumbo e epóxi condutivo de prata, com o objetivo de permitir sua aplicação em Microssistemas de Análise Total (µTAS). Para os testes de integração foram construídas estruturas em dois substratos, o FR-4, pelo método de ligação por fios (wire bonding), e o LTCC, que pode ser aplicado na construção de µTAS. Como os terminais de contato do ISFET tem seu acabamento superficial em alumínio não é possível realizar a montagem por viragem utilizando equipamentos SMT, sendo necessários processos intermediários. Dois processos que permitem o uso de equipamentos SMT foram aplicados: a remetalização, onde camadas de níquel e ouro são depositadas sobre o alumínio do terminal de contato, através do banho químico eletrolítico sem eletrodo (Electroless), e protuberâncias de solda (stud ou ball bumps), que são ligadas ao alumínio do terminal de contato pelo processo conhecido como Stud Ball Bumping (SBB). Na integração do ISFET foi feita a selagem dos terminais de contato e a abertura de uma janela que permite o contato da área ativa (região de porta) do ISFET com as soluções a serem analisadas. A selagem dos terminais de contato foi feita com o fotoresiste SU-8, e a abertura da área ativa foi feita diretamente sobre os substratos de FR-4 e LTCC. Ambos processos apresentaram soldabilidade com a pasta de solda apresentando ponto de refusão em torno de 250°C, indicando que equipamentos SMT podem ser aplicados na montagem por viragem. Verificou-se que o epóxi condutivo de prata foi curado a 100°C por uma hora e também pode ser aplicado na integração do ISFET. Por fim o SU-8 usado na selagem apresentou uma boa adesão aos substratos de FR-4 e LTCC, sendo curado na mesma etapa térmica da pasta de solda e/ou epóxi condutivo de prata ou após estes processos a 150°C por trinta minutos. / In this work is shown the analysis of integration techniques of ISFET (Ion Selective Field Effect Transitor) through the Flip-chip method using lead-free solder paste and silver conductive epoxy, in order to allow its application in Micro Total Analysis System (µTAS). For integration tests two substrates have been made, the FR-4, as already used in the integration of the ISFET, but assembled through wire bonding method, and the LTCC that can be applied in the construction of µTAS. As the ISFET bonding pads has its surface finish in aluminum is not possible assembly through flip-chip method using SMT equipments, requiring intermediate processes. Two process that allow the use of SMT equipment were applied: the remetallization, where nickel and gold layers are deposited on the aluminum bonding pads, through the Electroless chemical baths, and stud or ball bumps, which are connected to bonding pads of aluminum by the process known as Stud Ball Bumping (SBB). In the ISFET integration should be made a seal in the bonding pads and a window that allows the contact of the active area (gate region) of ISFET with the solutions to be analyzed. The sealing of the bonding pads has been made with the photoresist SU-8 and the window of active area were made directly on the FR-4 and LTCC substrates. Both processes presented the solderability with the solder paste reflowed at 250°C, indicating that SMT equipments may be applied to the assembly through flip-chip method, the silver conductive epoxy was cured at 100°C for one hour and can also be applied in ISFET integration. Finally the SU-8 used to sealing have showed a good adherence to the FR-4 and LTCC substrates, being cured in the same thermal step of solder paste and/or silver conductive epoxy or after these processes at 150°C for thirty minutes.

Neste trabalho foi feita uma ampla pesquisa sobre blocos de RF, VCOs e LNAs, que fazem parte de transceptores. Esses blocos foram projetados utilizando um indutor externo com um alto Q, com o intuito de melhorar as principais características de desempenho de cada um dos blocos. Com a finalidade de ter um ponto de comparação foram projetados os mesmos blocos implementando todos os indutores integrados (internos). Foi proposta a utilização da tecnologia flip chip para interconectar os indutores externos aos dies dos circuitos, devido às vantagens que ela apresenta. Para implementar os indutores externos propôs-se um processo de fabricação completo, incluindo especificação das etapas de processos e dos materiais utilizados para estes indutores. Adicionalmente foi projetado um conjunto de máscaras para fabricar os indutores externos e fazer a montagem e teste dos circuitos que os utilizam. Para validar o processo proposto e caracterizar os indutores externos foram projetadas diferentes estruturas de teste. O Q do indutor externo é da ordem de 6 vezes maior que do indutor integrado, para a tecnologia escolhida. Foram projetados e fabricados dois VCOs LC: FC-VCO (Flip Chip VCO com o indutor externo), OC-VCO (On Chip VCO com o indutor interno), e dois LNAs CMOS de fonte comum cascode com degeneração indutiva: FC-LNA (Flip Chip LNA com o indutor Lg externo) e OC-LNA (On Chip LNA com todos os indutores internos). O objetivo desses quatro circuitos é demonstrar que o desempenho de circuitos RF pode ser melhorado, usando indutores externos com alto Q, conectados através de flip chip. Para implementação desses circuitos utilizou-se a tecnologia de processo AMS 0,35µm CMOS, para aplicações na banda 2,4GHz ISM, considerando o padrão Bluetooth. Foram medidos apenas os blocos com os indutores internos (OC-VCO e OC-LNA). Para os blocos com os indutores externos (FC-VCO e FC-LNA) foram apresentados os resultados de simulação pós-layout. Através da comparação dos resultados de simulação entre os VCOs foi comprovado que o uso de um indutor externo com alto Q conectado via flip chip pode melhorar significativamente o ruído de fase dos VCOs, atingindo -117dBc/Hz a 1MHz de frequência de offset para o FC-VCO, em 2,45GHz, onde a FOM é 8dB maior que o OC-VCO. Outro ganho foi através da área poupada, o FC-VCO tem uma área cerca de 83% menor que a do OC-VCO. Após as medidas elétricas do OC-VCO obteve-se um desempenho do ruído de fase de -110dBc/Hz@1MHz para 2,45GHz, e -112dBc/Hz@1MHz para 2,4GHz, o qual atende as especificações de projeto. O FC-LNA, que foi implementado com o indutor de porta Lg externo ao die, conectado via flip chip, atingiu uma figura de ruído de 2,39dB, 1,1dB menor que o OC-LNA com o mesmo consumo de potência. A área ocupada pelo FC-LNA é aproximadamente 30% menor do que o OC-LNA. Através das medidas elétricas do OC-LNA verificou-se que o circuito apresenta resultados adequados de S11 (perda de retorno da entrada) e S22 (perda de retorno da saída) na banda de frequências de interesse. No entanto, o valor do ganho apresenta uma redução em relação ao esperado. A proposta do trabalho de unir a tecnologia flip chip ao uso de indutores externos, proporciona circuitos mais compactos e consecutivamente mais baratos, pela economia de área de Si. Adicionalmente, após os indutores externos serem caracterizados, os mesmos indutores podem ser reutilizados independente da tecnologia CMOS utilizada facilitando o projeto dos blocos de RF em processos mais avançados. / This work presents a research about RF blocks that are used in Transceivers, VCOs and LNAs. These blocks were designed using a high-Q RF external inductor in order to improve the main performance characteristics. The same blocks were designed implementing all inductors on-chip (internal) in order to have a point of comparison. It was proposed the use of Flip Chip technology to interconnect the external inductors to the dies of the circuits due to the advantages that this technology offers. A full manufacturing process was proposed to implement the external inductors, including the specification of process steps and materials used for these inductors. Additionally, a set of masks was designed to fabricate the external inductors, to mount and test the circuits that used these inductors. Different test structures were designed to validate the proposed process and to characterize the external inductors. Q factor of the external inductor is around 6 times larger than the inductor integrated into the chosen IC technology. Two LC VCOs and two common-source cascode CMOS LNAs with inductive degeneration were designed and fabricated: FC-VCO (Flip Chip VCO using external inductor), OC-VCO (On Chip VCO using on-chip inductor), FCLNA (Flip Chip LNA using an external Lg inductor) and OC-LNA (On Chip LNA with all inductors implemented on-chip). The purpose of these four circuits is to demonstrate that the performance of RF circuits can be improved by using high-Q external inductors, connected by flip chip. The 0.35µm CMOS AMS technology was used to implement these circuits intended for applications in the 2.4 GHz ISM band, considering the Bluetooth standard. Were measured only the blocks with internal inductors (OC-VCO and OC-LNA). For the blocks with external inductors (FCVCO and FC-LNA) were presented the results of post-layout simulation. The comparison between the VCOs simulations results demonstrates that using an external high-Q inductor connected by flip chip can significantly improve the phase noise of VCOs. FC-VCO reached a phase noise of -117dBc/Hz at 1MHz offset frequency and a FOM 8dB greater than the OC-VCO. Another important improvement was the saved area, the FC-VCO has an area approximately 83% lower than that of OC-VCO. After electrical characterizations of the OC-VCO, phase noise performances of -110dBc/Hz@1MHz for 2.45GHz and -112dBc/Hz@1MHz for 2.4GHz were obtained, that accomplish the design specifications. FC-LNA reached a noise figure of 2.39dB, 1.1dB lower than that of OC-LNA with the same power comsumption. The total area occupied by FC-LNA is around 30% lower than that OC-LNA. Measurement results of the OC-LNA showed that the circuit presents suitable S11 (input return loss) and S22 (output return loss) values in the desired frequency band. However, the gain value presents a reduction compared with the expected values. The proposal to use the flip chip technology together with external inductors, allows more compact and cheap circuits, because Silicon area can be saved. Moreover, after the external inductors being characterized, the same inductors can be reused regardless of the CMOS technology facilitating the design of RF blocks in more advanced processes.

L’assemblage et le conditionnement en électronique représentent un enjeu de création de nouveaux systèmes électroniques hybrides rassemblant sur un même substrat des éléments électroniques, optiques, mécaniques… La technologie Flip-chip , introduite par IBM et baptisée C4 (Control Collapse Chip Connection), garantit une plus grande densité d’intégration tout en gardant les mêmes dimensions de puce. Au coeur de cette technologie, le « Bumping » est un procédé qui consiste en l’introduction d’une microbille conductrice entre deux plots de connexion des puces afin de réaliser une liaison électrique et mécanique avec le niveau de packaging suivant. La technique de dépôt par sérigraphie de pâte à braser est récemment devenue pratique en raison de son adaptation aux alliages sans plomb. Cette méthode présente l'avantage d'un faible coût et d'une possible production à grande échelle. Nous avons donc choisi de développer cette technique afin d’obtenir des matrices de connexions électriques de dimensions comprises entre 50 μm et 100 μm, pour une pâte à braser de type Sn3.0Ag0.5Cu. Nous avons déterminé les paramètres de sérigraphie afin d’obtenir un minimum d’étalement de pâte pour un remplissage maximum des ouvertures du masque choisi en Ni-électroformé d’épaisseur 50μm : une vitesse de racle de 20mm/s et une vitesse de démoulage de 4mm/s sont par exemple à retenir pour une pâte de type 5. L’étude du masque de sérigraphie a conduit au choix d’ouvertures circulaires. Des formes de billes circulaires ont été obtenues pour des UBM (Under Bump Metallurgy) également circulaires, de diamètre ¼ et ½ le diamètre de l’ouverture du masque. L’optimisation du profil de refusion a permis de déterminer qu’un palier à 180°C, un TAL de 90s ou plus et une température maximale à 250°C favorisaient l’obtention de billes circulaires avec absence de vides. Pour une pâte de type 6, des billes de 60à 70μm de diamètre ont été obtenues pour des ouvertures de masque de 100μm. Une étude de fiabilité de ces billes à partir de tests de cisaillement et de l’analyse des IMC (composés intermétalliques) formés après refusion a permis de montrer que des UBM en Cr-Cu-Au, de diamètre égal à la moitié de l’ouverture du masque, permettaient d’assurer un meilleur maintien mécanique des billes / The semiconductor industry has continuously improved its products by increasing the density of integration resulting in an increasing of the I/Os, always with a low cost requirement. To obtain high-density and high-speed packaging, the Flip-Chip interconnection technology was introduced by IBM also called C4 (Control Collapse Chip Connection). Solder bumps have been widely used in electronic industry and were generally based on the Sn-Pb alloy, for its low melting point and good wetting property. Containing highly toxic element (Pb), Pb-Sn solder alloy has been banned. The ternary alloy Sn-Ag-Cu seems to be the best compromise, in fact it as physical and chemical characteristics equivalent to that of Sn-Pb.In this study we are interested to optimize stencil printing process and adjust it with the flip-chip technology, in order to obtain solder bumps which height is between 50µm and 100µm associated to pitches less than or equal to 200µm, using Sn-3.0Ag-0.5Cu solder paste. We have optimized the stencil printing parameters machine, the stencil apertures shape and size (circular shape and 50µm height, for a Ni-electroformed stencil). Spherical solder balls have been achieved with circular UBM (Under Bump Metallurgy), which diameter is ¼ and ½ the diameter of the stencil aperture. The reflow thermal profile is the key to the formation of a reliable solder bump. It must allow a homogeneous reflow for all particles of the metallic solder paste. We define a thermal profile with a Time above liquidus (TAL) of 90s, a temperature in soaking zone (Ts) of 180°C and a maximum temperature (Tmax) of 250°C. For type 6 solder pastes, balls of 60-70µm diameter have been obtained for 100µm stencil apertures.The quality of a solder joint is directly related to the adhesion of the solder ball to the substrate. Among the various methods of mechanical testing, shear testing is the most widely used to assess the strength of the attachment of beads to the substrate and determine the fragility of the ball at the interface caused by the intermetallic layer compounds (IMC) formed after the reflow step. We have shown that Cr-Cu-Au UBM, with a diameter equal to the half of the stencil aperture, ensure the mechanical adhesion of the balls

Neste trabalho é apresentada a análise de técnicas para a integração de ISFETs (Ion Selective Field Effect Transitors), através do método de montagem por viragem (Flip-chip) usando pasta de solda livre de chumbo e epóxi condutivo de prata, com o objetivo de permitir sua aplicação em Microssistemas de Análise Total (µTAS). Para os testes de integração foram construídas estruturas em dois substratos, o FR-4, pelo método de ligação por fios (wire bonding), e o LTCC, que pode ser aplicado na construção de µTAS. Como os terminais de contato do ISFET tem seu acabamento superficial em alumínio não é possível realizar a montagem por viragem utilizando equipamentos SMT, sendo necessários processos intermediários. Dois processos que permitem o uso de equipamentos SMT foram aplicados: a remetalização, onde camadas de níquel e ouro são depositadas sobre o alumínio do terminal de contato, através do banho químico eletrolítico sem eletrodo (Electroless), e protuberâncias de solda (stud ou ball bumps), que são ligadas ao alumínio do terminal de contato pelo processo conhecido como Stud Ball Bumping (SBB). Na integração do ISFET foi feita a selagem dos terminais de contato e a abertura de uma janela que permite o contato da área ativa (região de porta) do ISFET com as soluções a serem analisadas. A selagem dos terminais de contato foi feita com o fotoresiste SU-8, e a abertura da área ativa foi feita diretamente sobre os substratos de FR-4 e LTCC. Ambos processos apresentaram soldabilidade com a pasta de solda apresentando ponto de refusão em torno de 250°C, indicando que equipamentos SMT podem ser aplicados na montagem por viragem. Verificou-se que o epóxi condutivo de prata foi curado a 100°C por uma hora e também pode ser aplicado na integração do ISFET. Por fim o SU-8 usado na selagem apresentou uma boa adesão aos substratos de FR-4 e LTCC, sendo curado na mesma etapa térmica da pasta de solda e/ou epóxi condutivo de prata ou após estes processos a 150°C por trinta minutos. / In this work is shown the analysis of integration techniques of ISFET (Ion Selective Field Effect Transitor) through the Flip-chip method using lead-free solder paste and silver conductive epoxy, in order to allow its application in Micro Total Analysis System (µTAS). For integration tests two substrates have been made, the FR-4, as already used in the integration of the ISFET, but assembled through wire bonding method, and the LTCC that can be applied in the construction of µTAS. As the ISFET bonding pads has its surface finish in aluminum is not possible assembly through flip-chip method using SMT equipments, requiring intermediate processes. Two process that allow the use of SMT equipment were applied: the remetallization, where nickel and gold layers are deposited on the aluminum bonding pads, through the Electroless chemical baths, and stud or ball bumps, which are connected to bonding pads of aluminum by the process known as Stud Ball Bumping (SBB). In the ISFET integration should be made a seal in the bonding pads and a window that allows the contact of the active area (gate region) of ISFET with the solutions to be analyzed. The sealing of the bonding pads has been made with the photoresist SU-8 and the window of active area were made directly on the FR-4 and LTCC substrates. Both processes presented the solderability with the solder paste reflowed at 250°C, indicating that SMT equipments may be applied to the assembly through flip-chip method, the silver conductive epoxy was cured at 100°C for one hour and can also be applied in ISFET integration. Finally the SU-8 used to sealing have showed a good adherence to the FR-4 and LTCC substrates, being cured in the same thermal step of solder paste and/or silver conductive epoxy or after these processes at 150°C for thirty minutes.

Neste trabalho foi feita uma ampla pesquisa sobre blocos de RF, VCOs e LNAs, que fazem parte de transceptores. Esses blocos foram projetados utilizando um indutor externo com um alto Q, com o intuito de melhorar as principais características de desempenho de cada um dos blocos. Com a finalidade de ter um ponto de comparação foram projetados os mesmos blocos implementando todos os indutores integrados (internos). Foi proposta a utilização da tecnologia flip chip para interconectar os indutores externos aos dies dos circuitos, devido às vantagens que ela apresenta. Para implementar os indutores externos propôs-se um processo de fabricação completo, incluindo especificação das etapas de processos e dos materiais utilizados para estes indutores. Adicionalmente foi projetado um conjunto de máscaras para fabricar os indutores externos e fazer a montagem e teste dos circuitos que os utilizam. Para validar o processo proposto e caracterizar os indutores externos foram projetadas diferentes estruturas de teste. O Q do indutor externo é da ordem de 6 vezes maior que do indutor integrado, para a tecnologia escolhida. Foram projetados e fabricados dois VCOs LC: FC-VCO (Flip Chip VCO com o indutor externo), OC-VCO (On Chip VCO com o indutor interno), e dois LNAs CMOS de fonte comum cascode com degeneração indutiva: FC-LNA (Flip Chip LNA com o indutor Lg externo) e OC-LNA (On Chip LNA com todos os indutores internos). O objetivo desses quatro circuitos é demonstrar que o desempenho de circuitos RF pode ser melhorado, usando indutores externos com alto Q, conectados através de flip chip. Para implementação desses circuitos utilizou-se a tecnologia de processo AMS 0,35µm CMOS, para aplicações na banda 2,4GHz ISM, considerando o padrão Bluetooth. Foram medidos apenas os blocos com os indutores internos (OC-VCO e OC-LNA). Para os blocos com os indutores externos (FC-VCO e FC-LNA) foram apresentados os resultados de simulação pós-layout. Através da comparação dos resultados de simulação entre os VCOs foi comprovado que o uso de um indutor externo com alto Q conectado via flip chip pode melhorar significativamente o ruído de fase dos VCOs, atingindo -117dBc/Hz a 1MHz de frequência de offset para o FC-VCO, em 2,45GHz, onde a FOM é 8dB maior que o OC-VCO. Outro ganho foi através da área poupada, o FC-VCO tem uma área cerca de 83% menor que a do OC-VCO. Após as medidas elétricas do OC-VCO obteve-se um desempenho do ruído de fase de -110dBc/Hz@1MHz para 2,45GHz, e -112dBc/Hz@1MHz para 2,4GHz, o qual atende as especificações de projeto. O FC-LNA, que foi implementado com o indutor de porta Lg externo ao die, conectado via flip chip, atingiu uma figura de ruído de 2,39dB, 1,1dB menor que o OC-LNA com o mesmo consumo de potência. A área ocupada pelo FC-LNA é aproximadamente 30% menor do que o OC-LNA. Através das medidas elétricas do OC-LNA verificou-se que o circuito apresenta resultados adequados de S11 (perda de retorno da entrada) e S22 (perda de retorno da saída) na banda de frequências de interesse. No entanto, o valor do ganho apresenta uma redução em relação ao esperado. A proposta do trabalho de unir a tecnologia flip chip ao uso de indutores externos, proporciona circuitos mais compactos e consecutivamente mais baratos, pela economia de área de Si. Adicionalmente, após os indutores externos serem caracterizados, os mesmos indutores podem ser reutilizados independente da tecnologia CMOS utilizada facilitando o projeto dos blocos de RF em processos mais avançados. / This work presents a research about RF blocks that are used in Transceivers, VCOs and LNAs. These blocks were designed using a high-Q RF external inductor in order to improve the main performance characteristics. The same blocks were designed implementing all inductors on-chip (internal) in order to have a point of comparison. It was proposed the use of Flip Chip technology to interconnect the external inductors to the dies of the circuits due to the advantages that this technology offers. A full manufacturing process was proposed to implement the external inductors, including the specification of process steps and materials used for these inductors. Additionally, a set of masks was designed to fabricate the external inductors, to mount and test the circuits that used these inductors. Different test structures were designed to validate the proposed process and to characterize the external inductors. Q factor of the external inductor is around 6 times larger than the inductor integrated into the chosen IC technology. Two LC VCOs and two common-source cascode CMOS LNAs with inductive degeneration were designed and fabricated: FC-VCO (Flip Chip VCO using external inductor), OC-VCO (On Chip VCO using on-chip inductor), FCLNA (Flip Chip LNA using an external Lg inductor) and OC-LNA (On Chip LNA with all inductors implemented on-chip). The purpose of these four circuits is to demonstrate that the performance of RF circuits can be improved by using high-Q external inductors, connected by flip chip. The 0.35µm CMOS AMS technology was used to implement these circuits intended for applications in the 2.4 GHz ISM band, considering the Bluetooth standard. Were measured only the blocks with internal inductors (OC-VCO and OC-LNA). For the blocks with external inductors (FCVCO and FC-LNA) were presented the results of post-layout simulation. The comparison between the VCOs simulations results demonstrates that using an external high-Q inductor connected by flip chip can significantly improve the phase noise of VCOs. FC-VCO reached a phase noise of -117dBc/Hz at 1MHz offset frequency and a FOM 8dB greater than the OC-VCO. Another important improvement was the saved area, the FC-VCO has an area approximately 83% lower than that of OC-VCO. After electrical characterizations of the OC-VCO, phase noise performances of -110dBc/Hz@1MHz for 2.45GHz and -112dBc/Hz@1MHz for 2.4GHz were obtained, that accomplish the design specifications. FC-LNA reached a noise figure of 2.39dB, 1.1dB lower than that of OC-LNA with the same power comsumption. The total area occupied by FC-LNA is around 30% lower than that OC-LNA. Measurement results of the OC-LNA showed that the circuit presents suitable S11 (input return loss) and S22 (output return loss) values in the desired frequency band. However, the gain value presents a reduction compared with the expected values. The proposal to use the flip chip technology together with external inductors, allows more compact and cheap circuits, because Silicon area can be saved. Moreover, after the external inductors being characterized, the same inductors can be reused regardless of the CMOS technology facilitating the design of RF blocks in more advanced processes.