Afin de pouvoir continuer la miniaturisation de la brique de base des circuits électroniques, le transistor MOS, l’introduction d’oxyde de grille à haute permittivité était inévitable. Un empilement de type high-k/grille métal en remplacement du couple SiO2 /Poly-Si est introduit afin de limiter le courant de fuite tout en conservant un bon contrôle électrostatique du canal de conduction. L’introduction de ces matériaux pose naturellement des questions de fiabilité des dispositifs obtenus et ce travail s’inscrit dans ce contexte. Afin de réaliser des mesures de durée de vie sans avoir à finir les dispositifs, une méthode utilisant le C-AFM sous ultravide est proposée. Le protocole expérimental repose sur une comparaison systématique des distributions des temps de claquage obtenues à l’échelle du composant et à l’échelle nanométrique. La comparaison systématique des mesures s’avère fiable si l’on considère une surface de contact entre la pointe et le diélectrique de l’ordre du nm². Des distributions de Weibull présentant une même pente et un même facteur d’accélération en tension sont rapportées montrant une origine commune pour le mécanisme de rupture aux deux échelles.Une résistance différentielle négative, précédant la rupture diélectrique, est rapportée lors de mesures courant–tension pour certaines conditions de rampe. Ce phénomène de dégradation de l’oxyde, visible grâce au C-AFM , est expliqué et modélisé dans ce manuscrit par la croissance d’un filament conducteur dans l’oxyde. Ce même modèle permet aussi de décrire la rupture diélectrique.Finalement, l’empilement de grille bicouche du noeud 28nm est étudié. Une preuve expérimentale montrant que la distribution du temps de claquage du bicouche est bien une fonction des caractéristiques de tenue en tension propres de chaque couche est présentée. / In order to continue the scaling of the MOS transistor the replacement of the gate oxide layer by a high K/Metal gate was mandatory. From a reliability point of view, the introduction of these new materials could cause a lifetime reduction. To test the lifetime of the device a new technique using the C-AFM under Ultra High Vacuum is proposed. The experimental approach is based on a systematic comparison between the time to failure distribution obtained at device scale and at nanoscale. The comparison is reliable if we assume a contact surface of several nm² under the tip. Weibull distributions with a same slope and a same voltage acceleration factor have been found exhibiting a common origin of breakdown at both scales.We have reported a negative differential resistance phenomenon during Current-Voltage measurements. This degradation phenomenon has been modelled and explained by the growth of a conductive filament in the oxide layer. This model is also able to describe the breakdown of the oxide layer.Finally the bi layer gate stack of the 28nm node was studied. The first experimental proof confirming that the lifetime distribution of the bi-layer gate stack is a function of the lifetime of each layer taken separately is presented.

System on Chip (SoC) and System in Package (SiP) are two electronic technologies that involve integrating multiple functionalities onto a single platform. When the platform is a single wafer, as in SOC, it requires the ability to deposit various materials that enable the different functions on to an underlying substrate that can host the electronic circuitry. Transition metal oxides which have a wide range of properties are ideal candidates for the functional material. Si wafer on which micro-electronics technology is widely commercialized is the ideal host platform. Integrating oxides with Si, generally in the form of thin films as required by microelectronics technology, is however a challenge. It starts with the fact that the properties of crystalline oxides to be exploited in performing various functions are direction dependent. Thus, thin films of these oxides need to be deposited on Si in certain crystallographic orientations. Even if a suitably oriented Si wafer surface were available, it does not always provide for epitaxial growth a critical requirement for controlling the crystalline orientation of thin films. This is because Si surface is covered by an amorphous oxide of Si (SiOx). Thus, during growth of the functional oxide, an ambience in which the Si itself will not oxidize needs to be provided. In addition, during thin film growth on either Si or SiOx surface stresses are generated from various sources. Stress and its relaxation are also associated with the formation and evolution of defects. Both, stress and defects need to be managed in order to harness their beneficial effects and prevent detrimental ones. Given the requirement of SoC technology and the problem associated, the research work reported in this thesis was hence concerned with the precise controlling the stress and microstructure in oxide thin films deposited on Si substrates. In order to do so a versatile, ultra high vacuum (UHV) thin film with a base pressure of 10-9 Torr was designed and built as part of this study. The chamber is capable of depositing films by both sputtering (RF & DC) and pulsed laser ablation (PLD). The system has been designed to include an optical curvature measurement tool that enabled real-time stress measurement during growth. Doped zirconia, ZrO2, was chosen as the first oxide to be deposited, as it is among the few oxides that is more stable than SiOx. It is hence used as a buffer layer. It is shown in this thesis that a change in the growth rate at nucleation can lead to (100) or (111) textured films. These two are among the most commonly preferred orientation. Following nucleation a change in growth rate does not affect orientation but affects stress. Thus, independent selection of texture and stress is demonstrated in YSZ thin films on Si. A quantitative model based on the adatom motion on the growth surface and the anisotropic growth rates of the two orientations is used to explain these observations. This study was then subsequent extended to the growth on platinized Si another commonly used Si platform.. A knowledge of the stress and microstructure tailoring in cubic zirconia on Si was then extended to look at the effect of stress on electrical properties of zirconia on germanium for high-k dielectric applications. Ge channels are expected to play a key role in next generation n-MOS technology. Development of high-k dielectrics for channel control is hence essential. Interesting stress and property relations were analyzed in ZrO2/Ge. Stress and texture in pulsed laser deposited (PLD) oxides on silicon and SrTiO3 were studied. It is shown in this thesis that stress tuning is critical to achieve the highest possible dielectric constant. The effect of stress on dielectric constant is due to two reasons. The first one is an indirect effect involving the effect of stress on phase stability. The second one is the direct effect involving interatomic distance. By stress control an equivalent oxide thickness (EOT) of 0.8 nm was achieved in sputter deposited ZrO2/Ge films at 5 nm thickness. This is among the best reported till date. Finally, the effect of growth parameters and deposition geometry on the microstructural and stress evolution during deposition of SrTiO3 on Si and BaTiO3 on SrTiO3 by pulsed laser deposition is the same chamber is described.

This thesis studies the interaction between the bare Cu{311} surface with NO and NH3,individually and co-adsorbed using reflection-absorption infrared spectroscopy (RAIRS). In addition to the bare Cu{311} surface, the interaction of NO and NH3 with the various oxygen phases of the Cu{311} surface phases was also studied. Several other techniques were used in tandem to support the study, such as low energy electron diffraction (LEED) and temperature programmed desorption (TPD) experiments using mass spectrometry. The study was carried out in pursuit an understanding of the underlying mechanism of the selective catalytic reduction (SCR) of NO using NH3 in current diesel engines. The dosing of NO onto the Cu{311} surface at 100 K leads to the initial adsorption of intact NO. After an exposure threshold is reached, individual NO molecules react with another NO molecule to form (NO)2 dimers. These dimer species subsequently form N2O, leaving O(a) on the surface. Oxygen was found to be an inhibitor for the reaction, either due to the reaction in a self-poisoning process or from oxygen pre-dosing onto the Cu{311} surface. Temperature plays a minor role with regards to NO/Cu{311}, as it only affects the amount of NO on the surface along with adsorbate surface mobility. Similarly, NH3 was found to adsorb intact onto the Cu{311} surface and not to react or dissociate at 100 K. Oxygen acts as a site blocker for the adsorption, but can also stabilise NH3 to remain on the surface at higher temperatures due to electronic effects. At 300 K, it was found that both the bare and oxygen pre-covered Cu{311} surface was able to dissociate NH3 into NH2. The co-adsorption of NO and that of NH3 onto the Cu{311} surface were found to be largely independent of each other and the interaction is dominated by the displacement of NO by NH3. However, as NO adsorption on the Cu{311} surface forms O(a), it indirectly affects the adsorption of NH3 by creating an oxygen covered Cu{311} surface, which changes how NH3 adsorbs onto the surface.

This thesis presents HELIOS, an in-house laboratory for time-resolved pump-probe spectroscopy with extreme-ultraviolet (XUV) probe radiation. A wide span of pump wavelengths can be generated using commercial laser equipment while XUV probe radiation is generated via a high harmonic generation process in a noble gas delivering probe photons with energies between 20 eV and 72 eV. The XUV beam path features a time-preserving monochromator and was constructed and built in-house. HELIOS features an overall time resolution of about 50 fs when using 800 nm pump and 41 eV probe photons. An energy resolution of 110 meV at 41 eV photon energy can be achieved. HELIOS features two beamlines. One µ-focus beamline with an XUV focal size of about 20 µm can be used with experiments that require such a small XUV focal size as well as with different end stations. The other beamline features a semi-permanently mounted end station for angle-resolved photoelectron spectroscopy under ultra-high vacuum conditions. Experiments demonstrating the usability of HELIOS and the two beamlines are presented. A pump-probe measurement on graphene demonstrates the capability of determining a large part of the k-space in only one measurement due to the use of an ARTOF angle-resolved time-of-flight electron spectrometer. A non-angle-resolved pump-probe measurement on the conducting polymer PCPDTBT demonstrates the high signal-to-noise ratio achievable at this beamline in non-angle-resolved photoelectron-spectroscopy pump-probe measurements. The usability of the µ-focus beamline is demonstrated with time-resolved measurements on magnetic samples employing an in-house-designed spectrometer. These experiments allow the retrieval of element-specific information on the magnetization within a sample employing the transversal magneto-optical Kerr effect (T-MOKE). Additionally, a Fourier transform spectrometer for the XUV is presented, the concept was tested at a synchrotron and it was used to determine the longitudinal coherence of the XUV radiation at HELIOS.

We present the development of a novel, UHV-compatible device fabrication strategy for the realisation of nano- and atomic-scale devices in silicon by harnessing the atomic-resolution capability of a scanning tunnelling microscope (STM). We develop etched registration markers in the silicon substrate in combination with a custom-designed STM/ molecular beam epitaxy system (MBE) to solve one of the key problems in STM device fabrication ??? connecting devices, fabricated in UHV, to the outside world. Using hydrogen-based STM lithography in combination with phosphine, as a dopant source, and silicon MBE, we then go on to fabricate several planar Si:P devices on one chip, including control devices that demonstrate the efficiency of each stage of the fabrication process. We demonstrate that we can perform four terminal magnetoconductance measurements at cryogenic temperatures after ex-situ alignment of metal contacts to the buried device. Using this process, we demonstrate the lateral confinement of P dopants in a delta-doped plane to a line of width 90nm; and observe the cross-over from 2D to 1D magnetotransport. These measurements enable us to extract the wire width which is in excellent agreement with STM images of the patterned wire. We then create STM-patterned Si:P wires with widths from 90nm to 8nm that show ohmic conduction and low resistivities of 1 to 20 micro Ohm-cm respectively ??? some of the highest conductivity wires reported in silicon. We study the dominant scattering mechanisms in the wires and find that temperature-dependent magnetoconductance can be described by a combination of both 1D weak localisation and 1D electron-electron interaction theories with a potential crossover to strong localisation at lower temperatures. We present results from STM-patterned tunnel junctions with gap sizes of 50nm and 17nm exhibiting clean, non-linear characteristics. We also present preliminary conductance results from a 70nm long and 90nm wide dot between source-drain leads which show evidence of Coulomb blockade behaviour. The thesis demonstrates the viability of using STM lithography to make devices in silicon down to atomic-scale dimensions. In particular, we show the enormous potential of this technology to directly correlate images of the doped regions with ex-situ electrical device characteristics.

We present the development of a novel, UHV-compatible device fabrication strategy for the realisation of nano- and atomic-scale devices in silicon by harnessing the atomic-resolution capability of a scanning tunnelling microscope (STM). We develop etched registration markers in the silicon substrate in combination with a custom-designed STM/ molecular beam epitaxy system (MBE) to solve one of the key problems in STM device fabrication ??? connecting devices, fabricated in UHV, to the outside world. Using hydrogen-based STM lithography in combination with phosphine, as a dopant source, and silicon MBE, we then go on to fabricate several planar Si:P devices on one chip, including control devices that demonstrate the efficiency of each stage of the fabrication process. We demonstrate that we can perform four terminal magnetoconductance measurements at cryogenic temperatures after ex-situ alignment of metal contacts to the buried device. Using this process, we demonstrate the lateral confinement of P dopants in a delta-doped plane to a line of width 90nm; and observe the cross-over from 2D to 1D magnetotransport. These measurements enable us to extract the wire width which is in excellent agreement with STM images of the patterned wire. We then create STM-patterned Si:P wires with widths from 90nm to 8nm that show ohmic conduction and low resistivities of 1 to 20 micro Ohm-cm respectively ??? some of the highest conductivity wires reported in silicon. We study the dominant scattering mechanisms in the wires and find that temperature-dependent magnetoconductance can be described by a combination of both 1D weak localisation and 1D electron-electron interaction theories with a potential crossover to strong localisation at lower temperatures. We present results from STM-patterned tunnel junctions with gap sizes of 50nm and 17nm exhibiting clean, non-linear characteristics. We also present preliminary conductance results from a 70nm long and 90nm wide dot between source-drain leads which show evidence of Coulomb blockade behaviour. The thesis demonstrates the viability of using STM lithography to make devices in silicon down to atomic-scale dimensions. In particular, we show the enormous potential of this technology to directly correlate images of the doped regions with ex-situ electrical device characteristics.