The objective of this research was to build a reprogrammable computational imager utilizing on-chip analog computations for the purpose of studying the capabilities of integrated sensing and processing. Unlike conventional imaging systems, which acquire image data and perform calculations on it, this system tightly integrates the computation and sensing into one process. This allows the exploration of intelligent and efficient sensory and processing. The IC architecture and circuit designs have focused on wide dynamic range signals. The fundamental computation performed is a separable two-dimensional transform. This allows various operations, including block transformations and separable convolutions. The operations are reprogramable and utilize analog memory and processing along with digital control. The random access to both the image plane and the computational operations allows for intraframe transform variations creating a hardware foundation for dynamic sampling and computation. One can also capture scenes with non-uniform resolution. Advantages, including utilization of feedback from processing to sensing and extensions of the technology including support for wavelets and larger transforms are also explored.

Biosensors are extremely powerful analytical tools instrumental for detection and quantification of bio-molecules such as DNA, peptides and even metabolites. The recent decade has seen a surge in biosensing applications ranging from molecular diagnostics, environmental monitoring, basic life science research, forensics and biothreat monitoring. The existing biosensor systems of today, however, have several limitations. They are expensive, bulky in size, power hungry, hard to use and with access limited to core facilities. Among other disadvantages, these impediments discourage the availability of point-of-care testing and low cost in-vitro diagnostics (IVD) in locations such as developing and third world countries. The main bottleneck in the development of low-cost and compact biosensors is the effective and efficient integration of several complex components present inside a typical biosensor. These components are the sample preparation, biomolecular recognition, signal transduction and data analysis. With vii the recent advancements in very large scale integration (VLSI) and fabrication technologies, it is now possible to integrate several of these biosensing components into a small form factor. This thesis proposes leveraging the utilization of VLSI technology to develop a low-cost, miniature, portable, fast analysis, high throughput and low power consumption biosensor solution. Apart from the miniaturization bene- fits, employing VLSI technology facilitates low-cost, high yield and low process variation. We present complementary metal-oxide semiconductor (CMOS) integrated microsystem solutions for fluorescence, bioluminescence and electrochemical biosensing. Simulation models are provided for the microsystems and the specifications for the constituent components derived. A common problem in the transducer development of biosensors that we specifically focus on, is the presence of a large non-informative signal called the background signal. This background signal can be several orders of magnitudes higher than the signal of interest and it reduces the overall sensitivity of the biosensor. Existing transducer solutions rely on very high dynamic range, expensive and power hungry solutions to solve the problem of high background signal. To address the problem of overwhelming background signal, this thesis proposes an active background subtraction architecture merged with a Σ∆ modulator. The robust, versatile architecture can be conveniently employed for optical and electrochemical sensing. The proposed architecture attenuates the background signal very early in the signal chain, achieving high dyviii namic range while significantly relaxing the performance requirements of the subsequent circuit blocks in terms of power dissipation, area and bandwidth requirements. To validate the proposed solution, two CMOS IC prototypes were developed for optical and electrochemical sensing respectively. A 12 × 12 array of Σ∆ photodetector with in-pixel background subtraction was developed in 0.18µm standard CMOS technology. The pixel performance has been validated with over 140dB dynamic range and the ability of subtract the background subtraction current validated from 10nA to 10fA. Real time pyrosequencing experiment has also been performed utilizing the photodetector array. A 12 × 12 array of Σ∆ electrochemical sensor with in-pixel background subtraction was developed in 0.18µm standard CMOS technology. Capacitive charge redistribution circuit architecture for bipolar current measurements was employed. The circuit performance was validated over the wide input current range of 100nA to 1pA. / text

This thesis presents the design and implementation of a current-mode computational CMOS image sensor that performs video image compression based on the CRVDC (conditional replenishment video data compression) algorithm. With such on-chip pre-processing, a compression ratio of 10:1 can be achieved without significant signal degradation. Our research focuses on designing the basic building blocks. As the image sensor works in the current-mode, the building blocks will be current mirrors and current comparators. Several kinds of current mirrors have been analyzed in details and an improved regulated cascode current mirror was chosen. Through simulations and prototyping, we demonstrated that this current mirror is capable of achieving a resolution of 11 bits at 200MHz. To implement the CRVDC algorithm, it was necessary to design an accurate and fast current comparator. Two novel CMOS current comparators were proposed and analyzed and the results were compared to conventional CMOS current comparators. Simulations and measurements demonstrated that the new CMOS current comparators had better performance both in terms of the propagation delay and power dissipation. For the CMOS image sensor, a photodiode-type active pixel transducer was used to convert incident light to photocurrent. The characterization and modeling of the transducer were presented and detailed analyses on the performance was obtained from chips fabricated using the standard 0.18μm CMOS process technology. Since the electrical characteristics of the active devices in the pixel sensor chip can generate large fixed pattern noise (FPN), a current-mode FPN suppression circuit was designed and adopted. Based on the test results obtained from a fabricated prototype chip, a FPN suppression rate of 0.35% was achieved. An on-chip analog to digital converter (ADC) was necessary to implement digital interface and a current-mode pipeline ADC with 8 bit resolution was proposed. Simulation results demonstrated that the ADC was monotonic and possessed an integral nonlinearity (INL) of ±0.45 LSB and a differential nonlinearity (DNL) of ±0.43 LSB. Our results suggested that the overall design can more than adequately meet the system specifications of the computational CMOS image sensor and potentially can be used as a front-end processing block in other image processing applications such as in motion detection and in image segmentation for a dynamic environment.

Le travail de cette thèse vise la réalisation d’un nouveau capteur d’images pour mobile en technologie CMOS (Complementary Metal Oxide Semiconductor). Ce capteur a été développé en vue de répondre à une forte demande du marché. Les prochaines générations de produits, nécessitent des capteurs d’image avec des performances agressives. Par exemple, le niveau de qualité d’image peut être fortement amélioré avec des architectures faible bruit, ou l’utilisation de nouvelles technologies, pour augmenter le niveau du signal ou diminuer la consommation. L’augmentation de la qualité d’image entraîne un agrandissement de la taille des matrices de pixels, et de la résolution des données. La vitesse de conversion devient donc critique. Le sujet de cette thèse porte sur l’amélioration de ce dernier point. Une étude comparative a été réalisée pour étudier différentes architectures. Le convertisseur à rampe est le mieux adapté pour les petits pixels. Toutefois, son principal inconvénient est son temps de conversion qui nécessite 2N cycles d’horloge. Afin d’obtenir un frame rate plus élevé, une méthode tirant profit du bruit photonique a été proposée. Ce circuit de lecture est fondé sur un convertisseur à rampe par morceaux, et un algorithme qui permet la linéarisation des données. Afin de réduire le bruit, cette nouvelle architecture doit prendre en compte le double échantillonnage corrélé digital. Durant la période de conception, des modes de test ont été mis en place pour permettre la caractérisation du circuit. L’innovation se trouve dans le développement d’une rampe par morceaux qui réduit le temps de lecture d’une ligne de 1us. Cependant, ce développement a besoin d’une calibration adaptée. Un prototype de capteur d’image CMOS de 13Mpixel a été fabriqué en 65 nm, 5 niveaux de métaux, et 1 seul niveau de poly en technologie CMOS standard. Les mesures ont montré que l’INL et DNL du convertisseur étaient aussi performantes qu’avec une rampe linéaire classique. Une attention particulière a été apportée sur la mesure du bruit. Malheureusement, le bruit s’est montré plus élevé qu’avec un capteur « classique ». Cependant, la consommation reste identique en ayant une vitesse de conversion plus rapide. Les solutions proposées sont simples à intégrer structurellement, et faciles à mettre en œuvre. Elles ont l’avantage de ne pas impacter la surface du pixel et préservent donc les performances de ce dernier. Les résultats issus des mesures sur silicium sont très encourageants, car on obtient un gain de presque 20% sur le temps de lecture. / The aim of this thesis is the implementation of new image sensors for mobile in CMOS (Complementary Metal Oxide Semiconductor) technology to meet strong market demand. Next generations of products require image sensors with high performances.These improvements would change the image quality with low noise architecture in one hand, and the use of new technologies to increase the signal level, or reduce the power consumption in the other hand. The gain in image quality leads to increase the size of the pixel’s array, and the resolution of the data -the conversion speed becoming critical-. The subject of this thesis focuses on improving this latter point. A comparative study has been made between several architectures to find the best solution that would fit our needs.The ramp converter is the most suitable for small pixels, but his main drawback is the conversion time that requires 2N clock cycles. To obtain a higher frame rate, a method taking advantage of the photon noise has been presented. This readout circuit is based on a piecewise linear ramp converter and an algorithm that allows the linearization of the data. Furthermore, for noise reduction, the new architecture must take into account the digital correlated double sampling. During the period of design, test modes have also been designed and implemented to allow characterization of the circuit.The innovative part is the use of a piecewise linear ramp, which in simulation, reduces the readout time of 1us per row. However, this element needs calibration. A CMOS image sensor prototype of 13Mpixel has been made in 65 nm, 5 levels of metals, and 1 level of poly standard CMOS technology. Measurements showed that the INL and DNL of the converter were as good as with a conventional linear ramp. A careful consideration has been given to the measurement of noise, which unfortunately is higher than a "conventional" sensor. However, the consumption remains the same while having a faster conversion speed. The solutions are simple to integrate structurally and easy to implement. They have the advantage of not affecting the surface of the pixel, thus preserve the performance of the latter. The results found from the silicon-on measures are very encouraging, we gain almost 20% of the conversion time.

Pas de résumé / CMOS image sensor based on Active pixel sensor has considerably contributed to the imaging market and research interest in the past decade. Furthermore technology advancement has provided the capability to integrate more and more functionality into a single chip in multiple layers leading to a new paradigm, 3D integration. CMOS image sensor is one such application which could utilize the capability of 3D stacked architecture to achieve dedicated technologies in different layers, wire length reduction, less area, improved performancesThis research work is focused mainly on the early stages of design space exploration using hierarchical approach and aims at reducing time to market. This work investigates the imager from the top-down design perspective. Methodical anal y sis of imager is performed to achieve high level of flexibility and modularity. Re-useable models are developed to explore early design choices throughout the hierarchy. Finally, pareto front (providing trade off solutions) methodology is applied to explore the operating range of individual block at system level to help the designer making his design choice. Furthermore the thermal issues which get aggravated in the 3D stacked chip on the performance of the imager are studied. Systeme based thermal model is built to investigate the behavior of imager pixel matrix and to simulate the pixel matrix at high speed with acceptable accuracy compared to electrical simulations. The modular nature of the model makes simulations with future matrix extension straightforward. Validation of the thermal model with respect to electrical simulations is discussed. Finally an integrated design flow is developed to perform 3D floorplanning and to perform thermal anal y sis of the imager pixel matrix.

L'avancement de la technologie durant ces dernières années a permis aux imageurs d'atteindre de très hautes résolutions. Ceci a rendu les images plus riches en détails. D'un autre côté, une autre limitation se présente à ce niveau; celle du nombre de bits limité après la conversion analogique numérique. De ce fait, la qualité de l'image peut être affectée. Pour remédier à cette limitation et garder une meilleure qualité de l'image en sortie de son système d'acquisition, l'information lumineuse doit être codée sur un grand nombre de bits et conservée durant tout le flot de traitement pour éviter l'intervention du bruit et la génération des artefacts en sortie du système. En outre, le traitement numérique de chaque pixel sera coûteux en consommation d'énergie et en occupation de surface silicium.Le travail effectué dans cette thèse consiste à étudier, concevoir et implémenter plusieurs fonctions et architectures de traitement d'image en électronique analogique ou mixte. L'implémentation de ces fonctions en analogique permet de décaler la conversion de l'information lumineuse en numérique vers une étape ultérieure. ceci permet de conserver un maximum de précision sur l'information traitée. Ces fonctions et leurs architectures ont un but d'améliorer la dynamique de fonctionnement des imageurs CMOS standard (à intégration), en utilisant des techniques à temps d'intégration variable, et des "tone mapping" locaux qui imitent le système de vision humaine.Les principes de fonctionnement, les émulations sous MATLAB, la conception et les simulations électriques ainsi que les résultats expérimentaux des techniques proposées sont présentés en détails dans ce manuscrit. / The technology progress in recent years has enabled imagers to reach a very high resolutions. This allows images to be more detailed and rich in information. On the other hand, the limited number of bites after the digital analogue conversion may drastically affect the quality of the image. To maintain the quality of the output image of the acquisition system, the luminous information should be (1) encoded on a large number of bits and (2) maintained throughout the processing flow so that to avoid noise interference and generating artifacts system output. However, the digital processing of each pixel will be energy consuming will occupy more surface silicon.The goal of this thesis is to study, design and implement several image processing functions as well as their architectures using analog and mixed electronic. Implementation of these functions shifts the analog to digital conversion to a subsequent step. This allows a maximum precision of the processed information. The proposed functions and their architectures improve the operational dynamics Standard CMOS imagers using (1) variable integration time techniques, and (2) "tone mapping" which mimics the human vision system.The experimental results based on emulations in Matlab and the electrical design show the novelty and the efficiency of the proposed method.

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第22442号 / 工博第4703号 / 新制||工||1734(附属図書館) / 京都大学大学院工学研究科原子核工学専攻 / (主査)教授 斉藤 学, 教授 神野 郁夫, 准教授 松尾 二郎 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

Les capteurs d’images cherchent de nos jours non seulement à être performant mais également à être adaptés à leur environnement et à de nouvelles utilisations. On peut évoquer le cas des machines et véhicules autonomes par exemple. En raison de la qualité d’image et son coût, une vaste majorité des applications ont aujourd’hui adopté l’usage des pixels CMOS actifs à photodiodes pincées et à illumination par la face arrière.L’originalité de la solution proposée dans ce manuscrit repose l’intégration d’une photogate, utilisée par les capteurs CCD, au sein d’un pixel CMOS. Son utilisation optimise alors l’espace disponible dans le pixel et diminue le nombre d’implantation nécessaire à sa réalisation. Ce développement a également conduit à l’emploi d’une grille de transfert spécifique. Ces deux nouvelles structures auront toutes les deux été élaborées durant cette thèse notamment à l’aide de simulations et de structures de test.La caractérisation de ce nouveau pixel aura démontré de nombreux atouts : entre autres, l’augmentation de la charge à saturation et la réduction du courant d’obscurité. De plus, l’étude détaillée du courant d’obscurité indique une distribution davantage centrée. Celle-ci permet l’identification de contaminants et une meilleure tenue en température en comparaison à une photodiode classique.De nombreuses perspectives s’offrent à la structure telle que la réduction du pas du pixel ou son utilisation dans un environnement contraint en température. / Nowadays image sensors look neither to be efficient, but rather to be adapted to their environment or to new uses. Autonomous machines and vehicles can be mentioned for instance. Because of image quality and cost, a large majority of applications employs CMOS pixels and pinned back-side illuminated photodiodes.The originality of the solution proposed in this manuscript relies on the integration of a photogate, used by CCD sensors, inside a CMOS pixel. Its use optimize the available space inside the pixel and decrease the number of implantation needed to its realization. This development has also led to the use of specific transfer gate. Both structures have been created during this thesis and designed using simulation and specific test structures.The characterization of the developed pixel demonstrate many assets such as an increase of saturation charges and a reduction of dark current. Furthermore, a detailed study of the dark currant indicates a more gathered pixel distribution, allowing the identification of contaminants and a better temperature handling in comparison to a classical photodiode.The proposed structure offers many perspectives such as reduction of the pixel pitch or its potential use in an environment with a temperature constraint.

Cette thèse porte sur la conception et la réalisation de convertisseurs analogique/numérique (ADC) haute résolution dans le domaine de l’imagerie spatiale en technologie 0.18 μm.Un imageur CMOS est un système destiné à acquérir des informations lumineuses et les convertir en données numériques afin que cellesci soient traitées. Ce système est composé d’une matrice de pixels, d’ADC, de registres et de blocs de signaux de commande afin de rendre toutes ces données disponibles. Avec la taille grandissante de la matrice de pixels et la cadence d’image par seconde croissante, l’ADC doit réaliser de plus en plus de conversions en moins de temps et est donc devenu l’un des « bottleneck » les plus importants dans les systèmes d’imagerie. Une solution adaptée a donc été le développement d’ADC colonne situé en bout de colonnes de pixels afin de réaliser des conversions en parallèles et c’est ce sujet qui va m’intéresser.Dans une première partie, n’ayant pas de contraintes sur l’architecture d’ADC à utiliser, une étude de l’état de l’art des ADC pour l’imagerie est réalisée ainsi que les spécifications visées pour notre application. Une architecture sigma-delta incrémental à deux étapes semble la plus prometteuse et va être développée. Ensuite, une étude théorique de l’ADC choisi, et plus particulièrement du modulateur sigma-delta à utiliser est effectuée, afin notamment de déterminer l’ordre de ce modulateur, mais également le nombre de cycles de cette conversions. Une fois les paramètres de modélisation définis, un schéma transistor est réalisé au niveau transistor, avec une particularité au niveau de l’amplificateur utilisé. En effet, afin de gagner en surface qui est l’un des points importants dans les systèmes d’imagerie, un inverseur est utilisé. Une étude de cette inverseur, afin de choisir le plus adapté à notre besoin est effectuée avec des simulations montecarlo et aux « corners ». Pour finir, un routage global de l’ADC est réalisé afin de pouvoir comparer ces performances à l’état de l’art. / This thesis deals with the conception and design of high resolution analog-to-digital converters (ADC) for CMOS image sensor (CIS) applications with the 0.18 μm technology. A CIS is a system able to convert light to digital data to be processed. This system includes a pixel array, ADCs, registers and a set of clocks to acquire and transport the data. At the beginning, a single ADC was used for the whole matrix of pixels, converting the pixel value in a sequential way. With the growing size of the pixel array and the increasing frame rate, the ADC became one of the bottleneck of these system. A solution was found to use column ADC, located at the bottom of each column in order to parallelize the conversions. These column ADC are going to be my point of interest in this thesis.First of all, a state of the art of the ADC for CIS is realized in order to determine the best architecture to use. A two-step incremental sigma-delta is chosen and investigated. A theoretical analysis is done, especially on the modulator in order to determine the order of this modulator and the oversampling ratio of the conversion. Then a schematic is realized, with a special feature on the amplifier. Indeed, an inverter is used as amplifier in order to reduce the size of the ADC. A montecarlo and corner studies are then realized on the ADC, a layout is proposed and the ADC is compared to the state of the art of the ADC for CIS.

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第19700号 / 工博第4155号 / 新制||工||1641(附属図書館) / 32736 / 京都大学大学院工学研究科機械理工学専攻 / (主査)教授 井手 亜里, 教授 松野 文俊, 教授 蓮尾 昌裕 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DGAM