Variable-speed Induction motor drives are nowadays used for various kinds of industrial processes, transportation systems, wind turbines and household appliances in the world. The majority of drives are for general purpose speed control applications where accurate speed control is not required for entire speed range. But for high dynamic drive application, very precise and fast control of induction motor drive is essential. For such applications, sophisticated and well-performing control design is a key issue. Precise and accurate torque control of the Induction Motor (IM) can only be accomplished by vector control and direct torque control. In terms of space vector theory, vector control implies that the instantaneous torque is controlled by way of the stator current vector that is orthogonal to the rotor flux vector. Precise knowledge of the rotor flux angle is therefore essential for a vector controlled IM. IMs do not allow the flux position to be easily measured, so most modern vector controlled IM drives rely on flux estimation. This means that the flux angle is derived from a flux estimator, using the dynamic model of the IM. Given that the rotor speed of the IM is measured by a mechanical shaft sensor. Flux estimation is a fairly easy task. However, vector control of IM without mechanical shaft speed sensor is of current interest in industrial environment. The driving motivations behind the development in sensorless control are lower cost, improved reliability and operating environment. In this thesis, a sensorless vector control scheme for rotor flux estimation using current error space phasor based hysteresis controller is proposed including the method for estimation of leakage inductance, Ls. For frequencies of operation less than 25 Hz, the rotor voltage and hence the rotor flux position is computed during the inverter zero voltage space vector using steady state model of IM. For above 25 Hz, active vector period and steady state model of IM is used. The whole rotor flux estimation scheme is dependent on current error space phasor and the steady state motor model, with rotor flux as a reference vector. Since no terminal voltage sensing is involved, dead time effects will not create problem in rotor flux sensing at low frequencies of operation. But appropriate device on-state drop are compensated at low frequencies (below 5 Hz) of operation to achieve a steady state operation up to less than 1 Hz. A constant switching frequency hysteresis current controller is used in inner current control loop for the PWM regulation, with smooth transition of operation to six-step mode operation. A simple Ls estimation based on current error space phasor is also proposed to nullify the deteriorating effect on rotor flux estimation. The parameter sensitivity of the control scheme to changes in the stator resistance Rs is also investigated. The drive scheme is tested up to a low frequency operation less than 1 Hz. The extensive simulation and experiment results are presented to show the proposed scheme’s good dynamic performance extending up to six-step operation. In contrast to vector control, direct torque control (DTC) method requires the knowledge of stator resistance only and thereby decreasing the associated sensitivity to parameters variation and the elimination of speed information. DTC as compared to vector control does not require co-ordinate transformation and PI controller. DTC is easy to implement because it needs only two hysteresis comparators and a lookup table for both flux and torque control. This thesis also investigates the possibilities in improvement of direct torque control scheme for high performance induction motor drive applications. Here, two schemes are proposed based on the direct torque control scheme for IM drive using 12-sided polygonal voltage space vectors for fast torque control. The torque control scheme based on DTC algorithm is proposed using 12-sided polygonal voltage space vector. The basic DTC scheme is used to control the torque. But the IM drive is open-end type. For torque control, the voltage space vectors orthogonal to stator flux vector in 12-sided polygonal space vector structure are used as hexagonal space vector based DTC scheme. The advantages achieved due to 12-sided polygonal space vector are mainly fast torque control and small torque ripple. The fast transient of torque with precise control is achieved using voltage space vector placed with a resolution of ±15. The torque ripple will be less as 6n±1 (n=odd) harmonic torque is totally eliminated from the whole range of PWM modulation. The comparative analysis of proposed 12-sided polygonal voltage space vector based DTC and conventional hexagonal space vector based DTC is also presented. Extensive simulation and experiment results are also presented to show the fast torque control at speeds of operation ranging from 5 Hz to the rated speed. The concept of 12-sided polygonal space vector based DTC is further extended for a variable speed control scheme using estimated fundamental stator voltage for sector identification. The conventional DTC scheme uses stator flux vector for identification of the sector and the switching vector are selected based on this sector information to control stator flux and torque. However, the proposed DTC scheme selects switching vectors based on the sector information of the estimated fundamental stator voltage vector and its relative position with respect to the stator flux vector. The fundamental stator voltage estimation is based on the steady state model of IM and information of synchronous frequency which is derived from computed stator flux using a low pass filter technique. The proposed DTC scheme utilizes the exact position of fundamental stator voltage vector and stator flux vector position to select optimal switching vector for fast control of torque with small variation of stator flux within hysteresis band. The present DTC scheme allows the full load torque control with fast transient response to very low speeds of operation below 5 Hz. The extensive simulation and experiment results are presented to show the fast torque control for speed of operation from zero speed to rated speed. However, the present scheme will have all the advantages of DTC scheme using stator flux vector for sector identification. All the above propositions are first simulated by MATLAB/Simulink and subsequently verified by an experimental laboratory prototype. The proposed control schemes are experimentally verified on a 3.7 kW IM drive. The control algorithms of the sensorless vector control using current error space phasor as well as DTC using 12-sided polygonal voltage space vector are completely implemented on a TI TMS320LF2812 DSP controller platform. These are some of the constituents for chapters 2, 3 and 4 in this thesis. Additionally, the first chapter also covers a brief survey on some of the recent progresses made in the field of sensorless vector control, direct torque control and current hysteresis controller. The thesis concludes with suggestion for further exploration.

Voltage source inverter (VSI) is used to control the speed of an induction motor by applying AC voltage of variable amplitude and frequency. The semiconductor switches in a VSI are turned on and off in an appropriate fashion to vary the output voltage of the VSI. Various pulse width modulation (PWM) methods are available to generate the gating signals for the switches. The process of PWM ensures proper fundamental voltage, but introduces harmonics at the output of the VSI. Ripple in the developed torque of the induction motor, also known as pulsating torque, is a prominent consequence of the harmonic content. The harmonic voltages, impressed by the VSI on the motor, differ from one PWM method to another. Space-vector-based approach to PWM facilitates a large number of switching patterns or switching sequences to operate the switches in a VSI. The switching sequences can be classified as conventional, bus-clamping and advanced bus-clamping sequences. The conventional sequence switches each phase once in a half-carrier cycle or sub-cycle, as in case of sine-triangle PWM, third harmonic injection PWM and conventional space vector PWM (CSVPWM). The bus-clamping sequences clamp a phase to one of the DC terminals of the VSI in certain regions of the fundamental cycle; these are employed by discontinuous PWM (DPWM) methods. Popular DPWM methods include 30 degree clamp PWM, wherein a phase is clamped during the middle 30 degree duration of each quarter cycle, and 60 degree clamp PWM which clamps a phase in the middle 60 degree duration of each half cycle. Advanced bus-clamping PWM (ABCPWM) involves switching sequences that switch a phase twice in a sub-cycle besides clamping another phase. Unlike CSVPWM and BCPWM, the PWM waveforms corresponding to ABCPWM methods cannot be generated by comparison of three modulating signals against a common carrier. The process of modulation in ABCPWM is analyzed from a per-phase perspective, and a computationally efficient methodology to realize the sequences is derived. This methodology simplifies simulation and digital implementation of ABCPWM techniques. Further, a quick-simulation tool is developed to simulate motor drives, operated with a wide range of PWM methods. This tool is used for validation of various analytical results before experimental investigations. The switching sequences differ in terms of the harmonic voltages applied on the machine. The harmonic currents and, in turn, the torque ripple are different for different switching sequences. Analytical expression for the instantaneous torque ripple is derived for the various switching sequences. These analytical expressions are used to predict the torque ripple, corresponding to different switching sequences, at various operating conditions. These are verified through numerical simulations and experiments. Further, the spectral properties are studied for the torque ripple waveforms, pertaining to conventional space vector PWM (CSVPWM), 30 degree clamp PWM, 60 degree clamp PWM and ABCPWM methods. Based on analytical, simulation and experimental results, the magnitude of the dominant torque harmonic with an ABCPWM method is shown to be significantly lower than that with CSVPWM. Also, this ABCPWM method results in lower RMS torque ripple than the BCPWM methods at any speed and CSVPWM at high speeds of the motor. Design of hybrid PWM methods to reduce the RMS torque ripple is described. A hybrid PWM method to reduce the RMS torque ripple is proposed. The proposed method results in a dominant torque harmonic of magnitude lower than those due to CSVPWM and ABCPWM. The peak-to-peak torque in each sub-cycle is analyzed for different switching sequences. Another hybrid PWM is proposed to reduce the peak-to-peak torque ripple in each sub-cycle. Both the proposed hybrid PWM methods reduce the torque ripple, without increasing the total harmonic distortion (THD) in line current, compared to CSVPWM. CSVPWM divides the zero vector time equally between the two zero states of a VSI. The zero vector time can optimally be divided to minimize the RMS torque ripple in each sub-cycle. It is shown that such an optimal division of zero vector time is the same as addition of third harmonic of magnitude 0.25 times the fundamental magnitude to the three-phase sinusoidal modulating signals. ABCPWM applies an active state twice in a sub-cycle, with the active vector time divided equally. Optimal division of active vector time in ABCPWM to minimize the RMS torque ripple is evaluated, both theoretically and experimentally. Compared to CSVPWM, this optimal PWM is shown to reduce the RMS torque ripple significantly over a wide range of speed. The various PWM schemes are implemented on ALTERA CycloneII field programmable gate array (FPGA)-based digital control platform along with sensorless vector control and torque estimation algorithms. The controller generates the gating signals for a 10kVA IGBT-based two-level VSI connected to a 5hp, 400V, 4-pole, 50Hz squirrel-cage induction motor. The induction motor is coupled to a 230V, 3kW separately-excited DC generator.

This thesis is about the development and performance enhancement of an induction motor electric vehicle drive system. The fundamental operation of the induction motor drive hardware and control software are introduced, and the different modulation techniques tested are described. A software simulation package is developed to assist in the control design and analysis of the drive system. Next, to establish the efficiency gains obtained by using space vector modulation in the improved drive system, an inverter with hysteresis current control is compared to the same inverter with space vector modulation in steady state and on separate driving profiles. A method for determining induction motor harmonic losses is introduced and is based on obtaining the phase current harmonics from sampled induction motor stator phase currents obtained. Using a semi-empirical loss model, the induction motor losses are compared between different pulse width modulation control strategies throughout the torque versus speed operating region. Next, several issues related to the robustness of the control design are addressed. To obtain good performance in the actual vehicle, a new method for driveline resonance compensation is developed and proven to work well through simulation and experiment. Lastly, this thesis discusses the development of a new method to compensate for the gain and phase error obtained in the feedback of the d-axis and q-axis stator flux linkages. Improved accuracy of the measured stator flux linkages will be shown to improve the field oriented controller by obtaining a more accurate measurement of the feedback electromagnetic torque. / Master of Science

This thesis deals with modeling, simulation and implementation of Load Commutated SCR based current source Inverter (LCI) fed squirrel cage induction motor drive with sinusoidal voltage and sinusoidal current. In the proposed system, the induction motor is fed by an LCI. A three level diode clamped voltage source inverter (VSI) is connected at the motor terminal with ac chokes connected in series with it. The VSI currents are controlled in such a manner that it injects the reactive current demanded by the induction motor and the LCI for successful commutation of the SCRs in the LCI. Additionally, it absorbs the harmonic frequency currents to ensure that the induction motor draws sinusoidal current. As a result, the nature of the motor terminal voltage is also sinusoidal. The concept of load commutation of the SCRs in the LCI feeding an induction motor load is explained with necessary waveforms and phasor diagrams. The necessity of reactive compensation by the active filter connected at the motor terminal for the load commutation of the thyristors, is elaborated with the help of analytical equations and phasor diagrams. The requirement of harmonic compensation by the same active filter to achieve sinusoidal motor current and motor voltage, is also described. Finally, to achieve the aforementioned induction motor drive, the VA ratings of the active filter (VSI) and the CSI with respect to VA rating of the motor, are determined theoretically. The proposed drive scheme is simulated under idealized condition. Simulation results show good steady state and dynamic response of the drive system. Load commutation of the SCRs in the LCI and the sinusoidal profile of motor current and voltage, have been demonstrated. As in LCI fed synchronous motor drives, a special mode of operation is required to run up the induction motor from standstill. As the SCRs of the LCI are load commutated, they need motor terminal voltages for commutation. At standstill these voltages are zero. So, a starting strategy has been proposed and adopted to start the motor with the aid of the current controlled VSI to accelerate until the motor terminal voltages are high enough for the commutation of the SCRs in the LCI. The proposed drive is implemented on an experimental setup in the laboratory. The IGBT based three level diode clamped VSI has been fabricated following the design of the standard module in the laboratory. A generalized digital control platform is also developed using a TMS320F2407A DSP. Two, three phase thyristor bridges with necessary firing pulse circuits have been used as the phase controlled rectifier and the LCI respectively. Appropriate protection scheme for such a drive is developed and adopted to operate the drive. Relevant experimental results are presented. They are observed to be in good agreement with the simulation results. The effect of capacitors connected at the output of the LCI in the commutation process of the SCRs in the LCI is studied and analyzed. From the analysis, it is understood that the capacitors form a parallel resonating pair with filter inductor and the motor leakage inductance, which results in an undesired oscillation in the terminal voltage during each of the commutation intervals leading to commutation failure. So, in the final system, the capacitors are removed to eliminate any chance of commutation failure of the SCRs in the LCI. It is shown by experiment that the commutation of the SCRs takes place reliably in the absence of the capacitors also. The commutation process is studied and analyzed without the capacitors to understand the motor terminal voltage waveform of the experimental results.

In DC to AC power conversion, voltage source inverters (VSI) based current controllers are usually preferred for today’s high performance AC drive which requires excellent dynamic and steady state performances at different transient and load conditions, with the additional advantages like inherent short circuit and over current protection. Out of different types of current controllers, hysteresis controllers are widely used due to their simplicity and ability to meet the requirements for a high performance AC drives. But the conventional hysteresis controllers suffers from wide variation of PWM switching frequency, overshoot in current errors, sub-harmonic components in the current waveform and non-optimum switching at different operating point of the drive system. To mitigate these problems, particularly to control the switching frequency variation, which is the root cause of all other problems, several methodologies like ramp comparison based controller, predictive current controller, etc. were proposed in the literature. But amplitude and phase offset error in the ramp comparison based controllers and complexities involved in the predictive controllers have limited the use of these controllers. Moreover, these type of controllers, which uses three separate and independently controlled tolerance band (sinusoidal type or adaptive) to control the 3-phase currents, shows limited dynamic responses and they are not simple to implement. To tackle the problem of controlling 3-phase currents simultaneously, space vector based hysteresis current controller is very effective as it combines the current errors of all the three phases as a single entity called current error space vector. It has a single controller’s logic with a hysteresis boundary for controlling this current error space vector. Several papers on space vector based hysteresis controllers for 2-level inverter with constant switching frequency have been published, but the application of the constant switching frequency based hysteresis current controllers for multi¬level inverter fed drive system, has not been addressed properly. Use of multi-level inverter in modern high performance drive for medium and high voltage levels is more prominent because of multi-level’s inherent advantages like good power quality, good electromagnetic compatibility (EMC), better DC link voltage utilization, reduced device voltage rating, so on. Even though some of the earlier works describe three-level space vector based hysteresis current controller techniques, they are specific to the particular level of inverters and does not demonstrate constant switching frequency of operation. This thesis proposes a novel approach where nearly constant switching frequency based hysteresis controller can be implemented for any general n-level inverter and it is also independent of inverter topology. In this work, varying parabolic boundary is used as the hysteresis current error boundary for controlling the current in a multi-level space vector structure. The computation of the parabolic boundary is accomplished offline and all the necessary boundary parameters at different operating points are stored in the look-up tables. The varying parabolic boundary for the multi-level space vector structure depends on the sampled reference phase voltage values which are estimated from stator current error information and then using the equivalent circuit model of induction motors. Here, a mapping technique is adopted to bring down all the three phase references to the inner- most carrier region, which results in mapping any outer triangular structure where tip of the voltage space vector is located, to one of the sectors of the inner most hexagon of the multi-level space vector structure. In this way, the required mapped sector information is easily found out to fix the correct orientation of the parabolic boundary in the space vector plane. This mapping technique simplifies the controller’s logic similar to that of a 2-level inverter. For online identification of the inverter switching voltage vectors constructing the present outer triangle of the multi-level space vector structure, the proposed controller utilizes the sampled phase voltage references. This identification technique is novel and also generic for any n-level inverter structure. This controller is having all the advantages of a space vector based hysteresis current controller and that of a multi-level inverter apart from having a nearly constant switching frequency spectrum similar to that of a voltage controlled space vector PWM (VC-SVPWM). Using the proposed controller, simulation study of a five-level inverter fed induction motor (IM) drive scheme, was carried out using Matlab-Simulink. Simulation study showed that the switching frequency variations in a fundamental cycle and over the entire speed range of the linear modulation region, is similar to that of a VC-SVPWM based multi-level VSI. The proposed hysteresis controller is experimentally verified on a 7.5 kW IM vector control drive fed with a five-level VSI. The proposed current error space vector based hysteresis controller providing nearly constant switching frequency is implemented on a TI TMS320LF2812 DSP and Xilinx XC3S200FT256 FPGA based platform. The three-phase reference currents are generated depending on the frequency command and the controller is tested with the drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and quick transient results of the proposed drive are presented in this thesis. This thesis also proposes another type of hysteresis controller, firstly for 2-level inverter and then for general n-level multi-level inverter, which eliminates the parabolic boundary and replaces it with a boundary which is computed online and does not use any look up table for boundary selection. The current error boundary for the proposed hysteresis controller is computed online in a very simple way, using the information of estimated fundamental stator voltages along α and β axes of space vector plane. The method adopted for the proposed controller to compute the boundary does not involve any complicated computations and it selects the optimal vector for switching when current error space vector crosses the boundary. This way adjacent voltage vector switching similar to VC-SVPWM can be ensured. For 2-level inverter, it precisely determines the sector, in which reference voltage vector is present. In multi-level inverter, this controller also finds out the mapped sector information using the same mapping techniques as explained in the first part of this thesis. In both 2-level and multi-level inverter, the proposed controller does not use any look up table for finding individual voltage vector switching times from the estimated voltage references. These switching times are used for the computation of hysteresis boundary for individual vectors. Thus the hysteresis boundary for individual vectors is exactly calculated and the boundary is similar to that of VC-SVPWM scheme for the respective levels of inverter. In the present scheme, the phase voltage harmonic spectrum is very close to that of a constant switching frequency VC-SVPWM inverter. In this thesis, at first, the proposed on line boundary computation scheme is implemented for a 2-level inverter based controller for the initial study, so that it can be executed as fast as 10 µs in a DSP platform, which is required for accurate current control. Then the same algorithm of 2-level inverter is extended for multi-level inverter with the additional logic for online identification of nearest switching voltage vectors (also used in the parabolic boundary case) for the present sampling interval. Previously mentioned mapping technique for multi-level inverter, is also implemented here to bring down the phase voltage references to the inner-most carrier region to realize the multi-level current control strategy equivalent to that of a 2-level inverter PWM current control. Simulation study to verify the steady state as well as transient performance of the proposed controller for both 2-level as well as five-level VSI fed IM drive is carried out using Simulink tool box of MATLAB Simulation Software. The proposed hysteresis controllers are experimentally verified on a 7.5 kW IM vector control drive fed with a two-level VSI and five-level VSI separately. The proposed current error space vector based hysteresis controller providing nearly constant switching frequency profile for phase voltage is implemented on the TI TMS320LF2812 DSP and Xilinx XC3S200FT256 FPGA based platform. The three-phase reference currents are generated depending on the frequency command and the proposed hysteresis controllers are tested with drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and transient results of the proposed drive are also presented for different operating conditions, through the simulation study followed by experimental verifications. Even though the simulation and experimental verifications are done on a 5-level inverter to explain the proposed hysteresis controller, it can be easily implemented for any general n-level inverter, as described in this thesis.

Les travaux développés durant cette thèse concernent la détection et l'identification des défauts simples et multiples d'ouverture des transistors dans un convertisseur statique associé à une machine asynchrone. Pour aborder cette problématique, nous avons commencé par l'analyse des potentialités, des faiblesses et des incertitudes des techniques qui ont initiés notre démarche. Ensuite, nous avons présenté deux méthodologies permettant d'analyser les performances du moteur asynchrone en présence des défauts dans une ou plusieurs cellules de commutation. Cette étude préliminaire nous a permis ainsi de proposer deux nouvelles stratégies de diagnostic sans référence basées sur l'approche signal. Les signaux électriques (courants ou tensions) disponibles à la sortie du convertisseur statique sont utilisés pour alimenter le processus de diagnostic. La première stratégie retenue est basée sur l'analyse qualitative des tensions de sortie entre phases du convertisseur et des signaux de commande appliqués aux transistors pendant les instants de commutation. Grâce à une représentation instantanée de ces grandeurs, à l'échelle de la période de découpage, nous avons pu mettre en évidence des caractéristiques favorables à la détection des défauts simples et multiples d'ouverture des transistors. L'implémentation pratique de cette première approche a été réalisée au moyen d'une technologie analogique permettant ainsi de minimiser le temps de retard à la détection jusqu'à quelques dizaines de microsecondes. / The main goal of this thesis concerns the detection and identification of simple and multiple open-circuit faults in voltage source inverters (VSIs)-fed induction motor drives. In first step, the potentialities, the weaknesses as well as the uncertainties of the previously published works have been discussed. The second step was dedicated to the study of the inverter faults impact on the induction motor. For this purpose, we have proposed two methodologies permitting the characterization of the electromagnetic torque behaviour as well as the electric variables of the induction motor under the open- and short-circuit faults. These preliminary studies allowed to propose two novel signal-based approaches for open-circuit fault diagnosis in voltage source inverter. The measured outputs inverter voltages and currents have been used as the input quantities for the fault detection and identification (FDI) process. The first approach consists in analyzing the pulse-width modulation (PWM) switching signals and the line-to-line voltage levels during the switching times, under both healthy and faulty operating conditions. For this purpose, we have adopted an instantaneous representation of these variables, which permits their analysis over one switching period. The fault diagnosis scheme is achieved using simple analog device. This circuit allows an accurate single and multiple faults diagnosis, and a minimization of the fault detection time which becomes about a few tens of microseconds.

Voltage source inverter (VSI) fed induction motors are increasingly used in industrial and transportation applications as variable speed drives. However, VSIs generate non-sinusoidal voltages and hence result in harmonic distortion in motor current, motor heating, torque pulsations and increased acoustic noise. Most of these undesirable effects can be reduced by increasing the switching frequency of the inverter. This is not necessarily true for acoustic noise. Acoustic noise does not decrease monotonically with increase in switching frequency since the noise emitted depends on the proximity of harmonic frequencies to the motor resonant frequencies. Also there are practical limitations on the inverter switching frequency on account of device rating and losses. The switching frequency of many inverters often falls in the range 2 kHz - 6 kHz where the human ear is highly sensitive. Hence, the acoustic noise emission from the motor drive is of utmost important. Further, the acoustic noise emitted by the motor drive is known to depend on the waveform quality of the voltage applied. Hence, the acoustic performance varies with the pulse width modulation (PWM) technique used to modulate the inverter, even at the same modulation index. Therefore a comprehensive study on the acoustic noise aspects of induction motor drive is required. The acoustic noise study of the motor drive poses multifaceted challenges. A simple motor model is sufficient for calculation of total harmonic distortion (THD). A more detailed model is required for torque pulsation studies. But the motor acoustic noise is affected by many other factors such as stator winding distribution, space harmonics, geometry of stator and rotor slots, motor irregularities, structural issues controlling the resonant frequency and environmental factors. Hence an accurate model for acoustic noise would have to be very detailed and would span different domains such as electromagnetic fields, structural engineering, vibration and acoustics. Motor designers employ such detailed models along with details of the materials used and geometry to predict the acoustic noise that would be emitted by a motor and also to design a low-noise motor. However such detailed motor model for acoustic noise purposes and the necessary material and constructional details of the motor are usually not available to the user. Also, certain factors influencing the acoustic noise change due to wear and tear during the operational life of the motor. Hence this thesis takes up an experimental approach to study the acoustic noise performance of an inverter-fed induction motor at any stage of its operating life. A 10 kVA insulated gate bipolar transistor (IGBT) based inverter is built to feed the induction motor; a 6 kW and 2.3 kW induction motors are used as experimental motors. A low-cost acoustic noise measurement system is also developed as per relevant standards for measurement and spectral analysis of the acoustic noise emitted. For each PWM scheme, the current and acoustic noise measurements are carried out extensively at different carrier frequencies over a range of fundamental frequencies. The main cause of acoustic noise of electromagnetic origin is the stator core vibration, which is caused by the interaction of air-gap fluxes produced by fundamental current and harmonic currents. In this thesis, an experimental procedure is suggested for the acoustic noise characterization of an induction motor inclusive of determination of resonant frequencies. Further, based on current and acoustic noise measurements, a vibration model is proposed for the stator structure. This model is used to predict the acoustic noise pertaining to time harmonic currents with reasonable accuracy. Literature on motor acoustic noise mainly focuses on sinusoidal PWM (SPWM), conventional space vector PWM (CSVPWM) and random PWM (RPWM). In this thesis, acoustic noise pertaining to two bus-clamping PWM (BCPWM) schemes and an advanced bus-clamping PWM (ABCPWM) scheme is investigated. BCPWM schemes are mainly used to reduce the switching loss of the inverter by clamping any of the three phases to DC rail for 120◦ duration of the fundamental cycle. Experimental results show that these BCPWM schemes reduce the amplitude of the tonal component of noise at the carrier frequency, compared to CSVPWM. Experimental results with ABCPWM show that the overall acoustic noise produced by the motor drive is reduced at low and medium speeds if the switching frequency is above 3 kHz. Certain spread in the frequency spectrum of noise is also seen with both BCPWM and ABCPWM. To spread the acoustic noise spectrum further, many variable-frequency PWM schemes have been suggested by researchers. But these schemes, by and large, increase the current total harmonic distortion (THD) compared to CSVPWM. Thus, a novel variable-frequency PWM (VFPWM) method is proposed, which offers reduced current THD in addition to uniformly spread noise spectrum. Experimental results also show spread in the acoustic noise spectrum and reduction in the dominant noise components with the proposed VFPWM. Also, the current THD is reduced at high speeds of the motor drive with the proposed method.

Conventional 2-level inverters have been quite popular in industry for drives applications. It used pulse width modulation techniques to generate a voltage waveform with high quality. For achieving this, it had to switch at high frequencies and also the switching is between 0 and Vdc. Also additional LC filters are required before feeding to a motor. 3-phase IM is the work horse of the industry. Several speed control techniques have been established namely the V/f control technique and for high performance, vector control is adopted. An electric drive system comprises of a rectifier, inverter, a motor and a load. each module is a topic by itself. This thesis work discusses the novel inverter topologies to overcome the demerits of a conventional 2-level inverter or even the basic multilevel topologies, for an electric drive. The word ‘multilevel’ itself signifies that inverter can generate more than two levels. The idea was first originated by Nabae, Takahashi and Akagi to bring an additional voltage level so that the waveform becomes a quasi square wave. This additional voltage level brought additional benefits in terms of reduced dv/dt and requirement of low switching frequency. But this was not without any cost. The inverter structure is slightly more complicated than a 2-level and also required more devices. But the advantage it gave was superior enough to such an extent that the above topology (popularly known as NPC) has become quite popular in industry. This topology was later modified to equalize the semiconductor losses among switches by replacing the clamping diodes with controllable switches and such topologies are popularly known as Active NPCs (ANPCs) because of the replacement of diodes with active switches. 3-level flying capacitors were then introduced where the additional voltage level is provided using charged capacitors. But this capacitor voltage has to be maintained at its nominal value during the inverter operation. An additional floating capacitor, which is an electrolytic capacitor is needed for this. Increasing the number of electrolytic capacitors reduces the reliability of the inverter drive since they are the weakest link in any inverters and its count has to be kept to the minimum. By using a H-bridge cell in each of the three phases, three voltage levels can be easily obtained.This is commonly known as Cascaded H-bridge (CHB) multilevel inverter. The above three topologies have been discussed with respect to generation of three pole voltage levels and these topologies are quite suited also. A higher number of voltage levels will reduce the switching frequency even lesser and also the dv/dt. On increasing the number of levels further and further, finally the inverter need not do any PWM switching and just generating the levels is sufficient enough for a good quality waveform and also low dv/dt. But when the above topologies are scaled for more than three voltage levels, all of them suffer serious drawbacks which is briefly discussed below. The diode clamped inverter (known as NPC if it is 3-level), when extended to more than three levels suffers from the neutral point balancing issue and also the count of clamping diodes increase drastically. FC inverters, when extended beyond 3-level, the number of electrolytic capacitors increases and also balancing of these capacitors to their nominal voltages becomes complicated. In the case of multilevel CHB, when extended beyond 3-level, the requirement of isolated DC sources also increases. To generate isolated supplies, phase shifting transformer and 8, 12 or 24 pulse diode rectifier is needed which increases the weight , size and cost of the drive. Therefore its application is limited. In this thesis, the aim is to develop a novel method to develop a multilevel inverter without the drawbacks faced by the basic multilevel topologies when scaled for higher number of voltage levels. This is done through stacking the basic or hybrid combination of these basic multilevel topologies through selector switches. This method is experimentally verified by stacking two 5-level inverters through a 2-level selector switch (whose switching losses can be minimized through soft cycle commutation). This will generate nine levels.Generating 9-levels through scaling the basic topologies is disadvantageous, the comparison table is provided in the thesis. This is true for any higher voltage level generation. Each of the above 5-level inverter is developed through cascading an FC with a capacitor fed H-bridge. The device count can be reduced by making the FC-CHB module common to the selector switches by shifting the selector switches between the DC link and the common FC-CHB module. Doing so, reduces the modular feature of the drive but the device count can be reduced. The FFT plot at different frequencies of operation and the switching losses of the different modules-FC, CHB and the selector switches are also plotted for different frequencies of operation. The next step is to check whether this method can be extended to any number of stackings for generation of more voltage levels. For this, a 49-level inverter is developed in laboratory by stacking three 17-level inverters. Each of the 17-level inverter is developed by cascading an FC with three CHBs. When there are 49 levels in the pole voltage waveform, there is no need to do any regular PWM since the output waveform will be very close to a sine wave even without any PWM switching. The technique used is commonly known in literature as Nearest Level Control (NLC). This method of stacking and cascading has the advantage that the FC and the CHB modules now are of very low voltages and the switching losses can be reduced. The switching losses of the different modules are calculated and plotted for different operating frequencies in the thesis. To reduce the voltages of the modules further, a 6-phase machine has been reconfigured as a 3-phase machine, the advantage being that now the DC link voltage requirement is half of that needed earlier for the same power. This further reduces voltages of the modules by half and this allows the switches to be replaced with MOSFETs, improving the efficiency of the drive. This topology is also experimentally verified for both steady state and transient conditions. So far the research focussed on a 3-phase IM fed through a stacked MLI. It can be observed that a stacked MLI needs as many DC sources as the number of stackings. A 6-phase machine apart from reduced DC link voltage requirement, has other advantages of better fault tolerant capability and better space harmonics. They are serious contenders for applications like ship propulsion, locomotive traction, electric vehicles, more electric aircraft and other high power industrial applications. Using the unique property of a 6-phase machine that its opposite windings always draw equal and opposite current, the neutral point (NP) (formed as a result of stacking two MLIs) voltage can be balanced. It was observed that the net mid point current drawn from the mid point can be made zero in a switching interval. It was later observed that with minimal changes, the mid point current drawn from the NP can be made instantaneously zero and the NP voltage deviation is completely arrested and the topology needs only very low capacity series connected capacitors energized from a single DC link. This topology is also experimentally verified using the stacked 9-level inverter topology discussed above but now for 6-phase application and experimental results are provided in the thesis. Single DC link enables direct back to back conversion and power can be fed back to the mains at any desired power factor. All the experimental verification is done on a DSP (TMS320F28335) and FPGA (Spartan 3 XCS3200) platform. An IM is run using V/f control scheme and the above inverter topologies are used to drive the motor. The IGBTs used are SKM75GB123D for the stacked 9-level inverter in the 3-phase and 6-phase experiments. For the 49-level inverter experiment, MOSFETs-IRF260N were used. Both steady state and transient results ensure that the proposed inverter topologies are suitable for high power applications.

Multilevel inverters play a major role in the modern day medium and high power energy conversion processes. The classic two level voltage source inverter generates PWM pole voltage output having two levels with strong fundamental component and harmonics centered around the switching frequency and its multiples. With higher switching frequency, its components can be easily filtered and results in better Total harmonic distortion (THD) output voltage and current. But with higher switching frequency, switching loss of power devices increases and electromagnetic interferences also increases. Also in two level inverter, pole voltage switches between zero and DC bus volt-age Vdc. This switching results in high dv=dt and causes EMI and increased stress on the motor winding insulation. The attractive features of multilevel inverters compared to a two level inverter are reduced switching frequency, reduced switching loss, improved volt-age and current THD, reduced dv=dt, etc. Because of these reasons, multilevel invertersultilevelinvertersplayamajorroleinthemoderndaymediumandhighpower find application in electric motor drives, transmission and distribution of power, transportation, traction, distributed generation, renewable energy systems like photo voltaic, hydel power, energy management, power quality, electric vehicle applications, etc. AC motor driven applications are consuming the significant part of the generated electrical energy (more than 60%) around the world. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low with lower out-put voltage dv=dt. Also by using multilevel inverters, the common mode voltage (CMV) switching can be made zero and associated motor bearing failure can be mitigated. For multilevel inverter topologies, as the number of level increases, the power circuit becomes more complex by the increase in the number of DC power supplies, capacitors, switching devices and associated control circuitry. The main focus of development in multilevel inverter for medium and high power applications is to obtain an optimized number of voltage levels with reduced number of switching devices, capacitors and DC power sources. In this thesis, a new hybrid seven level inverter topology with a single DC supply is proposed with reduced switch count. The inverter is realized by cascading two three level flying capacitor inverters with a half bridge module. Compared to the conventional seven level inverter topologies, the proposed inverter topology uses lesser number of semiconductor devices, capacitors and DC power supplies for its operation. For this topology, capacitor voltage balancing is possible for entire modulation range irrespective of the load power factor. Also capacitor voltage can be controlled over a switching cycle and this result in lowering the capacitor sizing for the proposed topology. A simple hysteresis band based capacitor voltage balancing scheme is implemented for the inverter topology. For a voltage source inverter fed induction motor drive system, the inverter pole voltage is the sum of motor phase voltage and common mode voltage. In induction motors, there exists a parasitic capacitance between stator winding and stator iron, and between stator winding and rotor iron. Common mode voltage with significant magnitude and high frequency switching causes leakage current through these parasitic capacitances and motor bearings. This leakage current can cause ash over of bearing lubricant and corrosion of ball bearings, resulting in an early mechanical failure of the drive system. In this thesis, analysis of extending the linear modulation range of a general n-level inverter by allowing reduced magnitude of common mode voltage (CMV) switching (only Vdc/18) is presented. A new hybrid seven level inverter topology, with a single DC supply and with reduced common mode voltage (CMV) switching is presented in this thesis for the first time. Inverter is operated with zero CMV for modulation index less than 86% and is operated with a CMV magnitude of Vdc/18 to extend the linear modulation range up to 96%. Experimental results are presented for zero CMV operation and for reduced common voltage operation to extend the linear modulation range. A capacitor voltage balancing algorithm is designed utilizing the pole voltage redundancies of the inverter, which works for every sampling instant to correct the capacitor voltage irrespective of load power factor and modulation index. The capacitor voltage balancing algorithm is tested for different modulation indices and for various transient conditions, to validate the proposed topology. In recent years, model predictive control (MPC) using the system model has proved to be a good choice for the control of power converter and motor drive applications. MPC predicts system behavior using a system model and current system state. For cascaded multilevel inverter topologies with a single DC supply, closed loop capacitor voltage control is necessary for proper operation. This thesis presents zero and reduced common mode voltage (CMV) operation of a hybrid cascaded multilevel inverter with predictive capacitor voltage control. For the presented inverter topology, there are redundant switching states for each inverter voltage levels. By using these switching state redundancies, for every sampling instant, a cost function is evaluated based on the predicted capacitor voltages for each phase. The switching state which minimizes cost function is treated as the best and is switched for that sampling instant. The inverter operates with zero CMV for a modulation index upto 86%. For modulation indices from 86% to 96% the inverter can operate with reduced CMV magnitude ( Vdc/18) and reduced CMV switching frequency using the new space-vector PWM (SVPWM) presented herein. As a result, the linear modulation range is increased to 96% as compared to 86% for zero CMV operation. Simulation and experimental results are presented for the inverter topology for various steady state and transient operating conditions by running an induction motor drive with open loop V/f control scheme. The operation of a two level inverter in the over-modulation region (maximum peak phase fundamental output of inverter is greater than 0:577Vdc) results in lower order harmonics in the inverter output voltage. This lower order harmonics (mainly 5th, 7th, 11th, and 13th) causes electromagnetic torque ripple in motor drive applications. Also these harmonics causes extra losses and adversely affects the efficiency of the drive system. Also inverter control becomes non linear and special control algorithms are required for inverter operation in the over modulation region. In conventional schemes, maximum fundamental output voltage possible is 0:637Vdc. In that case inverter is operated in a square wave mode, also called six-step mode. This operation results in high dv=dt for the inverter output voltage. With multilevel inverters also, the inverter operation with peak phase fundamental output voltage above 0:577Vdc results in lower order harmonics in the inverter output voltage and results in electromagnetic torque pulsation. In this thesis, a new space vector PWM (SVPWM) method to extend the linear modulation range of a cascaded five level inverter topology with a single DC supply is presented. Using this method, the inverter can be controlled linearly and the peak phase fundamental output voltage of the inverter can be increased from 0:577Vdc to 0:637Vdc without increasing the DC bus voltage and without exceeding the induction motor voltage rating. This new technique makes use of cascaded inverter pole voltage redundancy and property of the space vector structure for its operation. Using this, the induction motor drive can be operated till the full speed range (0 Hz to 50 Hz) with the elimination of lower order harmonics in the phase voltage and phase current. The ve level topology presented in this thesis is realized by cascading a two level inverter and two full bridge modules with floating capacitors. The inverter topology and its operation for extending the modulation range is analyzed extensively. Simulation and experimental results for both steady state and dynamic operating conditions are presented. Zero common mode voltage (CMV) operation of multilevel inverters results in reduced DC bus utilization and reduced linear modulation range. In this thesis two reduced CMV SVPWM schemes are presented to extend the linear modulation range by allowing reduced CMV switching. But using these SVPWM schemes the peak phase fundamental output voltage possible is only 0:55Vdc in the linear region. In this thesis, a method to extend the linear modulation range of a CMV eliminated hybrid cascaded multilevel inverter with a single DC supply is presented. Using this method peak fundamental voltage can be increased from 0 to 0:637Vdc with zero CMV switching inside the linear modulation range. Also inverter can be controlled linearly for the entire modulation range. Also, various PWM switching sequences are analyzed in this thesis and the PWM sequence which gives minimum current ripple is used for the zero CMV operation of the inverter. The inverter topology with single DC supply is realized by cascading a two level inverter with two floating capacitor fed full bridge modules. Simulation and experimental results for steady state and dynamic operating conditions are presented to validate the proposed method. A three phase, 400 V, 3.7 kW, 50 Hz, two-pole induction motor drive with the open-loop V/f control scheme is implemented in the hardware for testing proposed inverter topology and proposed SVPWM algorithms experimentally. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V IGBT half-bridge modules (SKM-75GB-12T4). Optoisolated gate drivers with de-saturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation, TMS320F28335 DSP is used as the main controller and Xilinx SPARTAN-3 XC3S200 FPGA as the PWM signal generator with dead time of 2.5 s. Level shifted carrier-based PWM algorithm is implemented for the normal inverter operation and zero CMV operation. From the PWM algorithm, information about the pole voltage levels to be switched can be obtained for each phase. In the sampling period, for capacitor voltage balancing of each phase, the DSP selects a switching state using the capacitor voltage information, current direction and pole voltage data for each phase. This switching state information along with the PWM timing data is sent to an FPGA module. The FPGA module generates the gating signals with a dead time of 2.5 s for the gate driver module for all the three phases by processing the switching state information and PWM signals for the given sampling period. For fundamental frequencies above 10Hz, synchronous PWM technique was used for testing the inverter topology. For modulation frequencies 10Hz and below, a constant switching frequency of 900 Hz was used. Various steady state and transient operation results are provided to validate the proposed inverter topology and the zero and reduced CMV operation schemes and extending the linear modulation scheme presented in this thesis. With the advantages like reduced switch count, single DC supply requirement, zero and reduced CMV operation, extension of linear modulation range, linear control of induction motor over the entire modulation range with zero CMV, lesser dv=dt stresses on devices and motor phase windings, lower switching frequency, inherent capacitor balancing, the proposed inverter power circuit topologies, and the SVPWM methods can be considered as good choice for medium voltage, high power motor drive applications.

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