No description available.

As Moore's law continues to progress, it is becoming increasingly difficult for hardware designers to fully utilize the increasing number of transistors available semiconductor devices including FPGAs. This design productivity gap must be addressed to allow designs to take full advantage of the increased logic density that results from rising transistor density. The reuse of previously developed and verified intellectual property (IP) is one approach that has claimed to narrow the design productivity gap. Reuse, however, has proved difficult to realize in practice because of the complexity of IP and the reluctance of designers to reuse IP that they do not understand. This thesis proposes to narrow the design productivity gap for FPGAs by simplifying the reuse problem by encapsulating IP with extra machine-readable information or meta-data. This meta-data simplifies reuse by providing a language independent format for composing complex systems, providing a parameter representation system, defining high-level data types for FPGA IP, and allowing arbitrary IP to be described as actors in the homogeneous synchronous dataflow model of computation.This work implements meta-data in XML and presents two XML schemas that enable reuse. A new XML schema known as CHREC XML is presented as well as extensions that enable IP-XACT to be used to describe FPGA dataflow IP. Two tools developed in this work are also presented that leverage meta-data to simplify reuse of arbitrary IP. These tools simplify structural composition of IP, allow designers to manipulate parameters, check and validate high-level data types, and automatically synthesize control circuitry for dataflow designs. Productivity improvements are also demonstrated by reusing IP to quickly compose software radio receivers.

No description available.

This paper examines the relationship between research and development (R&D) expenditures under International Financial Reporting Standards (IFRS) and firms’ innovation, proxied by future patent counts and patent citations. Accounting for R&D is a major difference between IFRS and generally accepted accounting principles in the United States (US GAAP). The difference is that certain development costs can be treated as assets under IFRS, but all R&D expenditures are expensed under US GAAP. This difference in the accounting treatment is grounded in the conceptual question of whether R&D expenditures provide future benefits, consistent with the definition of an asset, or whether the benefits are so uncertain that they are treated as the consumption of resources, consistent with the definition of an expense. If R&D expenditures provide future benefits, they are expected to be associated with future patents and citations. Capitalized development costs should exhibit a stronger association as they meet the criteria to be assets, expecting to provide future benefits. Expensed R&D can also be associated with patents and patent citations as these expenditures may also lead to patents and patent citations. As expensed R&D relates to expenditures in the research stage or those development costs that do not meet the criteria to be capitalized, the association should be weaker. Therefore, this paper examines the association between R&D expenditures that are expensed and those that are capitalized under IFRS with patents and patent citations as future benefits.Using a hand-collected sample of high-tech firms in European Union from 2012 to 2018, this paper finds economically and statistically significant different associations between capitalized development costs and expensed R&D and a firms’ innovation, as proxied by future patents and patent citations. Using median effects, the association between one million euros investment in firms’ capitalized development costs and patent counts (citations) is 200% or more than the association between one million euro’s expensed R&D and patent counts (citations). This paper is one of the first to examine the relationship between R&D capitalization under IFRS and firms’ innovation, as measured by future patent counts and patent citations. This paper contributes to the literature on R&D capitalization by identifying the fundamental difference in the association between capitalized development costs and expensed R&D and innovation. Further, this paper contributes to our understanding of the accounting for R&D, and the different treatment between US GAAP and IFRS by finding that capitalized development costs display a different association from expensed R&D. / Business Administration/Accounting

No description available.

No description available.

No description available.

No description available.

No description available.

The complexity of chip design has been exponentially rising, resulting in increased complexity and costs in chip verification. This rise in complexity results in increased time to market and increases risks of chip in fabrication, that can be catastrophic and result in major losses. For this reason, it is necessary for companies to ensure the verification testbenches used are predictable and reusable. The SystemVerilog language is a Hardware Verification Language that adopts the object-oriented principles. It is a highly suitable language for verification environments as it offers functional coverage, constrained random testing and assertions. The Universal Verification Methodology package consists of SystemVerilog libraries used for the industry grade verification environments. The Universal Verification Methodology takes advantages of features and design patterns from software engineering in general and Object-oriented Programming in particular, such as data hiding to raise the level of abstraction, generic programming to increase reusability, polymorphism for inter-operability, etc. There is a lot of pressure on the performance of today’s verification teams. This thesis develops a functional verification environment for the Avalon Streaming Interface while incorporating design practices that make the environment far more robust and reusable. The study focuses on instilling properties in the Verification environment that help save verification time. / Komplexiteten i chipdesign har ökat exponentiellt, vilket resulterat i ökad komplexitet och ökade kostnader vid chipverifiering. Denna ökning i komplexitet resulterar i längre tid till marknaden och ökar riskerna vid tillverkning av kiselchip, vilket kan vara katastrofalt och leda till stora förluster. Av denna anledning är det nödvändigt för företag att säkerställa att de testbänkar som används vid verifiering är förutsägbara och återanvändbara. Språket SystemVerilog är ett verifieringsspråk för maskinvara med objektorienterade egenskaper. Det är mycket lämpligt i verifieringsmiljöer eftersom det erbjuder funktionell täckning, målmässigt begränsade slumpmässiga tester samt påstenden i form av assertions. Biblioteket Universal Verification Methodology består av SystemVerilog-funktioner som används vid verifiering i industrimiljöer. Den universella verifieringsmetoden drar fördel av funktioner och designmönster från mjukvaruteknik i allmänhet och Objektorienterad Programmering i synnerhet, genom att gömma data för att höja abstraktionsnivån, generisk programmering för att öka återanvändbarheten, polymorfism för interoperabilitet, etc. Det är mycket press på prestandan för dagens verifieringslag. Denna avhandling utvecklar en funktionell verifieringsmiljö för ett Avalon Streaming Interface samtidigt som det integrerar designpraxis vilket gör miljön mycket mer robust och återanvändbar. Studien fokuserar på att inkludera egenskaper i verifieringsmiljön vilka hjälper till att spara verifieringstid.