The development and implementation of a metal gate technology (alloy, compound, or silicide) into metal-oxide-semiconductor field effect transistors (MOSFETs) is necessary to extend the life of planar CMOS devices and enable further downscaling. This thesis examines possible metal gate materials for improving the performance of the gate stack and discusses process integration as well as improved electrical and physical measurement methodologies, tested on capacitor structures and transistors. By using reactive PVD and gradually increasing the N2/Ar flow ratio, it was found that the work function (on SiO2) of the TiNx and ZrNx metal systems could be modulated ~0.7 eV from low near nMOS work functions to high pMOS work functions. After high-temperature anneals corresponding to junction activation, both metals systems reached mid-gap work function values. The mechanisms behind the work function changes are explained with XPS data and discussed in terms of metal gradients and Fermi level pinning due to extrinsic interface states. A modified scheme for improved Fowler-Nordheim tunnelling is also shown, using degenerately doped silicon substrates. In that case, the work functions of ALD/PVD TaN were accurately determined on both SiO2 and HfO2 and benchmarked against IPE (Internal Photoemission) results. KFM (Kelvin Force Microscopy) was also used to physically measure the work functions of PVD TiN and Mo deposited on SiO2; the results agreed well with C-V and I-V data. Finally, an appealing combination of novel materials is demonstrated with ALD TiN/Al2O3/HfAlOx/Al2O3/strained-SiGe surface channel pMOS devices. The drive current and transconductance were measured to be 30% higher than the Si reference, clearly demonstrating increased mobility and the absence of polydepletion. Finally, using similarly processed transistors with Al2O3 dielectric instead, low-temperature water vapour annealing was shown to improve the device characteristics by reducing the negative charge within the ALD Al2O3.

The demands for faster, smaller, and less expensive electronic equipments are basically the driving forces for improving the speed and increasing the packing density of microelectronic components. Down-scaling of the devices is the principal method to realize these requests. For future CMOS devices, new materials are required in the transistor structure to enable further scaling and improve the transistor performance. This thesis focuses on novel metal gate and high-κ dielectric materials for future CMOS technologies. Specifically, TiN and ZrN gate electrode materials were studied with respect to work function and thermal stability. High work function, suitable for pMOS transistors, was extracted from both C-V and I-V measurements for PVD and ALD TiN in TiN/SiO2/Si MOS capacitor structures. ZrNx/SiO2/Si MOS capacitors exhibited n-type work function when the low-resistivity ZrNx was deposited at low nitrogen gas flow. Further, variable work function by 0.6 eV was achieved by reactive sputter depositing TiNx or ZrNx at various nitrogen gas flow. Both metal-nitride systems demonstrate a shift in work function after RTP annealing, which is discussed in terms of Fermi level pinning due to extrinsic interface states. Still, the materials are promising in a gate last process as well as show potential as complementary gate electrodes. The dielectric constant of as-deposited (Ta2O5)1-x(TiO2)x thin films is around 22, whereas that of AlN is about 10. The latter is not dependent on the degree of crystallinity or on the measurement frequency up to 10 GHz. Both dielectrics exhibit characteristics appropriate for integrated capacitors. Finally, utilization of novel materials were demonstrated in strained SiGe surface-channel pMOSFETs with an ALD TiN/Al2O3 gate stack. The transistors were characterized with standard I-V, charge pumping, and low-frequency noise measurements. Correlation between the mobility and the oxide charge was found. Improved transistor performance was achieved by conducting low-temperature water vapor annealing, which reduced the negative charge in the Al2O3.

<p>Challenges with integrating high-κ gate dielectric,retrograde Si_1-xGe_xchannel and silicided contacts in future CMOStechnologies are investigated experimentally and theoreticallyin this thesis. ρMOSFETs with either Si or strained Si_1-xGex surface-channel and different high-κgate dielectric are examined. Si_1-xGex ρMOSFETs with an Al₂O₃/HfAlO_x/Al₂O₃nano-laminate gate dielectric prepared by means ofAtomic Layer Deposition (ALD) exhibit a great-than-30% increasein current drive and peak transconductance compared toreference Si ρMOSFETs with the same gate dielectric. Apoor high-κ/Si interface leading to carrier mobilitydegradation has often been reported in the literature, but thisdoes not seem to be the case for our Si ρMOSFETs whoseeffective mobility coincides with the universal hole mobilitycurve for Si. For the Si_1-xGe_xρMOSFETs, however, a high density ofinterface states giving riseto reduced carrier mobility isobserved. A method to extract the correct mobility in thepresence of high-density traps is presented. Coulomb scatteringfrom the charged traps or trapped charges at the interface isfound to play a dominant role in the observed mobilitydegradation in the Si_1-xGe_xρMOSFETs.</p><p>Studying contacts with metal silicides constitutes a majorpart of this thesis. With the conventional device fabrication,the Si_1-xGe_xincorporated for channel applications inevitablyextends to the source-drain areas. Measurement and modelingshow that the presence of Ge in the source/drain areaspositively affects the contact resistivity in such a way thatit is decreased by an order of magnitude for the contact of TiWto p-type Si_1-xGe_x/Si when the Ge content is increased from 0 to 30at. %. Modeling and extraction of contact resistivity are firstcarried out for the traditional TiSi₂-Si contact but with an emphasis on the influenceof a Nb interlayer for the silicide formation. Atwo-dimensional numerical model is employed to account foreffects due to current crowding. For more advanced contacts toultra-shallow junctions, Ni-based metallization scheme is used.NiSi_1-xGex is found to form on selectively grown p-typeSi_1-xGe_xused as low-resistivity source/drain. Since theformed NiSi1-xGex with a specific resistivity of 20 mWcmreplaces a significant fraction of the shallow junction, athree-dimensional numerical model is employed in order to takethe complex interface geometry and morphology into account. Thelowest contact resistivity obtained for our NiSi_1-xGe_x/p-type Si_1-xGe_xcontacts is 5´10^-8Ωcm², which satisfies the requirement for the 45-nmtechnology node in 2010.</p><p>When the Si_1-xGe_xchannel is incorporated in a MOSFET, it usuallyforms a retrograde channel with an undoped surface region on amoderately doped substrate. Charge sheet models are used tostudy the effects of a Si retrograde channel on surfacepotential, drain current, intrinsic charges and intrinsiccapacitances. Closed-form solutions are found for an abruptretrograde channel and results implicative for circuitdesigners are obtained. The model can be extended to include aSi_1-xGe_xretrograde channel. Although the analytical modeldeveloped in this thesis is one-dimensional for long-channeltransistors with the retrograde channel profile varying alongthe depth of the transistor, it should also be applicable forshort-channel transistors provided that the short channeleffects are perfectly controlled.</p><p><b>Key Words:</b>MOSFET, SiGe, high-k dielectric, metal gate,mobility, charge sheet model, retrograde channel structure,intrinsic charge, intrinsic capacitance, contactresistivity.</p>

La gravure chimique par voie humide des matériaux est toujours utilisée dans certaines étapes spécifiques des procédés de fabrication de transistors pour la microélectronique. Cette gravure est effectuée en présence de masques de résine photosensible, qui définissent les zones à protéger de l'attaque chimique. Une des difficultés rencontrées lors de cette étape technologique est la dégradation du masque en résine et de l'interface résine/matériau à graver, qui entraine un endommagement du matériau sous-jacent. L'objectif de cette thèse est d'étudier les dégradations occasionnées lors de la gravure humide par une solution chimique de type SC1 (NH4OH/H2O2/ H2O) de la grille métallique TiN / Al / TiN d'un transistor pMOS pour les nœuds technologiques 28nm et inférieurs. Dans notre étude, l'empilement protégeant la grille métallique est constitué d'une bicouche résine photosensible à 248nm / revêtement antireflectif développable (dit dBARC). Une première partie du travail a consisté à mener une étude phénoménologique des facteurs impactant l'adhésion des polymères sur le TiN, et a mis en évidence la forte influence de l'état de surface du film de TiN avant l'étape de lithographie, et notamment son vieillissement. Une seconde partie a consisté à étudier les différentes solutions permettant une amélioration de la tenue des polymères à la gravure SC1. Il a été montré que si aucun traitement de surface du TiN ne permettait d'améliorer cette adhésion, une augmentation de la température de recuit du dBARC permettait quant à elle d'accroitre le greffage du carbone sur la couche de TiN et donc la tenue à la gravure de tout l'empilement. Enfin, une troisième étude a permis de mettre en évidence l'endommagement de la surface de TiN par diffusion du SC1 dans l'empilement dBARC / résine, et de proposer un mécanisme expliquant ce phénomène. La réalisation d'un dispositif expérimental de mesure, innovant, basé sur la spectroscopie infrarouge en mode de réflexions internes multiples (MIR) a par ailleurs permis de caractériser cette diffusion des espèces chimiques dans l'empilement polymérique et d'étudier les facteurs l'impactant. / Materials wet etching is still used in some specific steps of the transistors manufacturing process in microelectronics. This etching is performed in the presence of photoresist masks that define the areas to be protected from the chemical etchants. One of the major problems encountered during this technology step is the degradation of both photoresist patterns and the photoresist / material interface, which leads to the underlying material's damaging. The goal of this thesis is to study these degradations, during the wet etching of the TiN / Al / TiN metal gate of a pMOS transistor using a SC1 chemical solution (NH4OH/H2O2/ H2O), for sub-28 nm technology nodes. In our study, the stack that protects the metal gate is a bilayer with a 248 nm photoresist and a developable anti-reflective coating (or dBARC). The first part of our work was to lead a phenomenology study of the various parameters impacting the polymers adhesion on TiN. It showed the strong influence of the TiN surface state before lithography, especially its ageing. In a second part, we studied various solutions to improve the polymers stack adhesion during the SC1 etching. No TiN surface treatment could enhance this adhesion, but we found that increasing the dBARC bake temperature lead to an increase of carbon grafting on TiN, which thus gave a better resistance of photoresist patterns to SC1 etching. Then in a third part, we highlighted the TiN surface damaging after SC1 diffusion through the resist bilayer and proposed a mechanism explaining this phenomenon. We also developed an innovative experimental device based on infrared spectroscopy in the Multiple Internal Reflections (MIR) mode to characterize the diffusion of chemical etchants in the polymers stack, and study the various parameters that may impact it.

Les semiconducteurs composés III-V, et en particulier l’InGaAs, sont considéréscomme une alternative attractive pour remplacer le Silicium (Si) habituellement utilisépour former le canal dans les dispositifs Métal-Oxide-Semiconducteur (MOS). Sa hautemobilité électronique et sa bande interdite modulable, des paramètres clés pourl’ingénierie de dispositifs à haute performance, ont fait de l’InGaAs un candidatprometteur. Cependant, la stabilité thermique et la chimie des interfaces desdiélectriques high-k sur InGaAs est beaucoup plus complexe que sur Si. Tandis que laplupart des études se concentrent sur diverses méthodes de passivation, telles que lacroissance de couches passivantes d’interface (Si, Ge, et Si/Ge) et/ou le traitementchimique afin d’améliorer la qualité de l’interface high-k/InGaAs, les phénomènes telsque la diffusion d’espèces atomiques provenant du substrat dus aux traitementsthermiques n’ont pas été étudiés attentivement. Les traitements thermiques liés auxprocédés d’intégration de la source (S) et du drain (D) induisent des changementsstructurels qui dégradent les performances électriques du dispositif MOS. Unecaractérisation adaptée des altérations structurelles associées à la diffusion d’élémentsdepuis la surface du substrat est importante afin de comprendre les mécanismes defaille. Dans ce travail, une analyse de la structure ainsi que de la stabilité thermiquedes couches TiN/ZrO2/InGaAs par spectroscopie de photoélectrons résolue en angle(ARXPS) est présentée. Grâce à cette méthode d’analyse non destructive, il a étépossible d’observer des effets subtils tels que la diffusion d’espèces atomiques àtravers la couche diélectrique due au recuit thermique. A partir de la connaissance dela structure des couches, les profils d’implantation d’In et de Ga ont pu être estiméspar la méthode des scenarios. L’analyse de l’échantillon avant recuit thermique apermis de localiser les espèces In-O et Ga-O à l’interface oxide-semiconducteur. Aprèsrecuit, les résultats démontrent de façon quantitative que le recuit thermique cause ladiffusion de In et Ga vers les couches supérieures. En considérant différents scénarios,il a pu être démontré que la diffusion d’In et de Ga induite par le recuit atteint lacouche de TiO2. Dans le cas où l’échantillon est recuit à 500 °C, seule la diffusion d’Inest clairement observée, tandis que dans le cas où l’échantillon est recuit à 700 °C, onobserve la diffusion d’In et de Ga jusqu’à la couche de TiO2. L’analyse quantitative~ viii ~montre une diffusion plus faible de Gallium (~ 0.12 ML) que d’Indium (~ 0.26 ML) à 700°C /10 s. L’analyse quantitative en fonction de la température de recuit a permisd’estimer la valeur de l’énergie d’activation pour la diffusion d’Indium à travers leZircone. La valeur obtenue est très proche des valeurs de diffusion de l’Indium àtravers l’alumine et l’hafnia précédemment rapportées. Des techniquescomplémentaires telles que la microscopie électronique en transmission à hauterésolution (HR-TEM), la spectroscopie X à dispersion d’énergie (EDX) et laspectrométrie de masse à temps de vol (TOF-SIMS) ont été utilisés pour corréler lesrésultats obtenus par ARXPS. En particulier, la TOF-SIMS a révélé le phénomène dediffusion des espèces atomiques vers la surface. / III-V compound semiconductors, in particular InGaAs, are considered attractivealternative channel materials to replace Si in complementary metal-oxidesemiconductor(MOS) devices. Its high mobility and tunable band gap, requirementsfor high performance device design, have placed InGaAs as a promising candidate.However, the interfacial thermal stability and chemistry of high-k dielectrics on InGaAsis far more complex than those on Si. While most studies are focused on variouspassivation methods, such as the growth of interfacial passivation layers (Si, Ge, andSi/Ge) and/or chemical treatments to improve the quality of high-k/InGaAs interface,phenomena such as the out-diffusion of atomic species from the substrate as aconsequence of the thermal treatments have not been carefully studied. The thermaltreatments, which are related with integration processes of source and drain (S/D),lead to structural changes that degrade the electrical performance of the MOS device.A proper characterization of the structural alterations associated with the out-diffusionof elements from the substrate is important for understanding failure mechanisms. Inthis work it is presented an analysis of the structure and thermal stability ofTiN/ZrO2/InGaAs stacks by angle-resolved x-ray photoelectron spectroscopy (ARXPS).Through a non-destructive analysis method, it was possible to observe subtle effectssuch as the diffusion of substrate atomic species through the dielectric layer as aconsequence of thermal annealing. The knowledge of the film structure allowed forassessing the In and Ga depth profiles by means of the scenarios-method. For the asdeposited sample, In-O and Ga-O are located at the oxide-semiconductor interface. Byassuming different scenarios for their distribution, it was quantitatively shown thatannealing causes the diffusion of In and Ga up to the TiO2 layer. For the sampleannealed at 500 °C, only the diffusion of indium was clearly observed, while for thesample annealed at 700 °C the diffusion of both In and Ga to the TiO2 layer wasevident. The quantitative analysis showed smaller diffusion of gallium (~ 0.12 ML) thanof indium (~ 0.26 ML) at 700 °C/10 s. Since the quantification was done at differenttemperatures, it was possible to obtain an approximate value of the activation energyfor the diffusion of indium through zirconia. The value resulted to be very similar topreviously reported values for indium diffusion through alumina and through hafnia.~ vi ~Complementary techniques as high resolution transmission electron microscopy (HRTEM),energy dispersive x-ray spectroscopy (EDX) and time of flight secondary ion massspectrometry (TOF-SIMS) were used to complement the results obtained with ARXPS.Specially, TOF-SIMS highlighted the phenomenon of diffusion of the substrate atomicspecies to the surface. / Compuestos semiconductores III-V, en particular InxGa1-xAs, son consideradosmateriales atractivos para reemplazar el silicio en estructuras metal-oxidosemiconductor(MOS). Su alta movilidad y flexible ancho de banda, requisitos para eldiseño de dispositivos de alto rendimiento, han colocado al InxGa1-xAs como uncandidato prometedor. Sin embargo, la estabilidad térmica en la interfazdieléctrico/InxGa1-xAs es mucho más compleja que aquella formada en la estructuraSiO2/Si. Mientras que la mayoría de los estudios se centran en diversos métodos depasivación tales como el crecimiento de las capas intermedias (Si, Ge y Si/Ge) y/otratamientos químicos para mejorar la calidad de la interfaz, fenómenos como ladifusión de las especies atómicas del sustrato como consecuencia del recocido no hansido cuidadosamente estudiados. Los tratamientos térmicos, los cuales estánrelacionados con los procesos de integración de la fuente y el drenador (S/D) en undispositivo MOSFET, conducen a cambios estructurales que degradan el rendimientoeléctrico de un dispositivo MOS. Una caracterización apropiada de las alteracionesestructurales asociadas con la difusión de los elementos del substrato hacia las capassuperiores es importante para entender cuáles son los mecanismos de falla en undispositivo MOS. En este trabajo se presenta un análisis de la estructura y laestabilidad térmica de la estructura TiN/ZrO2/InGaAs por la espectroscopía defotoelectrones por rayos X con resolución angular (ARXPS). A través de un método deanálisis no destructivo, fue posible observar efectos sutiles tales como la difusión delas especies atómicas del sustrato a través del dieléctrico como consecuencia delrecocido. El conocimiento detallado de la estructura permitió evaluar los perfiles deprofundidad para las componentes de In-O y Ga-O por medio del método deescenarios. Para la muestra en estado como se depositó, las componentes de In-O yGa-O fueron localizadas en la interfaz óxido-semiconductor. Después del recocido, semuestra cuantitativamente que éste causa la difusión de átomos de In y Ga hacia a lascapas superiores. Asumiendo diferentes escenarios para su distribución, se muestraque el recocido provoca la difusión de In y Ga hasta la capa de TiO2. Para la muestrarecocida a 500 °C, se observó claramente la difusión de indio, mientras que para lamuestra recocida a 700 °C tanto In y Ga difunden a la capa de TiO2. El análisis~ iv ~cuantitativo mostró que existe menor difusión de átomos de galio (0.12 ML) que deindio (0.26 ML) a 700 °C/10 s. Puesto que el análisis sobre la cantidad de materialdifundido se realizó a diferentes temperaturas, fue posible obtener un valoraproximado para la energía de activación del indio a través del ZrO2. El valor resultóser muy similar a los valores reportados previamente para la difusión de indio a travésde Al2O3 y a través de HfO2. Con el fin de correlacionar los resultados obtenidos porARXPS, se emplearon técnicas complementarias como la microscopía electrónica detransmisión (TEM), la espectroscopía de energía dispersiva (EDX) y la espectrometríade masas de iones secundarios por tiempo de vuelo (SIMS-TOF). Particularmente, TOFSIMSdestacó el fenómeno de difusión de las especies atómicas sustrato hacia lasuperficie.

Cette thèse porte sur l'élaboration et la caractérisation des grilles métalliques en TiN, aluminium et lanthane pour les technologies CMOS gate-first à base d'oxyde high-k HfSiON. L'effet de l'épaisseur et de la composition des dépôts métalliques a été caractérisé sur les paramètres de la technologie 32/28nm. Ces résultats ont été reliés à une variation de travail de sortie au vide du TiN, à des dipôles induits par l'Al et le La à l'interface HfSiON/SiON et à leur diminution aux petites épaisseurs de SiON (roll-off). Nous avons montré que l'aluminium déposé sous forme métallique dans le TiN cause une diminution de son travail de sortie, opposée au faible dipôle positif induit par l'Al. Nous avons évalué l'influence du roll-off pour ces différents métaux et mis en évidence pour la première fois sa forte dépendance avec l'épaisseur de lanthane déposée. Le développement de procédés de dépôt de TiN, Al, La a permis d'accroître les bénéfices de ces matériaux pour la technologie CMOS 32/28nm. / This thesis is about the manufacturing and the characterization of TiN, aluminum and lanthanum metal gate for high-k based 32/28nm CMOS technologies. The effect of metal gate layer thickness and composition has been characterized on 32/28nm technology parameters. These results have been related to a change in the TiN vacuum work function, to Al- and La- induced dipoles at the HfSiON/SiON interface or their lowering on thin SiON (roll-off). We have shown that metallic aluminum introduced in the TiN metal gate causes a work function lowering, opposed to the weak Al-induced dipole. We have evaluated the roll-off influence for theses different metals. For the first time we report the strong roll-off dependence with the deposited lanthanum thickness. Newly developed TiN, Al, La deposition processes have brought benefits for the CMOS 32/28nm technology

Cette thèse concerne l’étude des procédés de fabrication des grilles HKMG des technologies FDSOI 14 et 28 nm sur les performances électriques des transistors MOS. Elle a porté spécifiquement sur l'aspect fiabilité et la maîtrise du travail de sortie effectif (WFeff), au travers de la diffusion des additifs comme le lanthane (La) et l’aluminium (Al). Ce travail combine des techniques de caractérisation électriques et physico-chimiques et leur développement. L'effet de l'incorporation de ces additifs sur la fiabilité et la durée de vie du dispositif a été étudié. Le lanthane dégrade les performances de claquage TDDB et de dérives suite aux tests aux tensions négatives. L’introduction d’aluminium améliore le claquage TDDB, mais dégrade les dérives aux tensions positives. Ces comportements ont été reliés à des mécanismes physiques. Par ailleurs, la diffusion de ces additifs dans l’empilement de grille a été étudiée pour différents matériaux high-k en fonction de la température et de la durée de recuit de diffusion. Les doses d’additifs ont pu être ainsi mesurées, comparées et corrélées au décalage de travail de sortie effectif de grille. On a également étudié, les influences des paramètres du procédé de dépôt de grille TiN sur leur microstructure et les propriétés électriques du dispositif, identifiant certaines conditions à même de réduire la taille de grain ou la dispersion d’orientation cristalline. Toutefois, les modulations obtenues sur le travail de sortie effectif de grille dépendent plus du ratio Ti/N, suggérant un changement du dipôle à l'interface SiO2 / high-k. Enfin, une technique éprouvée de mesure de spectroscopie à rayon X sous tension a pu être mise en place grâce des dispositifs spécifiques et une méthodologie adaptée. Elle permet de mesurer les positions relatives des bandes d’énergie à l'intérieur de l’empilement de grille. Cette technique a démontré que le décalage du travail de sortie effectif induits par des additifs (La or Al) ou par des variations d'épaisseur de grille métallique TiN provient de modifications du dipôle à l'interface SiO2/ high-k. / This Ph.D. thesis is focused on the impact of the 14 and 28 nm FDSOI technologies HKMG stack processes on the electrical performance of MOS transistors. It concerns specifically the reliability aspect and the engineering of effective workfunction (WFeff ), through diffusion of lanthanum (La) and aluminum (Al) additives. This work combines electrical and physicochemical characterization techniques, and their development. The impact of La and Al incorporation, in the MOS gate stack, on reliability and device lifetime has been studied. La addition has a significant negative impact on device lifetime related to both NBTI and TDDB degradations. Addition of Al has a significant negative impact on lifetime related to PBTI, but on the contrary improves the lifetime for TDDB degradation. These impacts on device lifetime have been well correlated to the material changes inside the gate oxides. Moreover, diffusion of these additives into the HKMG stack with annealing temperature and time has been studied on different high-k materials. The diffused dose has been compared with the resulting shift in effective workfunction (WFeff), evidencing clear correlation. In addition, impact of TiN metal gate RF-PVD parameters on its crystal size and orientation, and device electrical properties has been studied. XRD technique has been used to obtain the crystal size and orientation information. These properties are significantly modulated by TiN process, with a low grain size and a unique crystal orientation obtained in some conditions. However, the WFeff modulations are rather correlated to the Ti/N ratio change, suggesting a change in the dipole at SiO2/high-k interface. Lastly, using specific test structures and a new test methodology, a robust and accurate XPS under bias technique has been developed to determine the relative band energy positions inside the HKMG stack of MOS devices. Using this technique, we demonstrated that WFeff shift induced by La and Al or by variations in gate thickness originates due to modifications of the dipole at SiO2/high-k interface.

The continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxide semiconductor (CMOS)architecture has been the main impetus for the vast growth ofIC industry over the past decades. As the CMOS downscalingapproaches the fundamental limits, unconventional materials andnovel device architectures are required in order to guaranteethe ultimate scaling in device dimensions and maintain theperformance gain expected from the scaling. This thesisinvestigates both unconventional materials for the gate stackand the channel and a novel notched-gate device architecture,with the emphasis on the challenging issues in processintegration. High-κ gate dielectrics will become indispensable forCMOS technology beyond the 65-nm technology node in order toachieve a small equivalent oxide thickness (EOT) whilemaintaining a low gate leakage current. HfO2and Al2O3as well as their mixtures are investigated assubstitutes for the traditionally used SiO2in our MOS transistors. These high-κ filmsare deposited by means of atomic layer deposition (ALD) for anexcellent control of film composition, thickness, uniformityand conformality. Surface treatments prior to ALD are found tohave a crucial influence on the growth of the high-κdielectrics and the performance of the resultant transistors.Alternative gate materials such as TiN and poly-SiGe are alsostudied. The challenging issues encountered in processintegration of the TiN or poly-SiGe with the high-k are furtherelaborated. Transistors with TiN or poly-SiGe/high-k gate stackare successfully fabricated and characterized. Furthermore,proof-of-concept strained-SiGe surface-channel pMOSFETs withALD high-κ dielectrics are demonstrated. The pMOSFETs witha strained SiGe channel exhibit a higher hole mobility than theuniversal hole mobility in Si. A new procedure for extractionof carrier mobility in the presence of a high density ofinterface states found in MOSFETs with high-κ dielectricsis developed. A notched-gate architecture aiming at reducing the parasiticcapacitance of a MOSFET is studied. The notched gate is usuallyreferred to as a local thickness increase of the gatedielectric at the feet of the gate above the source/drainextensions. Two-dimensional simulations are carried out toinvestigate the influence of the notched gate on the static anddynamic characteristics of MOSFETs. MOSFETs with optimizednotch profile exhibit a substantial enhancement in the dynamiccharacteristics with a negligible effect on the staticcharacteristics. Notched-gate MOSFETs are also experimentallyimplemented with the integration of a high-κ gatedielectric and a poly-SiGe/TiN bi-layer gate electrode. Key words:CMOS technology, MOSFET, high-κ, gatedielectric, ALD, surface pre-treatment, metal gate, poly-SiGe,strained SiGe, surface-channel, buried-channel, notchedgate.

A wide variety of novel complementary-metal-oxide-semiconductor (CMOS) devices that are strong contenders for future high-speed and low-noise RF circuits have been evaluated by means of static electrical measurements and low-frequency noise characterizations in this thesis. These novel field-effect transistors (FETs) include (i) compressively strained SiGe channel pMOSFETs, (ii) tensile strained Si nMOSFETs, (iii) MOSFETs with high-k gate dielectrics, (iv) metal gate and (v) silicon-on-insulator (SOI) devices. The low-frequency noise was comprehensively characterized for different types of operating conditions where the gate and bulk terminal voltages were varied. Detailed studies were made of the relationship between the 1/f noise and the device architecture, strain, device geometry, location of the conduction path, surface cleaning, gate oxide charges and traps, water vapour annealing, carrier mobility and other technological factors. The locations of the dominant noise sources as well as their physical mechanisms were investigated. Model parameters and physical properties were extracted and compared. Several important new insights and refinements of the existing 1/f noise theories and models were also suggested and analyzed. The continuing trend of miniaturizing device sizes and building devices with more advanced architectures and complex materials can lead to escalating 1/f noise levels, which degrades the signal-to-noise (SNR) ratio in electronic circuits. For example, the 1/f noise of some critical transistors in a radio receiver may ultimately limit the information capacity of the communication system. Therefore, analyzing electronic devices in order to control and find ways to diminish the 1/f noise is a very important and challenging research subject. We present compelling evidence that the 1/f noise is affected by the distance of the conduction channel from the gate oxide/semiconductor substrate interface, or alternatively the vertical electric field pushing the carriers towards the gate oxide. The location of the conduction channel can be varied by the voltage on the bulk and gate terminals as well by device engineering. Devices with a buried channel architecture such as buried SiGe channel pMOSFETs and accumulation mode MOSFETs on SOI show significantly reduced 1/f noise. The same observation is made when the substrate/source junction is forward biased which decreases the vertical electric field in the channel and increases the inversion layer separation from the gate oxide interface. A 1/f noise model based on mobility fluctuations originating from the scattering of electrons with phonons or surface roughness was proposed. Materials with a high dielectric constant (high-k) is necessary to replace the conventional SiO2 as gate dielectrics in the future in order to maintain a low leakage current at the same time as the capacitance of the gate dielectrics is scaled up. In this work, we have made some of the very first examinations of 1/f noise in MOSFETs with high-k structures composed by layers of HfO2, HfAlOx and Al2O3. The 1/f noise level was found to be elevated (up to 3 orders of magnitude) in the MOSFETs with high-k gate dielectrics compared to the reference devices with SiO2. The reason behind the higher 1/f noise is a high density of traps in the high-k stacks and increased mobility fluctuation noise, the latter possibly due to noise generation in the electron-phonon scattering that originates from remote phonon modes in the high-k. The combination of a TiN metal gate, HfAlOx and a compressively strained surface SiGe channel was found to be superior in terms of both high mobility and low 1/f noise. / QC 20100928

<p>The continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxide semiconductor (CMOS)architecture has been the main impetus for the vast growth ofIC industry over the past decades. As the CMOS downscalingapproaches the fundamental limits, unconventional materials andnovel device architectures are required in order to guaranteethe ultimate scaling in device dimensions and maintain theperformance gain expected from the scaling. This thesisinvestigates both unconventional materials for the gate stackand the channel and a novel notched-gate device architecture,with the emphasis on the challenging issues in processintegration.</p><p>High-κ gate dielectrics will become indispensable forCMOS technology beyond the 65-nm technology node in order toachieve a small equivalent oxide thickness (EOT) whilemaintaining a low gate leakage current. HfO₂and Al₂O₃as well as their mixtures are investigated assubstitutes for the traditionally used SiO₂in our MOS transistors. These high-κ filmsare deposited by means of atomic layer deposition (ALD) for anexcellent control of film composition, thickness, uniformityand conformality. Surface treatments prior to ALD are found tohave a crucial influence on the growth of the high-κdielectrics and the performance of the resultant transistors.Alternative gate materials such as TiN and poly-SiGe are alsostudied. The challenging issues encountered in processintegration of the TiN or poly-SiGe with the high-k are furtherelaborated. Transistors with TiN or poly-SiGe/high-k gate stackare successfully fabricated and characterized. Furthermore,proof-of-concept strained-SiGe surface-channel pMOSFETs withALD high-κ dielectrics are demonstrated. The pMOSFETs witha strained SiGe channel exhibit a higher hole mobility than theuniversal hole mobility in Si. A new procedure for extractionof carrier mobility in the presence of a high density ofinterface states found in MOSFETs with high-κ dielectricsis developed.</p><p>A notched-gate architecture aiming at reducing the parasiticcapacitance of a MOSFET is studied. The notched gate is usuallyreferred to as a local thickness increase of the gatedielectric at the feet of the gate above the source/drainextensions. Two-dimensional simulations are carried out toinvestigate the influence of the notched gate on the static anddynamic characteristics of MOSFETs. MOSFETs with optimizednotch profile exhibit a substantial enhancement in the dynamiccharacteristics with a negligible effect on the staticcharacteristics. Notched-gate MOSFETs are also experimentallyimplemented with the integration of a high-κ gatedielectric and a poly-SiGe/TiN bi-layer gate electrode.</p><p><b>Key words:</b>CMOS technology, MOSFET, high-κ, gatedielectric, ALD, surface pre-treatment, metal gate, poly-SiGe,strained SiGe, surface-channel, buried-channel, notchedgate.</p>