晶圓製程設備商必須充分利用全球化智慧資源規劃，發展企業策略，才能創造企業競爭力和成長動能。經過多次的景氣循環，晶圓設備產業已經成為少數廠商全球激烈競爭的環境，特別是仍有兩家設備供應商以上的產品線。對於客戶而言，購買設備的主要因素來自於廠商製程能力和成本的優勢。除了少數關鍵製程由一家壟斷外，客戶都可以在每一個新製程世代(Technology node)找到兩家廠商評估設備和技術需求。在贏者全拿的壓力與吸引力下，在每一個新製程世代的銷售週期中，晶圓設備商都必須要充分利用智慧資本化的效益，掌握客戶的技術、量產時程，才能確保銷售空間。在發展策略上，為面對高技術競爭但是低成長的產業環境，晶圓設備商必須要透過併購和整合其核心技術相關新事業才能同時整合既有智慧資源和創造成長。 不管從市場規模和產業鏈來看，台灣的半導體產業已經成為全球最重要的製造據點，也是台灣最重要的產業之一。半導體製造廠龐大的資本支出和相關需求更讓台灣成為各半導體設備商的銷售服務的兵家必爭之地。根據SEMI的最新市場調查，總計台灣2007年的半導體設備市場達到106.5億美元，較2006年大幅成長45.2%，正式超越日本成為全球最大半導體設備投資市場。在產業鏈中，晶圓製程設備除了是晶圓廠最大資本支出外，還是產業技術發展的供應者。很可惜的是，雖然擁有龐大的商機做後盾，台灣卻沒有及時發展這個領域。在轉換成本、專利、和領導晶圓製造商合作開發和人才、資金等高產業門檻下，除了自動化設備較有進展外，台灣在晶圓製程設備產業的自給率普遍低於5%，技術、智財和人才還是掌握在外國的晶圓製程設備廠商。在沒有整合產、官、學、研等資源和適合的智財管理規劃下，在需要高度基礎科學和長遠技術發展的晶圓製程設備產業，我們設備自制化的結果不高，並不令人訝異。晶圓製造業者的議價和技術自主能力因此而受到拘束，所發展的智財也沒有太大價值和效用。 本研究目的希望以智慧資源規劃為研究方法，進行晶圓製程設備產業的實證研究。先就市場特性分析晶圓製程設備產業概況，接著探討廠商如何運用智慧資源規劃的資本化和產業結構化切入市場，最後在實證研究上以分析主要晶圓製程設備廠商的專利能量和最新奈米技術High-k/Metal Metal Gate探討產業的技術發展趨勢與廠商智慧資源規劃的運用和佈署。期望從綜合上述論點，做為台灣是否適合發展晶圓製程設備和又該如何準備智慧資源規劃的參考。 / Global intellectual resource planning (IRP) is cruicial in industrial strategy for wafer fabrication equipment vendors to develop competence and growth momentums. After several business cycles during the past few decades, this industry has become a very competitive market of a few players. For their customers, the key decision factors are the technology capability and cost of the vendors. Except for some critical process equipments dominated by only one vendor, the customers can identify 2 vendors to evaluate their equipment and cost performance. That Winner takes all become the pressure and attraction of the industry. The vendors must fully apply the value of intellectual property and overhaul their customer’s technology and production roadmap to ensure their share in the market. To cope with the market challenges of low growth and highly competitiveness, the vendors must incoporate and integrate other new companies of their core technology to consolidate given intellectual resource and create better achievements. Either from the perspective of market size and industry value chain, Taiwan has played the most important role in semiconductor manufacturing industry worldwide. To extend their market share and keep in the lead, the foundry and DRAM companies have aggressively invested in the production of 300mm fabs. The vast investments and its production demands have made Taiwan the most competitive place in semiconductor equipment markets. According to the SEMI most update, the business volume of Taiwan semiconductor equipments market reached to US$10.65 billion in 2007, with an impressive growth of 45.2% more than 2006. Taiwan has overtaken Japan and become the largest semiconductor equipment markets in the world. In the industry value chain, the wafer fabrication equipments not only accounted for the greatest capital expenditure of fibs but also the foundation for the process technology development. It is a pity that the equipments industry in Taiwan did not flourish as along with the great market here. All the key technologies, people, materials and components are manipulated by foreign vendors. This situation resulted in an un-balanced development in domestic semiconductor industry as well as the bargain power and self-owned technology. The related developed intellectual rights can not show the real value and effect. With the high entry barriers of transfer cost, patents, professionals and investments of wafer fabrication equipments markets, Taiwan vendors take less than 5% in the market share, except for some progress in automation equipments of lower IP, capital and transfer cost barriers. The Taiwan vendors have not demonstrated capability in process technology to penetrate the markets. The wafer fabrication equipment market growth was a result of o the outsource investment from Europe, US and Japan fabs. It turns out that the technology, IP and people are still possessed by foreign vendors. Without the synergy and integration of government, academia and industry and intangible resource planning, it is not surprising that our production localization ratio is relatively low. Thus, the thesis will elaborate the case study in the way of intellectual resource planning. First, the research will analyze the industrial characteristics of wafer fabrication equipment market. In the followings, this research will discuss how vendors can apply IRP to penetrate the market. Finally, this research will analyze the patents of major vendors and High-k/Metal Gate process technology to elaborate the industry technology cycles and new technology development strategy. As a result, the thesis will try to discuss if it is suitable for Taiwan to develop the wafer fabrication equipment market and also serve for reference how to prepare the intellectual resource planning.

A new high-k dielectric material, i.e., zirconium-doped tantalum oxide (Zr-doped TaOx), in the form of a sputter-deposited thin film with a thickness range of 5-100 nm, has been studied. Important applications of this new dielectric material include the gate dielectric layer for the next generation metal-oxide-semiconductor field effect transistor (MOSFET). Due to the aggressive device scaling in ultra-large-scale integrated circuitry (ULSI), the ultra-thin conventional gate oxide (SiO2) is unacceptable for many practical reasons. By replacing the SiO2 layer with a high dielectric constant material (high-k), many of the problems can be solved. In this study, a novel high-k dielectric thin film, i.e., TaOx doped with Zr, was deposited and studied. The film’s electrical, chemical, and structural properties were investigated experimentally. The Zr dopant concentration and the thermal treatment condition were studied with respect to gas composition, pressure, temperature, and annealing time. Interface layer formation and properties were studied with or without an inserted thin tantalum nitride (TaNx) layer. The gate electrode material influence on the dielectric properties was also investigated. Four types of gate materials, i.e., aluminum (Al), molybdenum (Mo), molybdenum nitride (MoN), and tungsten nitride (WN), were used in this study. The films were analyzed with ESCA, XRD, SIMS, and TEM. Films were made into MOS capacitors and characterized using I-V and C-V curves. Many promising results were obtained using this kind of high-k film. It is potentially applicable to future MOS devices.

A new high-k dielectric material, i.e., zirconium-doped tantalum oxide (Zr-doped TaOx), in the form of a sputter-deposited thin film with a thickness range of 5-100 nm, has been studied. Important applications of this new dielectric material include the gate dielectric layer for the next generation metal-oxide-semiconductor field effect transistor (MOSFET). Due to the aggressive device scaling in ultra-large-scale integrated circuitry (ULSI), the ultra-thin conventional gate oxide (SiO2) is unacceptable for many practical reasons. By replacing the SiO2 layer with a high dielectric constant material (high-k), many of the problems can be solved. In this study, a novel high-k dielectric thin film, i.e., TaOx doped with Zr, was deposited and studied. The film’s electrical, chemical, and structural properties were investigated experimentally. The Zr dopant concentration and the thermal treatment condition were studied with respect to gas composition, pressure, temperature, and annealing time. Interface layer formation and properties were studied with or without an inserted thin tantalum nitride (TaNx) layer. The gate electrode material influence on the dielectric properties was also investigated. Four types of gate materials, i.e., aluminum (Al), molybdenum (Mo), molybdenum nitride (MoN), and tungsten nitride (WN), were used in this study. The films were analyzed with ESCA, XRD, SIMS, and TEM. Films were made into MOS capacitors and characterized using I-V and C-V curves. Many promising results were obtained using this kind of high-k film. It is potentially applicable to future MOS devices.

Cette thèse porte sur l’élaboration et la caractérisation électrique et physico-chimique des grilles métalliques des dispositifs FDSOI MOSFET 14 nm à base d’oxyde high-K fabriqués chez STMicroelectronics. Ces grilles métalliques sont composées de couches de TiN, lanthane et aluminium, déposées par pulvérisation cathodique RF. Des structures de test et un schéma d’intégration simplifié permettant l’analyse capacitive ont été mis en place pour caractériser la modulation du travail de sortie effectif des grilles métalliques en TiN avec l’incorporation d'additifs tels que le lanthane ou l’aluminium. Ces additifs ont été incorporés suivant une approche de grille sacrificielle. Par ailleurs, une méthodologie inédite basée sur la fluorescence X a été proposée et validée pour la caractérisation précise en ligne de la diffusion des additifs. Cette méthodologie permet de prouver que la dose effective de l’espèce incorporée après recuit de diffusion peut être modélisée en fonction de l’épaisseur du TiN piédestal dans la grille sacrificielle ainsi que de la température de recuit. De plus, la variation de l’épaisseur de l’oxyde interfaciel sur une seule plaquette (oxyde biseau) autorise l’identification de l’origine physique de la modulation du travail de sortie effectif, qui s’explique par un dipôle qui évolue avec la dose effective de l’espèce incorporée. En conséquence, un modèle de la diffusion des dopants de grille dans l’oxyde high-K et de leur impact sur le travail de sortie effectif des grilles métalliques a été proposé afin de moduler avec précision la tension de seuil (VTH) des dispositifs FDSOI 14 nm. En outre, l’impact de l’oxyde high-K à la fois sur la diffusion des additifs et sur la modulation du travail de sortie effectif a été mis en évidence. Enfin, un procédé innovant de dépôt métallique, permettant la modification de la microstructure du TiN, a été développé afin d’améliorer davantage la variabilité locale du VTH des dispositifs FDSOI. / This Ph.D. thesis is focused on the fabrication and electrical and physicochemical characterization of metal gates in 14 nm high-K based FDSOI MOSFET devices, manufactured at STMicroelectronics. These metal gates are composed of TiN, lanthanum and aluminum layers, deposited by RF sputtering. Test structures and a simplified integration scheme allowing C-V measurements, have been implemented in order to characterize the modulation of the effective work function of TiN metal gates with the incorporation of dopants such as lanthanum or aluminum. These additives are incorporated in a sacrificial gate-first approach. Furthermore, a new methodology based on X-ray fluorescence was proposed and validated for accurate in-line characterization of the diffusion of dopants. This methodology enables to prove that the effective dose of the species incorporated into dielectrics after diffusion annealing may be modeled as a function of the thickness of the pedestal TiN in the sacrificial gate and the annealing temperature. Moreover, the variation of the thickness of the interfacial oxide along the wafer (bevel oxide) authorizes the identification of the origin of the modulation of the effective work function, which is explained by a dipole that evolves with the effective dose of the incorporated dopant. Accordingly, a model of the diffusion of dopants into the gate dielectrics and their impact on the effective work function of metal gates has been proposed to precisely modulate the threshold voltage (VTH) of the 14 nm FDSOI devices. In addition, the influence of the high-K oxide on both the diffusion of dopants and the modulation of the effective work function was highlighted. Lastly, an innovative process for metal deposition, allowing the modification of the microstructure of TiN, was developed in order to further improve the local VTH variability in FDSOI devices.

Im Rahmen dieser Arbeit werden haftstellen-basierte Speicherzellen als mögliche Alternative zum bestehenden Floating-Gate Konzept untersucht. Hierbei wird zunächst mittels Simulation und ausgewählten Messverfahren das Verständnis der Funktionsweise vertieft. Der darauffolgende Abschnitt befasst sich mit der Verbesserung der elektrischen Eigenschaften, basierend auf Änderungen der verwendeten Materialien und dem räumlichen Aufbau. Abschließend erfolgt die Untersuchung der Anwendbarkeit des Zellkonzeptes in hochdichten Zellenfeldern.

Im Rahmen dieser Arbeit werden haftstellen-basierte Speicherzellen als mögliche Alternative zum bestehenden Floating-Gate Konzept untersucht. Hierbei wird zunächst mittels Simulation und ausgewählten Messverfahren das Verständnis der Funktionsweise vertieft. Der darauffolgende Abschnitt befasst sich mit der Verbesserung der elektrischen Eigenschaften, basierend auf Änderungen der verwendeten Materialien und dem räumlichen Aufbau. Abschließend erfolgt die Untersuchung der Anwendbarkeit des Zellkonzeptes in hochdichten Zellenfeldern.:Kurzfassung Abstract 1 Einleitung 2 Grundlagen aktiver Halbleiterelemente 2.1 Die MOS-Struktur 2.2 Der MOS-Feldeffekt-Transistor 2.3 Nichtflüchtige Festkörperspeicher 2.4 Speicherarchitekturen 2.5 Charakterisierungsmethoden von Halbleiter-Speicherelementen 3 Defektbasierte Ladungsspeicherung in dielektrischen Schichten 3.1 Physikalische Grundlagen von Haftstellen 3.2 Betrachtung der vertikalen Ladungsverteilung mit Hilfe von Simulationen 3.3 Ableitung der vertikalen Ladungsverteilung aus Messungen 4 Elektrisches Verhalten einer haftstellen-basierten Speicherzelle 4.1 Auswirkung von inhomogen verteilter Ladung in der Speicherschicht 4.2 Auswirkungen von Al2O3-Topoxid auf das Zellverhalten 4.3 Auswirkung des Steuerelektrodenmaterials auf das Zellverhalten 4.4 Einfluss von Kanal- und Source/Drain-Dotierung 5 Integration in eine stark skalierte NAND Architektur 5.1 Auswirkung struktureller Effekte auf die Speicherzelle 5.2 Störmechanismen beim Betrieb von stark skalierten NAND-Speichern 6 Zusammenfassung und Ausblick 6.1 Zusammenfassung 6.2 Ausblick Danksagung Lebenslauf Symbol- und Abkürzungsverzeichnis Literaturverzeichnis