Η Ηλεκτροχημική Ενίσχυση της Κατάλυσης (ή φαινόμενο NEMCA) είναι ένα φαινόμενο όπου εφαρμογή μικρών ρευμάτων ή δυναμικών (±2 V) μπορεί να τροποποιήσει την ενεργότητα καταλυτών υποστηριγμένων σε ιοντικούς ή μικτούς ιοντικούς-ηλεκτρονικούς αγωγούς, να επηρεάσει την εκλεκτικότητα σε επιθυμητή κατεύθυνση και να μεταβάλλει τις ηλεκτρονικές και συνεπώς τις καταλυτικές ιδιότητες με τρόπο ελεγχόμενο, αντιστρεπτό και σε κάποιο βαθμό προβλέψιμο. Στην παρούσα διατριβή μελετήθηκε η επίδραση του πάχους του καταλυτικού υμενίου στο μέγεθος της ηλεκτροχημικής ενίσχυσης, χρησιμοποιώντας την αντίδραση της οξείδωσης του C2H4 σε πορώδη υμένια Pt πάχους μεταξύ 0.2 και 1.4 μm, εναποτεθειμένα με τη μέθοδο επάλειψης οργανομεταλλικής πάστας, σε στερεό ηλεκτρολύτη YSZ, έναν αγωγό ιόντων Ο2-. Βρέθηκε πως η αύξηση του πάχους των υμενίων που χρησιμοποιούνται στις μελέτες ηλεκτροχημικής ενίσχυσης, προκαλεί μείωση στο λόγο προσαύξησης του ρυθμού, ρ, συμπεριφορά που βρίσκεται σε καλή συμφωνία με τις αναλυτικές προβλέψεις του μαθηματικού μοντέλου που περιγράφει την επιφανειακή διάχυση-αντίδραση των προωθητικών ειδών. Με βάση τις επιτυχείς μελέτες ηλεκτροχημικής ενίσχυσης που έχουν πραγματοποιηθεί σε λεπτά (40 nm), εναποτεθειμένα με τη μέθοδο της ιοντοβολής (sputtering) καταλυτικά υμένια, έγινε επέκταση της μελέτης της επίδρασης του πάχους σε τόσο λεπτά υμένια. Συγκεκριμένα, εξετάσθηκε η καταλυτική και η ηλεκτροχημικά ενισχυμένη συμπεριφορά πολύ λεπτών (30-90 nm) καταλυτικών υμενίων εναποτεθειμένων με τη μέθοδο του sputtering, τη μέθοδο Pulsed Laser Deposition και την τεχνική εναπόθεσης με ατμό (vapor deposition). Τιμές του λόγου προσαύξησης του ρυθμού, ρ, έως και 440 και τιμές φαρανταϊκής απόδοσης, Λ, έως και 1000 παρατηρήθηκαν για τα υμένια που εναποτέθηκαν με τη μέθοδο του sputtering. Η διασπορά μετάλλου στα υμένια αυτά είναι έως και 20%, συγκρίσιμη δηλαδή με αυτή των εμπορικών υποστηριγμένων καταλυτών. Τέλος, παρουσιάζεται η λειτουργία ενός πρόσφατα ανεπτυγμένου μονολιθικού ηλεκτροχημικά ενισχυόμενου αντιδραστήρα (MEPR), χρησιμοποιώντας την περιβαλλοντικού ενδιαφέροντος αντίδραση της αναγωγής του ΝΟ από αιθυλένιο παρουσία Ο2. Χρησιμοποιώντας καταλυτικά στοιχεία τύπου Pt-Rh(1:1)/YSZ/Au, παρουσία 10% Ο2 και σε ογκομετρικές παροχές έως και 1000 cc/min, ο αντιδραστήρας λειτούργησε επιδεικνύοντας τιμές φαρανταϊκής απόδοσης που ξεπερνούν τη μονάδα και επιτυγχάνοντας 50% και 44% προσαύξηση στους ρυθμούς μετατροπής του καυσίμου και του ΝΟ αντίστοιχα. Αυτή η μελέτη είναι η πρώτη που επιδεικνύει ηλεκτροχημική ενίσχυση της αντίδρασης αναγωγής του NO σε τόσο υψηλές τιμές μερικής πίεσης οξυγόνου (10% O2), που είναι αντιπροσωπευτικές για εξατμίσεις μηχανών πτωχού καυσίμου και μηχανών Diesel. Ο MEPR αποδεσμεύει το φαινόμενο NEMCA από την έως σήμερα χρήση του στην καθαρά εργαστηριακή κλίμακα και δείχνει πολλά υποσχόμενος για την πρακτική εφαρμογή του φαινομένου. / The effect of Electrochemical Promotion of Catalysis (EPOC or NEMCA effect) is a phenomenon where application of small currents or potentials (±2 V) alters the activity and selectivity of catalysts supported on ionic or mixed ionic-electronic conductors and modifies the electronic and thus catalytic properties in a controllable, reversible and to some extent predictable manner. The effect of catalyst film thickness on the magnitude of electrochemical promotion (ρ and Λ values) has not been studied experimentally so far but a mathematical model has been developed, accounting for surface diffusion and reaction of the promoting species, which predicts a strong variation of ρ and Λ with catalyst film thickness L. In the present thesis is examined for the first time experimentally the effect of catalyst film thickness on the magnitude of the EPOC, using porous Pt catalyst-electrodes prepared from Engelhard Pt paste with thicknesses in the range 0.2 to 1.4 μm. It was found that increasing the thickness of porous catalyst films used in electrochemical promotion studies causes a decrease in the rate enhancement ratio, ρ, due to the gradual axial decrease from the three-phase-boundaries to the top of the film of the surface concentration of the promoting backspillover O2- species which diffuse and react on the porous catalyst surface. Increasing film thickness causes a moderate increase in the Faradaic efficiency, Λ, which can be predicted by the parameter 2Fro/I0. The ρ and Λ behaviour is in good agreement with the analytical model prediction and provides additional support for the O2- promoter reaction-diffusion model and for the sacrificial promoter mechanism of electrochemical promotion. Most electrochemical promotion studies have been carried out so far with thick (0.1 μm to 5 μm) porous metal catalyst films with a roughness factor of the order of 500 and small (typically less than 0.1%) metal dispersion, deposited on solid electrolytes using a variety of deposition techniques. Very recently, electropromotion studies have been extended to thin (40 nm) sputter coated porous metal catalysts with metal dispersion of the order of 10 to 30%. The effect of thickness with such thin (30 to 90 nm) sputtered Pt catalyst-electrodes on the magnitude of electrochemical promotion is discussed, as well as the effect of the catalyst deposition method (Sputtering, Pulsed Laser Deposition and Vapor Deposition) using the model reaction of ethylene oxidation. Rate enhancement ratio, ρ, values up to 440 and Λ values up to 1000 where obtained for the sputtered films, in agreement with the sacrificial promoter and diffusion-reaction models of EPOC which predict increase in ρ value with thinner films. An environmental interest reaction, the reduction of NO by ethylene in the presence of excess oxygen, was investigated in a recently developed MEPR. In this novel dismantlable monolithic-type electrochemically promoted catalytic reactor, thin (~40 nm) porous catalyst films are sputter-deposited on thin (0.25 mm) parallel solid electrolyte plates supported in the grooves of a ceramic monolithic holder and serve as electropromoted catalyst elements. Using Pt-Rh(1:1)/YSZ/Au-type catalyst elements, the 8-plate reactor operated with apparent Faradaic efficiency exceeding unity achieving significant and reversible enhancement in the rates of C2H4 and NO consumption in presence of up to 10% O2 in the feed at gas flow rates up to 1000 cc/min. The Pt-Rh co-sputtered films exhibited very good performance in terms of stability and selectivity for N2 formation, i.e. practically 100% under all reaction conditions. The reactor, which is a hybrid between a monolithic catalytic reactor and a flat-plate solid oxide fuel cell, permits easy practical utilization of the electrochemical promotion of catalysis.

This thesis presents the analysis, design and characterization of an integrated high-frequency phase-locked loop (PLL) frequency multiplier. The frequency multiplier is novel in its use of a low multiplication factor of 4 and a fully differential topology for rejection of common mode interference signals. The PLL is composed of a voltage controlled oscillator (VCO), injection-locked frequency divider (ILFD) for the first divide-by-two stage, a static master-slave flip-flop (MSFF) divider for the second divide-by-two stage and a Gilbert cell mixer phase detector (PD). The circuit has been fabricated using a standard CMOS 0.18-um process based on its relatively low cost and ready availability. The PLL frequency multiplier generates an output signal at 26 GHz and is the highest operational frequency PLL in the technology node reported to date. Time domain phase plane analysis is used for prediction of PLL locking range based on initial conditions of phase and frequency offsets. Tracking range of the PLL is limited by the inherent narrow locking range of the ILFD, and is confirmed via experimental results. The performance benefits of the fully differential PLL are experimentally confirmed by the injection of differential- and common-mode interfering signals at the VCO control lines. A comparison of the common- and differential-mode modulation indices reveals that a common mode rejection ratio (CMRR) of greater than 20 dB is possible for carrier offset frequencies of less than 1 MHz. Closed-loop frequency domain transfer functions are used for prediction of the PLL phase noise response, with the PLL being dominated by the reference and VCO phase noise contributions. Regions of dominant phase noise contributions are presented and correlated to the overall PLL phase noise performance. Experimental verifications display good agreement and confirm the usefulness of the techniques for PLL performance prediction. The PLL clock multiplier has an operational output frequency of 26.204 to 26.796 GHz and a maximum output frequency step of 16 MHz. Measured phase noise at 1 MHz offset from the carrier is -103.9 dBc/Hz. The PLL clock multiplier core circuit (VCO/ILFD/MSFF Divider/PD) consumes 186 mW of combined power from 2.8 and 4.3 V DC rails. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2009-04-24 11:31:35.384

This work deals with the design of a CMOS pixel sensor prototype (called MIMOSA 31) for the outer layers of the International Linear Collider (ILC) vertex detector. CMOS pixel sensors (CPS) also called monolithic active pixel sensors (MAPS) have demonstrated attractive performance towards the requirements of the vertex detector of the future linear collider. MIMOSA 31developed at IPHC-Strasbourg is the first pixel sensor integrated with 4-bit column-level ADC for the outer layers. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with an analog to digital converter (ADC). The self-triggered ADC accommodating the pixel readout in a rolling shutter mode completes the conversion by performing a multi-bit/step approximation. The ADC design was optimized for power saving at sampling frequency. Accounting the fact that in the outer layers of the ILC vertex detector, the hit density is inthe order of a few per thousand, this ADC works in two modes: active mode and inactive mode. This thesis presents the details of the prototype chip and its laboratory test results.

"2009" / Thesis (MSc (Hons))--Macquarie University, Faculty of Science, Dept. of Physics and Engineering, 2010. / Bibliography: p. 163-166. / Introduction -- Design theory and process technology -- 15GHz oscillator implementations -- 24GHz oscillator implementation -- Frequency prescaler implementation -- MMIC fabrication and measurement -- Conclusion. / Advances in Silicon Germanium (SiGe) Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) technology has caused a recent revolution in low-cost Monolithic Microwave Integrated Circuit (MMIC) design. -- This thesis presents the design, fabrication and measurement of four MMICs for frequency synthesis, manufactured in a commercially available IBM 0.18μm SiGe BiCMOS technology with ft = 60GHz. The high speed and low-cost features of SiGe Heterojunction Bipolar Transistors (HBTs) were exploited to successfully develop two single-ended injection-lockable 15GHz Voltage Controlled Oscillators (VCOs) for application in an active Ka-Band antenna beam-forming network, and a 24GHz differential cross-coupled VCO and 1/6 synchronous static frequency prescaler for emerging Ultra Wideband (UWB) automotive Short Range Radar (SRR) applications. -- On-wafer measurement techniques were used to precisely characterise the performance of each circuit and compare against expected simulation results and state-of-the-art performance reported in the literature. -- The original contributions of this thesis include the application of negative resistance theory to single-ended and differential SiGe VCO design at 15-24GHz, consideration of manufacturing process variation on 24GHz VCO and prescaler performance, implementation of a fully static multi-stage synchronous divider topology at 24GHz and the use of differential on-wafer measurement techniques. -- Finally, this thesis has llustrated the excellent practicability of SiGe BiCMOS technology in the engineering of high performance, low-cost MMICs for frequency synthesis in millimeterwave (mm-wave) devices. / Mode of access: World Wide Web. / xxii, 166 p. : ill (some col.)

Le sujet de cette thèse est de concevoir un prototype de capteur à pixel CMOS adapté aux couches extérieures du détecteur de vertex de l'International Linear Collider (ILC).Il est le premier prototype de capteur CMOS intégrant un ADC en bas de colonne de 4-bit et une matrice de pixels, dédié aux couches externes. L'architecture du prototype nommé MIMOSA 31 comprend une matrice de pixels de 48 colonnes par 64 lignes, des ADC en bas de colonne. Les pixels sont lus ligne par ligne en mode d'obturation roulant. Les ADCs reçoivent la sortie des pixels en parallèle achève réalisent la conversion en effectuant une approximation de multi-bit/step. Sachant que dans les couches externes de l'ILC, la densité de pixels touchés est de l'ordre de quelques pour mille, !'ADC est conçu pour fonctionner en deux modes (actifs et inactifs) afin de minimiser la consommation d'énergie. Les résultats indiquent que MIMOSA 31 répond aux performances nécessaires pour cette couche de capteurs. / This work deals with the design of a CMOS pixel sensor prototype (called MIMOSA 31) for the outer layers of the International Linear Collider (ILC) vertex detector. CMOS pixel sensors (CPS) also called monolithic active pixel sensors (MAPS) have demonstrated attractive performance towards the requirements of the vertex detector of the future linear collider. MIMOSA 31developed at IPHC-Strasbourg is the first pixel sensor integrated with 4-bit column-level ADC for the outer layers. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with an analog to digital converter (ADC). The self-triggered ADC accommodating the pixel readout in a rolling shutter mode completes the conversion by performing a multi-bit/step approximation. The ADC design was optimized for power saving at sampling frequency. Accounting the fact that in the outer layers of the ILC vertex detector, the hit density is inthe order of a few per thousand, this ADC works in two modes: active mode and inactive mode. This thesis presents the details of the prototype chip and its laboratory test results.

O presente trabalho descreve o desenvolvimento e implementação de duas configurações distintas de um receptor optoeletrônico integrado. A primeira configuração é similar a um projeto encontrado na literatura mas apresenta diversas modificações que lhe conferiram melhor desempenho em comparação ao projeto original. A segunda configuração é uma nova proposta deste trabalho. O receptor foi desenvolvido e implementado visando sua aplicação em redes de comunicações ópticas passivas (PONs) de alta velocidade comutadas a pacote, para possibilitar a utilização da técnica de multiplexação em comprimento de onda (WDM), aumentando assim a capacidade de transmissão da rede, em particular no ramo de ligação da rede de serviços com o usuário final, denominado rede de acesso. O principal objetivo do receptor aqui desenvolvido foi proporcionar uma sintonia rápida entre os canais disponíveis na rede, possibilitando sua seleção num tempo inferior àquele necessário para a transmissão de um único pacote de informação, diminuindo assim o atraso de sintonia e, por conseguinte, a perda de informação. Para tanto, os circuitos integrados implementados e caracterizados referem-se aos circuitos de chaveamento eletrônico e do amplificador de transimpedância das duas configurações investigadas. Os dados experimentais obtidos para as duas configurações confirmaram a previsão de chaveamento dos canais de entrada num intervalo de tempo da ordem de alguns nanosegundos, o que é totalmente compatível com a velocidade de transmissão das aplicações a que se destina este receptor (aproximadamente 5 Gbits/s). Adicionalmente, são apresentados os dados experimentais relativos à freqüência de corte, ganho direto, isolação, relação on/off e características de ruído dos circuitos implementados. / The present work describes the design and implementation of two configurations of an integrated optoelectronic receiver. The first one is similar to a previously reported design but with some modifications to improve its performance. The second one is a new proposal of this work. The goal of the receiver design and implementation was its application in high bit rate packet-switched passive optical networks (PONs) employing the wavelength division multiplexing (WDM) technique to increase the network capacity, in particular on the connection branch of the network core with the final user, the access network. The main goal of the receiver design was to achieve a fast channel tuning, allowing a tuning time smaller than the required for the transmission of a single information packet, decreasing the tuning latency and, therefore, the rate of information packet loss. In order to accomplish this goal, the implemented and tested integrated circuits include the electronic switching circuit and the transimpedance amplifier for both configurations investigated. The measured data for both configurations confirm the expected input channel switching time results, of about a few nanoseconds, which is certainly useful for the expected bit rate of operation (approximate 5 Gbps). Additionally, experimental results concerning cutoff frequency and bandwidth, direct gain, isolation, on/off ratio, and noise characteristics of both implemented circuits are presented.

La forte demande et le besoin d’intégration hétérogène de nouvelles fonctionnalités dans les systèmes mobiles et autonomes, tels que les mémoires, capteurs, et interfaces de communication doit prendre en compte les problématiques d’hétérogénéité, de consommation d’énergie et de dissipation de chaleur. Les systèmes mobiles intelligents sont déjà dotés de plusieurs composants de type capteur comme les accéléromètres, les thermomètres et les détecteurs infrarouge. Cependant, jusqu’à aujourd’hui l’intégration de capteurs chimiques dans des systèmes compacts sur puce reste limitée pour des raisons de consommation d’énergie et dissipation de chaleur principalement. La technologie actuelle et fiable des capteurs de gaz, les résistors à base d’oxyde métallique et les MOSFETs (Metal Oxide Semiconductor- Field Effect Transistors) catalytiques sont opérés à de hautes températures de 200–500 °C et 140–200 °C, respectivement. Les transistors à effet de champ à grille suspendu (SG-FETs pour Suspended Gate-Field Effect Transistors) offrent l’avantage d’être sensibles aux molécules gazeuses adsorbées aussi bien par chemisorption que par physisorption, et sont opérés à température ambiante ou légèrement au-dessus. Cependant l’intégration de ce type de composant est problématique due au besoin d’implémenter une grille suspendue et l’élargissement de la largeur du canal pour compenser la détérioration de la transconductance due à la faible capacité à travers le gap d’air. Les transistors à double grilles sont d’un grand intérêt pour les applications de détection de gaz, car une des deux grilles est fonctionnalisée et permet de coupler capacitivement au canal les charges induites par l’adsorption des molécules gazeuses cibles, et l’autre grille est utilisée pour le contrôle du point d’opération du transistor sans avoir besoin d’une structure suspendue. Les transistors monoélectroniques (les SETs pour Single Electron Transistors) présentent une solution très prometteuse grâce à leur faible puissance liée à leur principe de fonctionnement basé sur le transport d’un nombre réduit d’électrons et leur faible niveau de courant. Le travail présenté dans cette thèse fut donc concentré sur la démonstration de l’intégration 3D monolithique de SETs sur un substrat de technologie CMOS (Complementary Metal Oxide Semiconductor) pour la réalisation de la fonction capteurs de gaz très sensible et ultra basse consommation d’énergie. L’approche proposée consiste à l’intégration de SETs métalliques à double grilles dans l’unité de fabrication finale BEOL (Back-End-Of-Line) d’une technologie CMOS à l’aide du procédé nanodamascene. Le système sur puce profitera de la très élevée sensibilité à la charge électrique du transistor monoélectronique, ainsi que le traitement de signal et des données à haute vitesse en utilisant une technologie de pointe CMOS disponible. Les MOSFETs issus de la technologie FD-SOI (Fully Depleted-Silicon On Insulator) sont une solution très attractive à cause de leur pouvoir d’amplification du signal quand ils sont opérés dans le régime sous-le-seuil. Ces dispositifs permettent une très haute densité d’intégration due à leurs dimensions nanométriques et sont une technologie bien mature et modélisée. Ce travail se concentre sur le développement d’un procédé de fonctionnalisation d’un MOSFET FD-SOI comme démonstration du concept du capteur de gaz à base de transistor à double grilles. La sonde Kelvin a été la technique privilégiée pour la caractérisation des matériaux sensibles par le biais de mesure de la variation du travail de sortie induite par l’adsorption de molécules de gaz. Dans ce travail, une technique de caractérisation des matériaux sensibles alternative basée sur la mesure de la charge de surface est discutée. Pour augmenter la surface spécifique de l’électrode sensible, un nouveau concept de texturation de surface est présenté. Le procédé est basé sur le dépôt de réseaux de nanotubes de carbone multi-parois par pulvérisation d’une suspension de ces nanotubes. Les réseaux déposés servent de «squelettes» pour le matériau sensible. L’objectif principal de cette thèse de doctorat peut être divisé en 4 parties : (1) la modélisation et simulation de la réponse d’un capteur de gaz à base de SET à double grilles ou d’un MOSFET FD-SOI, et l’estimation de la sensibilité ainsi que la puissance consommée; (2) la caractérisation de la sensibilité du Pt comme couche sensible pour la détection du H[indice inférieur 2] par la technique de mesure de charge de surface, et le développement du procédé de texturation de surface de la grille fonctionnalisée avec les réseaux de nanotubes de carbone; (3) le développement et l’optimisation du procédé de fabrication des SETs à double grilles dans l’entité BEOL d’un substrat CMOS; et (4) la fonctionnalisation d’un MOSFET FD-SOI avec du Pt pour réaliser la fonction de capteur de H[indice inférieur 2]. / Abstract : The need of integration of new functionalities on mobile and autonomous electronic systems has to take into account all the problematic of heterogeneity together with energy consumption and thermal dissipation. In this context, all the sensing or memory components added to the CMOS (Complementary Metal Oxide Semiconductor) processing units have to respect drastic supply energy requirements. Smart mobile systems already incorporate a large number of embedded sensing components such as accelerometers, temperature sensors and infrared detectors. However, up to now, chemical sensors have not been fully integrated in compact systems on chips. Integration of gas sensors is limited since most used and reliable gas sensors, semiconducting metal oxide resistors and catalytic metal oxide semiconductor- field effect transistors (MOSFETs), are generally operated at high temperatures, 200–500 °C and 140–200° C, respectively. The suspended gate-field effect transistor (SG-FET)-based gas sensors offer advantages of detecting chemisorbed, as well as physisorbed gas molecules and to operate at room temperature or slightly above it. However they present integration limitations due to the implementation of a suspended gate electrode and augmented channel width in order to overcome poor transconductance due to the very low capacitance across the airgap. Double gate-transistors are of great interest for FET-based gas sensing since one functionalized gate would be dedicated for capacitively coupling of gas induced charges and the other one is used to bias the transistor, without need of airgap structure. This work discusses the integration of double gate-transistors with CMOS devices for highly sensitive and ultra-low power gas sensing applications. The use of single electron transistors (SETs) is of great interest for gas sensing applications because of their key properties, which are its ultra-high charge sensitivity and the ultra-low power consumption and dissipation, inherent to the fundamental of their operation based on the transport of a reduced number of charges. Therefore, the work presented in this thesis is focused on the proof of concept of 3D monolithic integration of SETs on CMOS technology for high sensitivity and ultra-low power gas sensing functionality. The proposed approach is to integrate metallic double gate-single electron transistors (DG-SETs) in the Back-End-Of-Line (BEOL) of CMOS circuits (within the CMOS interconnect layers) using the nanodamascene process. We take advantage of the hyper sensitivity of the SET to electric charges as well from CMOS circuits for high-speed signal processing. Fully depleted-silicon on insulator (FD-SOI) MOSFETs are very attractive devices for gas sensing due to their amplification capability when operated in the sub-threshold regime which is the strongest asset of these devices with respect to the FET-based gas sensor technology. In addition these devices are of a high interest in terms of integration density due to their small size. Moreover FD-SOI FETs is a mature and well-modelled technology. We focus on the functionalization of the front gate of a FD-SOI MOSFET as a demonstration of the DGtransistor- based gas sensor. Kelvin probe has been the privileged technique for the investigation of FET-based gas sensors’ sensitive material via measuring the work function variation induced by gas species adsorption. In this work an alternative technique to investigate gas sensitivity of materials suitable for implementation in DG-FET-based gas sensors, based on measurement of the surface charge induced by gas species adsorption is discussed. In order to increase the specific surface of the sensing electrode, a novel concept of functionalized gate surface texturing suitable for FET-based gas sensors are presented. It is based on the spray coating of a multi-walled-carbon nanotubes (MW-CNTs) suspension to deposit a MW-CNT porous network as a conducting frame for the sensing material. The main objective of this Ph.D. thesis can be divided into 4 parts: (1) modelling and simulation of a DG-SET and a FD-SOI MOSFET-based gas sensor response, and estimation of the sensitivity as well as the power consumption; (2) investigation of Pt sensitivity to hydrogen by surface charge measurement technique and development of the sensing electrode surface texturing process with CNT networks; (3) development and optimization of the DG-SET integration process in the BEOL of a CMOS substrate, and (4) FD-SOI MOSFET functionalization with Pt for H[subscript 2] sensing.

The locality is situated in the city quarter Brno-Židenice in close proximity of the railway line connecting Brno and Česká Třebová. The area is delimited by the Bubeníčkova Street from the South, the Koperníkova Street from the East, by Lazaretní Street from the North and by a road copying the railway line from the West. The elemental form of the projected compound is divided into three blocks by pass-through axes. The blocks are interconnected with a common basement where underground car park is located. The blocks have up to six floors above ground. On the first floor, there is a variety of commercial spaces for shops and restaurants and in the middle there is a supermarket. In the northern object, there are situated different types of amenities (kinder-garden, leisure activities for children, spa) on the second and higher floors. On the top floor of this object we can find the flats as well as in the middle building from the second floor. The commercial areas, offices and library are situated in the southern block.

The territory in question for the design of architectural study is located in the city of Brno-Zidenice, cadastral area of Zidenice, on the left (east) bank of the river Svitava, 2 km east of the historic core. An area of about 4.1 ha is bounded on the south Bubenickova street, on the east side is street Kopernikova, Lazaretni is on the north and on the west side is nameless street, which currently serves as a handler - connecting. The subject of this diploma thesis is the architectural study of the design of the urban spatial structure with intensive use of city urban area, designed in pre-diploma project, which preceded diploma thesis. The meaning this proposal is to achieve higher densities while maintaining quality of life and living environment. The shape of the object´s ground plan based on the area. The shape defined Bubenickova street from the south side and street Kopernikova defined the shape from the east side, which are themselves almost perpendicular. Also the shape is parallel with a very important point territory - the urban spa (architect B. Fuchs, 1931), which is adjacent to the proposed facility and the stresses their importance in terms of architecture. The spatial resolution respects the surrounding buildings. The aim is to release the most western part, which is defined for parking, urban public transportation, entrances to underground garages and green areas. Green area is also located in the northern part of the territory where it is created park with a water feature and tangled hiking trails. From the western and eastern parts of the object is tree-lined because the object is very the close to the surrounding streets. The object is for vehicular traffic completely closed and is only for pedestrians. But it also has a public plaza with green areas and water features for relaxation and wellbeing.

The theme of my disseration is an architecture study of multifunctional building which is surrounded by the streets Křenová, Rumiště, Mlýnská a Štěpánská. The main aim of the work is to create structure wich would offer different functions. These would fill the missing services and offer new opportunities. The result of my design is the construction which is characterized by its public terraces placed on top of the covered parking lots on the first floor. The whole complex is formed by three connected blocks. One of the important parts of the design is to uncover river Ponávka. That would make this area more attractive. The building has 2 underground floors and up to 6 floors. In the first two stories there are different public services - shops, café, restaurant, kindergarten, fitness, art gallery and other. In the third and fourth floor there are offices and apartements. Fifth and six floor are just for living. The construction of the building is from monolithic reinforced concrete frame, horizontal structure consists of beamless slabs.