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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2007. / Includes bibliographical references.

Thesis (Ph. D.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2008. / Includes bibliographical references.

La miniaturització de la industria microelectrònica és un fet del tot inqüestionables i la tecnologia CMOS no n'és una excepció. En conseqüència la comunitat científica s'ha plantejat dos grans reptes: En primer lloc portar la tecnologia CMOS el més lluny possible ('Beyond CMOS') tot desenvolupant sistemes d'altes prestacions com microprocessadors, micro - nanosistemes o bé sistemes de píxels. I en segon lloc encetar una nova generació electrònica basada en tecnologies totalment diferents dins l'àmbit de les Nanotecnologies. Tots aquests avanços exigeixen una recerca i innovació constant en la resta d'àrees complementaries com són les d'encapsulat. L'encapsulat ha de satisfer bàsicament tres funcions: Interfície elèctrica del sistema amb l'exterior, Proporcionar un suport mecànic al sistema i Proporcionar un camí de dissipació de calor. Per tant, si tenim en compte que la majoria d'aquests dispositius d'altes prestacions demanden un alt nombre d'entrades i sortides, els mòduls multixip (MCMs) i la tecnologia flip chip es presenten com una solució molt interessant per aquests tipus de dispositiu. L'objectiu d'aquesta tesi és la de desenvolupar una tecnologia de mòduls multixip basada en interconnexions flip chip per a la integració de detectors de píxels híbrids, que inclou: 1) El desenvolupament d'una tecnologia de bumping basada en bumps de soldadura Sn/Ag eutèctics dipositats per electrodeposició amb un pitch de 50µm, i 2) El desenvolupament d'una tecnologia de vies d'or en silici que permet interconnectar i apilar xips verticalment (3D packaging) amb un pitch de 100µm. Finalment aquesta alta capacitat d'interconnexió dels encapsulats flip chip ha permès que sistemes de píxels tradicionalment monolítics puguin evolucionar cap a sistemes híbrids més compactes i complexes, i que en aquesta tesi s'ha vist reflectit transferint la tecnologia desenvolupada al camp de la física d'altes energies, en concret implantant el sistema de bump bonding d'un mamògraf digital. Addicionalment s'ha implantat també un dispositiu detector híbrid modular per a la reconstrucció d'imatges 3D en temps real, que ha donat lloc a una patent. / The scaling down of microelectronic's industry is a fact completely unquestionable and the technology CMOS is not an exception. Consequently, the scientific community has considered two great challenges: In first place to bring the technology CMOS the most far away possible ('Beyond CMOS') while developing advanced systems such as microprocessors, micro - nanosystems or pixel systems. On the other hand to begin a new electronic generation based on technologies totally different inside the Nanotechnologies area.All these advances require a research and constant innovation in the rest of complementary areas such as Packaging. Any packaging system has to satisfy three functions in a basic way: Electrical interface of the system with the exterior, to provide a mechanical support to the system and to provide a way of heat dissipation. In order to satisfy the requirements of advanced systems with high number of I/Os, the multichip modules (MCMs) and the flip chip technology are presented as a very interesting solution.The goal of this thesis consist of developing a multichip module technology based on flip chip interconnections for the integration of hybrid pixel detectors, which includes: 1) The development of a bumping technology based on electrodeposited Sn/Ag eutectic solder bumps with a pitch of 50µm, and 2) The development of a technology of gold vias in silicon that allows to interconnect and to stack chips vertically (3D packaging) with a pitch of 100µm.Finally this high capacity of flip chip interconnection has allowed that traditional monolithic pixel systems can evolve towards hybrid systems more compact and complex, and that in this thesis has been reflected transferring the technology developed in the field of the high energies physics, implanting the bump bonding system of a digital mammography system in particular. Additionally also a modular hybrid detecting device (CMOS Image Sensor) has been implanted for the reconstruction of 3D images in real time, which has caused a patent.

Thesis (Ph. D.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, Thomas J. Watson School of Engineering and Applied Science, 2008. / Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2009. / Includes bibliographical references.

For decades, advances in device scaling has proven to be critical in improving the performance and productivity of 2D systems. In this thesis, we explore how advances in technology have pushed functional integration to such a high-level that interconnection and packaging issues represent real barriers to further progress. While three-dimensional (3D) integration offers to be a potential contender to overcome the barriers of increased energy consumption due to interconnects and bandwidth limitations, there are certain challenges that must be overcome before systems can be successfully stacked. Cooling and power delivery are among these key challenges in the integration of high performance 3D ICs. To address these challenges, microchannel heat sinks for inter-stratum cooling and through-silicon vias (TSVs) for signaling and power delivery between stacked ICs were explored. Novel integration schemes to integrate these uidic and electrical interconnects in conventional CMOS processes were also explored. Compact physical modeling was utilized to understand the trade-offs involved in the integration of electrical and microfluidic interconnects in a 3D IC stack. These concepts were demonstrated experimentally by showing different CMOS compatible methods of fabricating microchannels and integration of high aspect ratio (~20:1) and high density (200,000/cm²) electrical TSVs in the fins of the microchannels for signaling and power delivery. A novel mesh process for bottom up plating of high aspect ratio TSVs is also shown in this work. Fluidic reliability measurements are shown to demonstrate the feasibility of this technology. This work also demonstrates the design and fabrication of a 3D testbed which consists of a 2 chip stack with microchannel cooling on each level. Preliminary testing of the stack along with interlayer electro-fluidic I/Os has also been demonstrated.

As the convergence of multiple functions in a single electronic device drives current electronic trends, the need for increasing integration density is becoming more emphasized than in the past. To keep up with the industrial need and realize the new system integration law, three-dimensional (3-D) integration called System-on-Package (SoP) is becoming necessary. However, the commercialization of 3-D integration should overcome several technical barriers, one of which is the difficulty for the electrical design of interconnections. The 3-D interconnection design is difficult because of the modeling challenge of electrical coupling from the complicated structures of a large number of interconnections. In addition, mixed-signal design requires broadband modeling, which covers a large frequency spectrum for integrated microsystems. By using currently available methods, the electrical modeling of 3-D interconnections can be a very challenging task. This dissertation proposes a new method for constructing a broadband model of a large number of 3-D interconnections. The basic idea to address the many interconnections is using modal basis functions that capture electrical effects in interconnections. Since the use of global modal basis functions alleviates the need for discretization process of the interconnection structure, the computational cost is reduced considerably. The resultant interconnection model is a RLGC model that describes the broadband electrical behavior including losses and couplings. The smaller number of basis functions makes the interconnection model simpler, and therefore allows the generation of network parameters at reduced computational cost. Focusing on the modeling of bonding wires in stacked ICs and through-silicon via (TSV) interconnections, this research validates the interconnection modeling approach using several examples from 3-D full-wave EM simulation results.

Laser Induced Forward Transfer (LIFT) techniques show promise as a disruptive technology which will enable the placement of components smaller than what conventional pick-and-place techniques are capable of today. Limitations of current die-attach techniques are presented and discussed and present the opportunity for a new placement method. This study introduces the Thermo-Mechanical Selective Laser Assisted Die Transfer (tmSLADT) process and is an application of the unique blistering behavior of a dynamic releasing layer when irradiated by low energy focused UV laser pulses. The potential of tmSLADT as the next generation LIFT technique is demonstrated by the "touchless" transfer of 65 μm thick silicon tiles between two substrates spaced 195 μm apart. Additionally, the advantages of an enclosed blister-actuator mechanism over previously studied ablative and thermal releasing techniques are discussed. Finally, experimental results studying transfer precision indicate this non optimized die transfer process compares with, and may exceed, the placement precision of current assembly techniques. / Defense Microelectronics Activity (DMEA) under agreement number H94003-09-2-0905