Para suportar as novas aplicações heterogêneas e dinâmicas, como a TV digital interativa, os vídeos sob demanda e a computação em nuvem, as redes ópticas WDM (wavelength division multiplexing) estão passando por uma grande mudança. Estão deixando de ser estáticas para se tornarem reconfiguráveis. Assim, elas devem suportar diferentes taxas e formatos de modulação, que podem variar com o tempo, tornando-as heterogêneas tanto no que se refere aos tipos de serviços, quanto às tecnologias de transmissão. Assim, novos desafios para controlar e administrar estas redes estão surgindo e soluções cognitivas estão começando a ser estudadas. Uma das premissas de uma solução cognitiva é a adaptabilidade. Neste cenário, este trabalho propõe uma metodologia de controle adaptativo de ganho para amplificadores ópticos em redes WDM dinâmicas. Tal metodologia baseia-se em uma máscara de potência com informações sobre o desempenho óptico do amplificador em termos de figura de ruído e \"planicidade\" espectral de ganho, ajustando seu ponto de operação visando um compromisso entre estes parâmetros. Esta metodologia foi aplicada em um problema de roteamento e alocação de comprimento de onda para algumas topologias de redes com 4, 6, 10 e 15 nós e considerando uma restrição de qualidade de serviço, relacionada à OSNR do sinal, para realização da conexão. Os resultados mostram uma redução na probabilidade de bloqueio total com a aplicação da metodologia proposta em relação a um cenário sem a metodologia de 80% para abaixo de 20% em alguns casos. / To support new dynamic and heterogeneous applications such as interactive digital TV, video on demand and cloud computing, WDM (wavelength division multiplexing) optical networks are undergoing significant changes. They are changing from static to reconfigurable networks. Thus, they need to support different data rates and modulation formats, which can varie along the time, leading to a heterogeneous network with respect not only to different services, but also to different transmission technology. Therefore, new network control and management challenges are arising and cognitive solutions are being studied. One of the cognitive solution premises is adaptability. In this scenario, this work propose an adaptive gain control methodology for optical amplifiers in WDM dynamic optical networks. Such methodology is based on a power mask with information about the amplifier optical performance in terms of noise figure and gain flatness, adjusting its operating point aiming to the best trade off between these parameters. This methodology was applied to a routing and wavelength assignment problem to some network topology with 4, 6, 10 and 15 nodes and considering a quality of service constraint, due to the signal OSNR, to accomplish the connection. Results show blocking probability reduction from 80% to bellow 20% for some cases from a scenario without the methodology to one with it.

The growth in the number of wireless devices and applications underscores the need for characterizing and mitigating interference induced problems such as distortion and blocking. A typical interference scenario involves the detection of a small amplitude signal of interest (SOI) in the presence of a large amplitude interfering signal; it is desirable to attenuate the interfering signal while preserving the integrity of SOI and an appropriate dynamic range. If the frequency of the interfering signal varies or is unknown, an adaptive notch function must be applied in order to maintain adequate attenuation. This work explores the performance space of a phase cancellation technique used in implementing the desired notch function for communication systems in the 1-3 GHz frequency range. A system level model constructed with MATLAB and related simulation results assist in building the theoretical foundation for setting performance bounds on the implemented solution and deriving hardware specifications for the RF notch subsystem devices. Simulations and measurements are presented for a Low Noise Amplifer (LNA), voltage variable attenuators, bandpass filters and phase shifters. Ultimately, full system tests provide a measure of merit for this work as well as invaluable lessons learned. The emphasis of this project is the on-wafer LNA measurements, dependence of IC system performance on mismatches and overall system performance tests. Where possible, predictions are plotted alongside measured data. The reasonable match between the two validates system and component models and more than compensates for the painstaking modeling efforts. Most importantly, using the signal to interferer ratio (SIR) as a figure of merit, experimental results demonstrate up to 58 dB of SIR improvement. This number represents a remarkable advancement in interference rejection at RF or microwave frequencies.

Made available in DSpace on 2016-04-04T18:31:31Z (GMT). No. of bitstreams: 1 Raphael Montali da Assumpcao.pdf: 4212017 bytes, checksum: 0f3ac0dc977e7baf5d1589a58db83ffd (MD5) Previous issue date: 2011-06-29 / This study analyzes the impact that Radio over Fiber technology, functioning as a transport network, causes to a Wireless Sensor Network. Phenomena present in Radio over Fiber system tnet degrade the RF signal are analyzed. For this impact verification a test bed was assembled with wireless sensors operating at the 915 MHz Range and RoF equipments. To avoid uncertainties caused by effects in radio signal propagation a channel emulation system capable of varying the attenuation imposed to the radio signal was used. In the conducted tests packet loss and received signal strength at the receiver were measured for two different modulations: FSK and MSK. In the first experiment the Wireless Sensor Network was tested without the introduction of the Radio over Fiber system, those results were used as a reference for the other tests. /n the second experiment tests with the introduction of a Radio over Fiber system creating a covering cell were made. In the third experiment a second RoF equipment was introduced to create a second covering cell. Ali the tests were repeated using a Low Noise Amplifier. The results show that it is possible to use RoF in a WSN implementation. However, the impact at the penalty introduced by the RoF on the cell covering distance was high, showing that in fact there is an impact in the covering distance. It was shown that the introduction of new covering cells adds additional penalty because of characteristics of the RoF. The introduction of the LNA was shown to be effective for fighting the degradation added by the RoF system. / O presente trabalho analisa o impacto que a tecnologia de R?dio Sobre Fibra, funcionando como rede de transporte, provoca a uma Rede de Sensores Sem Fio. S?o analisados os fen?menos presentes no sistema de r?dio sobre fibra que degradam o sinal de r?dio frequ?ncia. Para verifica??o deste impacto foi montada uma estrutura de testes com sensores Sem Fio operando na faixa de 915 MHz e equipamentos de RoF. Para evitar incertezas causadas por efeitos de propaga??o do sinal de r?dio foi utilizada uma bancada de emula??o de canal com capacidade para varia??o da atenua??o do sinal r?dio. Nos testes realizados foram medidas a perda de pacotes e a pot?ncia de sinal recebido na base receptora em duas modula??es diferentes: FSK e MSK. No primeiro experimento foram feitos testes com a Rede de Sensores Sem Fio sem a introdu??o do sistema de R?dio Sobre Fibra, cujos resultados foram utilizados como refer?ncia para os outros testes. No segundo experimento foram feitos testes com a introdu??o de um sistema de RoF criando uma c?lula de cobertura. No terceiro experimento foi introduzido um segundo equipamento de RoF criando uma segunda c?lula de cobertura. Todos os testes foram repetidos com a utiliza??o de um amplificador de baixo ru?do. Os resultados demonstram a possibilidade da implementa??o de RSSF com a utiliza??o de RoF. Entretanto, o impacto da penalidade introduzida pelo RoF na ?rea de cobertura da RSSF foi elevado, demonstrando que de fato existe uma penalidade em termos de dist?ncia de cobertura. Ficou demonstrado que a introdu??o de novas c?lulas acrescenta penaliza??o adicional devido a caracter?sticas do RoF. A introdu??o do LNA demonstrou ser eficaz para combater a degrada??o inserida pelo sistema RoF.

This master's thesis presents the design and the realization of a low noise amplifier (LNA) for the S band of radio frequency spectrum from 2.3 GHz to 2.4 GHz. This thesis is mainly focused on stability and impedance matching networks study. Ansoft Designer and ANSYS HFSS programs are used for this design to simulate the LNA. Different low noise devices are simulated in order to find the best results for the final design. Moreover, a coaxial cavity resonator is designed in the input of the LNA and works as a band pass filter. Finally, the LNA is fabricated and its properties compared with the simulation results.

This work deals with design, simulation and realisation of a receiving systém of an S-band front end for satellite communication. The first part of the project is designed the low noise amplifier (LNA) with high associated gain. The basic point of the design is choice of the active device. In the present time are available the ultra low noise transistors based on the GaAs with high mobility electron. The two-stage LNA has been designed with Agilent ATF-55143. It is pseudomorphic HEMTs ,which work in an enhancement mode.These transistor do not require a negative bias voltage and have extremely good typical noise figure. The design includes an interdigital tuned band pass filter between stages. The second part of the project is search another way design circuit. There are designed two LNA with paralel coupled line filter. The first has been applied on a PTFE substrate Duroid 5880 with relative permitivity 2,2 and tg d = 0,009. The substrate FR-4 (r = 4.34) with the thickness 0.06” was used for the realization.

Phased array element RF front ends typically use single pole double throw (SPDT) switches or circulators with high isolation to prevent leakage of transmit energy into the receiver circuits. However, as phased-array designs scale to the millimeter-wave range, with high degrees of integration, the physical size and performance degradations associated with switches and circulators can present challenges in meeting system performance and size/weight/power (SWAP) requirements. This work demonstrates a loss-aware methodology for analysis and design of switchless transmit/receive (T/R) circuits. The methodology provides design insights and a practical, generally applicable approach for solving the multi-variable optimization problem of switchless power amplifier/low-noise amplifier (PALNA) matching networks, which present optimal matching impedances to both the power amplifier (PA) and the low noise amplifier (LNA) while maximizing power transfer efficiency and minimizing dissipative losses in each (transmit or receive) mode of operation. Three PALNA example designs at W-band are presented in this dissertation, each following a distinct design methodology. The first example design in 32SOI CMOS leverages PA and LNA circuits that already include 50 Ω matching networks at both input and output. The second example design in 8XP SiGe develops the PA and LNA circuits and integrates the PA output and LNA input matching networks into the PALNA matching network that connects the PA and the LNA. The third design in 32SOI CMOS leverages the loss-aware PALNA design methodology to develop a PALNA that achieves simulated maximum power added efficiency of 18 % in transmit and noise figure of 7.5 dB in receive at 94 GHz, which is beyond the published state-of-art for T/R circuits. In addition, for comparison purposes, this dissertation also presents an efficient, switch-based T/R circuit design in 32SOI CMOS technology, which achieves a simulated maximum power added efficiency of 15 % in transmit and noise figure of 6.5 dB in receive at 94 GHz, which is also beyond the published state-of-art for T/R circuits. / Doctor of Philosophy / In military and commercial applications, phased arrays are devices primarily used to achieve focusing and steering of transmitted or received electromagnetic energy. Phased arrays consist of many elements, each with an ability to both transmit and receive radio frequency (RF) signals. Each element incorporates a power amplifier (PA) for transmit and a low noise amplifier (LNA) for receive, which are typically connected using a single pole double throw (SPDT) switch or a circulator with high isolation to prevent leakage of transmit energy into the receiver circuits. However, as phased arrays exploit the latest technological advances in circuit integration and their frequencies of operation increase, physical size and performance degradations associated with switches and circulators can present challenges in meeting system performance and size/weight/power (SWAP) requirements. This dissertation provides a loss-aware methodology for analysis and design of switchless transmit/receive (T/R) circuits where the switches and circulators are replaced by carefully designed power amplifier/low-noise amplifier (PALNA) impedance matching networks. In the switchless T/R circuits, the design goals of maximum power efficiency and minimum noise in transmit and receive, respectively, are achieved through impedance matching that is optimal and low-loss in both modes of operation simultaneously. Three distinct PALNA example designs at W-band are presented in this dissertation, each following a distinct design methodology. With each new design, lessons learned are leveraged and design methodologies are enhanced. The first example design leverages already available PA and LNA circuits and connects them using 50 Ω transmission lines whose lengths are designed to guarantee optimum impedance match in receive and transmit mode of operation. The second example design develops new PA and LNA circuits and connects them using 50 Ω transmission lines whose lengths are designed to simultaneously achieve optimum impedance matching for maximum power efficiency in transmit mode of operation and lowest noise in receive mode of operation. The third design leverages a loss-aware PALNA design methodology, a multi-variable optimization procedure, to develop a PALNA that achieves simulated maximum power added efficiency of 18 % in transmit and noise figure of 7.5 dB in receive at 94 GHz, which is beyond the published state-of-art for T/R circuits. In addition, for comparison purposes with the third PALNA design, this dissertation also presents an efficient, switch-based T/R circuit design, which achieves a simulated maximum power added efficiency of 15 % in transmit and noise figure of 6.5 dB in receive at 94 GHz, which is also beyond the published state-of-art for T/R circuits.

Le rendement consommation/fréquence des futures générations de circuits intégrés sur silicium n’est pas satisfaisant à cause de la faible mobilité électronique de ce semi-conducteur et des relativement grandes tensions d’alimentation VDD requises. Ce travail se propose d’explorer numériquement les potentialités des transistors à effet de champ (FET) à base de matériaux III-V à faible bande interdite et à haute mobilité pour un fonctionnement en haute fréquence et une ultra basse consommation. Tout d’abord, l’étude consiste à analyser théoriquement le fonctionnement d’une capacité MOS III-V en résolvant de façon auto-cohérente les équations de Poisson et Schrödinger (PS). On peut ainsi comprendre comment et pourquoi les effets extrinsèques comme les états de pièges à l’interface high-k/III-V dégradent les caractéristiques intrinsèques. Pour une géométrie 2D, les performances des dispositifs sont estimées pour des applications logiques et analogiques à l’aide d’un modèle de transport quasi-balistique.Nous avons ensuite étudié plus en détails les performances des MOSFET III-V en régimes statiques et dynamiques sous faible VDD, à l’aide du simulateur particulaire MONACO de type Monte Carlo. Les caractéristiques de quatre topologies de MOSFET ont été quantitativement étudiées, en termes de transport quasi-balistique, de courants statiques aux états passants et bloqués, de rendement fréquence/consommation et de bruit. Nous en tirons des conclusions sur l’optimisation de ces dispositifs. Enfin, l'étude comparative avec un FET à base de Si démontre clairement le potentiel des MOSFET III-V pour les applications à haute fréquence, à faible puissance de consommation et à faible bruit. / The optimal frequency performance/power-consumption trade-off is very difficult to achieve using CMOS technology because of low Si carrier mobility and relatively large supply voltage (VDD) required for circuit operation. The main objective of this work is to theoretically explore, in terms of operation frequency and power consumption, the potentialities of nano-MOSFET based on III-V materials with low energy bandgap and high electron mobility.First, this work analyzes theoretically the operation of a III-V MOS capacitor using self-consistent solution of Poisson - Schrödinger system equation. We can thus understand how and why the interface trap state densities at high-k/III-V interfaces degrade the intrinsic characteristics. For a 2D geometry, the performance of devices is estimated for digital and analog applications using a model of quasi-ballistic transport.Then, we estimated the performance of III-V MOSFET in static and dynamic regimes under low VDD, using MONACO a Monte Carlo simulator. The characteristics of four designs of III-V MOSFET have been studied quantitatively in terms of quasi-ballistic transport, DC current in ON and OFF states, frequency/consumption efficiency and optimum matching conditions of noise. We provide the guideline on the design optimization of the devices.Finally, the comparative study with Si-based devices clearly demonstrates the potentiality of III-V nano-MOSFET architectures for high-frequency and low-noise application under low operating power and even for low voltage logic.

This thesis deals with a theoretical analysis of the basic parameters of receivers, input circuit architecture and signal digitization. According to the specified assignment it is outlined block scheme of front end for software receiver with specified components and the total bilance is calculated. Individual parts of the system are designed and realized. This is a set of four input filters for bandwidths: short waves up to 30 MHz, 87,5-108 MHz, 144-148 MHz and 174-230 MHz. The main point of design is a circuit containing a low-noise amplifiers, switches, and two amplifiers with adjustable amplification. Mainly are used integrated circuits from Analog Devices corporation. To control the various switches and adjustable amplifiers was designed a separate panel, which is connected to the main circuit via a cable. In the last phase was the whole system and its components subjected to measurements. Thanks to a number of mounted SMA connectors it is possible to measure different parts of the system and we are able to modify it partially.

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works.