abstract: Programmable Metallization Cell (PMC) technology has been shown to possess the necessary qualities for it to be considered as a leading contender for the next generation memory. These qualities include high speed and endurance, extreme scalability, ease of fabrication, ultra low power operation, and perhaps most importantly ease of integration with the CMOS back end of line (BEOL) process flow. One area where detailed study is lacking is the reliability of PMC devices. In previous reliability work, the low and high resistance states were monitored for periods of hours to days without any applied voltage and the results were extrapolated to several years (>10) but little has been done to analyze the low resistance state under stress. With or without stress, the low resistance state appears to be highly stable but a gradual increase in resistance with time, less than one order of magnitude after ten years when extrapolated, has been observed. It is important to understand the physics behind this resistance rise mechanism to comprehend the reliability issues associated with the low resistance state. This is also related to the erase process in PMC cells where the transition from the ON to OFF state occurs under a negative voltage. Hence it is important to investigate this erase process in PMC cells under different conditions and to model it. Analyzing the programming and the erase operations separately is important for any memory technology but its ability to cycle efficiently (reliably) at low voltages and for more than 1E4 cycles (without affecting the cells performance) is more critical. Future memory technologies must operate with the low power supply voltages (<1V) required for small geometry nodes. Low voltage programming of PMC memory devices has previously been demonstrated using slow voltage sweeps and small numbers of fast pulses. In this work PMC memory cells were cycled at low voltages using symmetric pulses with different load resistances and the distribution of the ON and OFF resistances was analyzed. The effect of the program current used during the program-erase cycling on the resulting resistance distributions is also investigated. Finally the variation found in the behavior of similar resistance ON states in PMC cells was analyzed more in detail and measures to reduce this variation were looked into. It was found that slow low current programming helped reducing the variation in erase times of similar resistance ON states in PMC cells. This scheme was also used as a pre-conditioning technique and the improvements in subsequent cycling behavior were compared. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

In recent years, the conventional Flash memory with floating structure is expected to reach physical limits as devices scaling down in near future. In order to overcome this problem, alternative memory technologies have been widely investigated. And the resistance random access memory (RRAM) has attracted extensive attention for the application in next generation nonvolatile memory, due to the excellent memory property including lower consumption of energy, lower operating voltage, higher density, fast operating speed, simple structure, higher endurance, retention and process compatibility with CMOS. In this study, the tungsten-based oxide is chosen as RRAM switching layer because the tungsten is compatible with the present complementary metal oxide semiconductor (CMOS) process. The Pt/WOX/TiN structure device cells had the resistance switching property successfully. However, the experiment result revealed the inferior resistance switching property. The resistance switching characteristic of the WOX thin film is extremely unstable, it is impossible to become the products. Compared with WOX, the resistance switching property of WSiOX RRAM device is improved substantially such as stability of resistance states and reliability of device. In second parts, we purposed two methods to enhance the device switching characteristic, including controlling the filament formation/ interruption in the W doped SiOX layer and restricting oxygen movement in the WSiON layer. Finally, the transport mechanisms of carrier is analyzed and researched from the current-voltage (I-V) switching characteristic of the device. A designed circuit was used in this study to accurately observe the resistance switching process with a pulse generator and oscilloscope, which reveals that the switching process is related to both time and voltage. The oxygen movement will drift in the low temperature due to the electrical field and restricted the crystal lattice vibration. But, it will diffuse through thermal dynamics in the high temperature.

The evolution of the MOSFET technology has been driven by the aggressive shrinkage of the device size to improve the device performance and to increase the circuit density. Currently, many research demonstrated that the continuous polycrystalline silicon film in the floating-gate dielectric could be replaced with nanocrystal (nc) embedded high-k thin film to minimize the charge loss due to the defective thin tunnel dielectric layer. This research deals with both the statistical aspect of reliability and electrical aspect of reliability characterization as well. In this study, the Zr-doped HfO2 (ZrHfO) high-k MOS capacitors, which separately contain the nanocrystalline zinc oxide (nc-ZnO), silicon (nc-Si), Indium Tin Oxide (nc-ITO) and ruthenium (nc-Ru) are studied on their memory properties, charge transportation mechanism, ramp-relax test, accelerated life tests, failure rate estimation and thermal effect on the above reliability properties. C-V hysteresis result show that the amount of charges trapped in nanocrystal embedded films is in the order of nc-ZnO>nc-Ru>nc-Si~nc-ITO, which might probably be influenced by the EOT of each sample. In addition, all the results show that the nc-ZnO embedded ZrHfO non-volatile memory capacitor has the best memory property and reliability. In this study, the optimal burn-in time for this kind of device has been also investigated with nonparametric Bayesian analysis. The results show the optimal burn-in period for nc-ZnO embedded high-k device is 5470s with the maximum one-year mission reliability.

Le marché mondial des semi-conducteurs connait une croissance continue due à l'essor de l'électronique grand public et entraîne dans son sillage le marché des mémoires non volatiles. L'importance de ces produits mémoires est accentuée depuis le début des années 2000 par la mise sur le marché de produits nomades tels que les smartphones ou plus récemment les produits de l’internet des objets. De par leurs performances et leur fiabilité, la technologie Flash constitue, à l'heure actuelle, la référence en matière de mémoire non volatile. Cependant, le coût élevé des équipements en microélectronique rend impossible leur amortissement sur une génération technologique. Ceci incite l’industriel à adapter des équipements d’ancienne génération à des procédés de fabrication plus exigeants. Cette stratégie n’est pas sans conséquence sur la dispersion des caractéristiques physiques (dimension géométrique, épaisseur…) et électriques (courant, tension…) des dispositifs. Dans ce contexte, le sujet de ma thèse est d’optimiser et de réduire la variabilité d’une nouvelle architecture mémoire non volatile ultra basse consommation.Cette étude vise à poursuivre les travaux entamés par STMicroelectronics sur le développement, l’étude et la mise en œuvre de boucles de contrôle de type Run-to-Run (R2R) sur une nouvelle cellule mémoire ultra basse consommation. Afin d’assurer la mise en place d’une régulation pertinente, il est indispensable de pouvoir simuler l’influence des étapes du procédé de fabrication sur le comportement électrique des cellules en s’appuyant sur l’utilisation d’outils statistiques ainsi que sur une caractérisation électrique pointue. / The global semiconductor market is experiencing steady growth due to the development of consumer electronics and the wake of the non-volatile memory market. The importance of these memory products has been accentuated since the beginning of the 2000s by the introduction of nomadic products such as smartphones or, more recently, the Internet of things. Because of their performance and reliability, Flash technology is currently the standard for non-volatile memory. However, the high cost of microelectronic equipment makes it impossible to depreciate them on a technological generation. This encourages industry to adapt equipment from an older generation to more demanding manufacturing processes. This strategy is not without consequence on the spread of the physical characteristics (geometric dimension, thickness ...) and electrical (current, voltage ...) of the devices. In this context, the subject of my thesis is “Optimization and reduction of the variability of a new architecture ultra-low power non-volatile memory”.This study aims to continue the work begun by STMicroelectronics on the improvement, study and implementation of Run-to-Run (R2R) control loops on a new ultra-low power memory cell. In order to ensure the implementation of a relevant regulation, it is essential to be able to simulate the process manufacturing influence on the electrical behavior of the cells, using statistical tools as well as the electric characterization.

Emerging memory technologies are being intensively investigated for extending Moore\'s law in the next decade. The conductive bridge random access memory (CBRAM) is one of the most promising candidates. CBRAM shows unique nanoionics-based filamentary switching mechanism. Compared to flash memory, the advantages of CBRAM include excellent scalability, low power consumption, high OFF-/ON-state resistance ratio, good endurance, and long retention. Besides the nonvolatile memory applications, resistive switching devices implement the function of memristor which is the fourth basic electrical component. This research presents the characterization and modeling of Cu/TaOx/Pt resistive switching devices. Both Cu and oxygen vacancy nanofilaments can conduct current according to the polarity of bias voltage. The volatile resistive switching phenomenon has been observed on Cu/TaOx/delta-Cu/Pt devices and explained by a flux balancing model. The resistive devices are also connected in series and in anti-parallel manner. These circuit elements are tested for chaotic neural circuit. The quantum conduction has been observed in the I-V characteristics of devices, evidencing the metallic contact between the nanofilament and electrodes. The model of filament radial growth has been developed to explain the transient I-V relation and multilevel switching in the metallic contact regime. The electroforming/SET and RESET processes have been simulated according to the mechanism of conductive filament formation and rupture and validated by experimental results. The Joule and Thomson heating effects have also been investigated for the RESET processes. / Ph. D.

Resistive random access memory (RRAM), based on a two-terminal resistive switching device with a switching element sandwiched between two electrodes, has been an attractive candidate to replace flash memory owing to its simple structure, excellent scaling potential, low power consumption, high switching speed, and good retention and endurance properties. However, due to the current limited understanding of the device mechanism, RRAMs research are still facing several issues and challenges including instability of operation parameters, the relatively high reset current, the limited retention and the unsatisfactory endurance. In this study, we investigated the switching mechanisms, conditions and applications of oxygen vacancy (Vo) filament formation in resistive memories. By studying the behavior of conductive Vo nanofilaments in several metal/oxide/metal resistive devices of various thicknesses of oxides, a resulting model supported by the data postulates that there are two distinct modes of creating oxygen vacancies: i) a conventional bulk mode creation, and ii) surface mode of creating oxygen vacancies at the active metal-dielectric interface. A further investigation of conduction mechanism for the Vo CF only based memories is conducted through insertion of a thin layer of titanium into a Pt/ Ta2O5/Pt structure to form a Pt/Ti/ Ta2O5/Pt device. A space charge limited (SCL) conduction model is used to explain the experimental data regarding SET process at low voltage ranges. The evidence for existence of composite copper/oxygen vacancy nanofilaments is presented. The innovative use of hybrid Vo/Cu nanofilament will potentially overcome high forming voltage and gas accumulation issues. A resistive floating electrode device (RFED) is designed to allow the generation of current/voltage pulses that can be controlled by three independent technology parameters. Our recent research has demonstrated that in a Cu/TaOx/Pt resistive device multiple Cu conductive nanofilaments can be formed and ruptured successively. Near the end of the study, quantized and partial quantized conductance is observed at room temperature in metal-insulator-metal structures with graphene submicron-sized nanoplatelets embedded in a 3-hexylthiophene (P3HT) polymer layer. As an organic memory, the device exhibits reliable memory operation with an ON/OFF ratio of more than 10. / Ph. D.

Recently, active matrix flat-panel displays are widely used in consumer electronic products. With increasing popularity of flat-panel displays, market competition becomes more intense and demands for high performance flat-panel displays are increasing. Low-temperature polysilicon (LTPS) with higher mobility, as well as drive current can integrate electric circuit, such as controllers and memory on glass substrate of display to achieve the purpose of system on panel (SOP). Thus, flat-panel displays can be more compact, while reducing reliability issues and lowering production costs. In this dissertation, we studied the nonvolatile memory for system on panel applications and reducing cost of memory by increasing the memory density or reducing the processing steps. Therefore, we proposed several modes of operation in nonvolatile memory. First, we use channel hot-electron (CHE) to inject electrons into the nitride layer that¡¦s above source or drain sides of SONOS thin film transistor (TFT). Thus, we can increase the memory density by storing two-bit state in a memory cell. In this study, the two-bit memory effect is clearly observed for devices with a shorter gate length after CHE programming; however, the two-bit memory effect is absent in devices with a longer gate length. The gate-length-dependent two-bit memory effect is related to the location of injected electrons in the nitride layer. When electrons are injected into the nitride layer above the channel, they can create an additional energy barrier in the channel thus increasing the threshold voltage of the device to perform the programming operations. However, if electrons are injected into the depletion region at the P-N junction between the drain and the channel, the energy barrier induced by electrons is not significant when exchanging the source and drain electrodes to measure the memory status, and the program effect is not as significant. When the channel length is shorten, the built-in potential between the source and the channel can be decreased, the energy barrier caused by programmed electrons can affect electrons in the channel and increase the threshold voltage. Therefore, the two-bit memory effect can be seen in devices with the shorter gate length after CHE programming. Secondly, we stored charges in the body of the thin film transistor to make the conventional thin-film transistors become a non-volatile memory. This method does not need a floating gate or a tunneling oxide in the memory cell; therefore the memory cost can be reduced. In this study, we used trap-assisted band-to-band thermionic field emission enhanced by self-heating in TFT to produce electron-hole pairs. The hole will be separated by a vertical field under the gate and be injected into the body of TFT to complete the programming operation. The erasing operation is performed by applying a lateral electric field between the source/drain to remove holes in the body of TFT. Thirdly, we proposed an edge-FN tunneling method to allow SONOS TFT possess not only a pixel switch but also a two-bit nonvolatile memory function in a display panel, thus causing the memory density to increase. In this study, we used a channel FN tunneling to program the SONOS TFT. Because the electric field in the gate-to-drain overlap region is larger than that in the channel region, it will cause a smoother electron injection into the nitride layer inside of the gate-to-drain overlap region, which also increases the gate-induced drain leakage (GIDL) current. The edge-FN tunneling method is used to erase electrons in the gate-to-drain overlap region, by doing so, the GIDL current has decreased. The memory status at the source/drain side is determined by the corresponding GIDL current of the SONOS TFT. Fourthly, we stored electrons in the nitride layer at source, channel, and drain regions of SONOS TFT to make sure that TFT possess a three-bit memory effect in a unitary cell, which also allows the memory density to increase significantly. In this study, programming and erasing operations in the source/drain region are performed by channel hot-electron injection and edge-FN tunneling method, while that in the channel region are accomplished by channel FN tunneling. The memory status in the source/drain is determined by the corresponding GIDL current, while that in the channel region by threshold voltage of the device The memory density for the device operated by proposed method can be further increased. In addition, if we store a number of N different types of electrons in those three regions mentioned above, there are N3 status can be stored in a memory cell. The memory density can beyond conventional multi-level-cell (MLC) flash memory. Two-bit memory effect per cell in a MLC flash memory can be achieved by storing four quantitative electrons in the floating gate of the memory device. If we store four quantitative electrons in the nitride layer at source, channel, and drain regions of SONOS TFT, we can obtain 64 memory states or 6-bit memory effect in a memory cell. Thus, the proposed concept is promising to storage the messages in a memory cell beyond four-bit.

Logic-in-memory circuits promise to overcome the von-Neumann bottleneck, which constitutes one of the limiting factors to data throughput and power consumption of electronic devices. In the following we present four-input logic gates based on only two ferroelectric FETs (FeFETs) with hafnium oxide as the ferroelectric material. By utilizing two complementary inputs, a XOR and a XNOR gate are created. The use of only two FeFETs results in a compact and nonvolatile design. This realization, moreover, directly couples the memory and logic function of the FeFET. The feasibility of the proposed structures is revealed by electrical measurements of HKMG FeFET memory arrays manufactured in 28nm technology.

During the last decade ferroelectrics based on doped hafnium oxide emerged as promising candidates for realization of ultra-low-power non-volatile memories. Two spontaneous polarization states occurring in the material that can be altered by applying electrical fields rather than forcing a current through and the materials compatibility to CMOS processing are the main benefits setting the concept apart from other emerging memories. 1T1C ferroelectric random access memories (FeRAM) as well as 1T FeFET concepts are under investigation. In this article the application of hafnium based ferroelectric memories in different flavours and their ranking in the memory landscape are discussed.

Der zunehmende Bedarf nach digitalen Speichermedien macht die Erforschung von neuen Materialien für zukünftige Technologien von nichtflüchtigen Speichern nötig. Hierfür eignen sich zum Beispiel Metall-Nanopartikel, die in organischen Halbleiterschichten eingebettet sind. Aufgrund der bistabilen Schaltbarkeit der Leitfähigkeit von Metall-Nanopartikeln lassen sie sich in Abhängigkeit der elektrischen Umgebungsbedingungen entweder in einen niedrig- oder einen hochleitenden Zustand schalten. Bisher wurden verschiedene Modelle entwickelt, um den Schaltmechanismus von Speichern mit einem organischen Matrixmaterial zu erklären, jedoch fehlt bislang ein konsistentes Bild zum Verständnis des Schaltvorgangs. Die vorliegende Arbeit  untersucht die Rolle des Raumladungsfeldes ausgehend von Metall-Nanopartikeln in Bauelementen. Dazu wurde eine Reihe von Experimenten zur Bestimmung der elektronischen und elektrischen Eigenschaften durchgeführt, um die tatsächliche Rolle des Raumladungsfeldes aufzuklären. Mit Hilfe von Röntgen- und UV-Photoelektronenspektroskopie wurde die Wechselwirkung zwischen den Metall-Nanopartikeln und den prototypischen organischen Halbleiterschichten detailliert untersucht. Unter Verwendung der bereits untersuchten Materialien wurden Bauelemente hergestellt und charakterisiert. Die Ergebnisse zeigen, dass der allgemein vorgeschlagene Mechanismus bezüglich der Aufladung/Entladung von Metall-Nanopartikeln als Ursache für die elektrische Bistabiliät in einem zweipoligen Bauteil ausgeschlossen werden kann. Stattdessen stützt dieses Ergebnis den alternativen Mechanismus der Filamentbildung. Zur Untersuchung der Skalierbarkeit der Speicher im Nanometerbereich wurden die Strukturen durch das Abscheiden der Materialien bei streifendem Einfall präpariert. Die entsprechenden Nanospeicher wurden elektrisch charakterisiert und zeigten Bistabilität. Folglich sind diese Nanspeicher besonders attraktiv für zukünftige Technologien in Hinblick auf hohe Speicherdichten. / The increasing need to store digital information has triggered research into the exploration of new materials for future non-volatile memory (NVM) technologies. For instance, metal nanoparticles (MNPs) embedded into organic semiconductors are suitable for novel memory applications because they were found to display bistable resistive switching. Different switching models were hitherto developed to explain the fundamental mechanisms at work in resistive NVMs. This thesis explores specifically the role of space-charge field due to the charging of MNPs as rationale for resistive switching in two-terminal devices. A series of experiments on the electronic and electrical properties of devices were conducted in order to reveal whether this mechanism is, indeed, at play in resistance switching. Photoelectron spectroscopy provided detailed information about the interaction between gold nanoparticles (AuNPs) with prototypical organic semiconductors used in optoelectronics. The study of the electronic valence structures provided evidence of a space-charge due to the charging of AuNPs. Furthermore, it is found that charge-neutrality of AuNPs can be dynamically re-established upon illumination, through electron transfer from excitons. Devices were built with the same materials investigated by photoemission spectroscopy and electrical characterization was conducted. Despite the previously demonstrated ability to optically change the charging state of the AuNPs, the devices do not display any bistability. This finding provides evidence that the commonly proposed charging/decharging mechanism of MNPs can be excluded as cause for electrical bistability in NVM devices. In order to explore the scaling of resistive NVMs into the nanometric range, glancing angle deposition technique was employed. The nano-NVMs were electrically characterized and it is proved to manifest resistive bistability. These finding make nano-NVMs highly appealing for future high-density memory technology.