Les conditionneurs alternatifs – continu à absorption sinusoïdale (PFC) pour les applications critiques se distinguent par un haut niveau de performances tel que les THD réduits, un haut rendement et une bonne fiabilité. Leur importance est d’autant plus nécessaire qu’une continuité de service des alimentations est requise même en présence d’une défaillance interne de composant. Deux types de structures associées à leur commande sont réalisés à cet effet, les structures à redondance parallèle et les structure à redondance en série. Elles consistent respectivement en l’ajout d’un bras d’interrupteur dans le cas de la redondance parallèle, qui est une option plus compliquée et en une suppression d’une cellule de commutation dans le deuxième cas. L’étude présentée ici, consiste en premier lieu en une exploration et une évaluation de nouvelles familles de topologies multi-niveaux, caractérisée par un partitionnement cellulaire en série. Ces nouvelles topologies, ainsi que leurs variantes, comportent au moins une redondance structurelle avec des cellules mono-transistor à défaut de commande non critique et symétriques à point-milieu. Elles sont donc génériques pour la mise en parallèle et l’extension en triphasé. Cependant, elles sont pour la plupart peu compétitives à cause des composants qui sont souvent surdimensionnés et donc plus onéreuses, en comparaison avec la structure PFC Double-Boost 5 Niveaux à composants standards 600 V (brevetée par l’INPT – LAPLACE –CNRS en 2008) que nous étudions. Cette dernière constitue le meilleur compromis entre un bon rendement et une maîtrise des contraintes en mode dégradé. Sur le plan théorique nous montrons que le seul calcul de fiabilité basé uniquement sur un critère de premier défaut est inadapté pour décrire ce type de topologie. La prise en compte de la tolérance de panne est nécessaire et permet d'évaluer la fiabilité globale sur une panne effective (i.e. au second défaut). L'adaptation de modèles théoriques de fiabilité à taux de défaillance constant mais prenant en compte, au niveau de leurs paramètres, le report de contrainte en tension et l'augmentation de température qui résulte d'un premier défaut, permet de chiffrer en valeur relative, le gain obtenu sur un temps court. Ce résultat est compatible avec les systèmes embarqués et la maintenance conditionnelle. Un prototype monophasé de PFC double-boost 5 niveaux à commande entièrement numérique et à MLI optimisée reconfigurable en temps réelle a été réalisé afin de valider l’étude. Il permet une adaptation automatique de la topologie de 5 à 4 puis 3 niveaux par exemple. Ce prototype a également servi de test d'endurance aux transistors CoolMos et diodes SiC volontairement détruits dans des conditions d'énergie maîtrisée et reproductibles. D’autres campagnes d'endurance en modes dégradés ont été réalisées en laboratoire sur plusieurs centaines d’heures en utilisant ce même prototype. Nous nous sommes axés sur la détection de défauts internes et le diagnostic (localisation) rapide, d'une part par la surveillance directe et le seuillage des tensions internes (tensions flottantes) et d'autre part, par la détection d’harmoniques (amplitude et phase) en temps réel. Ces deux techniques ont été intégrées numériquement et évaluées sur le prototype, en particulier la seconde qui ne requiert qu'un seul capteur. Enfin, nous proposons une nouvelle variante PFC expérimentée en fin de mémoire, utilisant deux fois moins de transistors et de drivers pour les mêmes performances fréquentielles au prix d'un rendement et d'une répartition des pertes légèrement moins favorable que la structure brevetée. / This work is an exploration and an evaluation of new variants of multi-level AC/DC topologies (PFC) considering their global reliability and availability: electrical safety with an internal failure and post-failure operation. They are based on a non-differential AC and centre tap connection that led to symmetrical arrangement cells in series. These topologies permit an intrinsic active redundancy between cells in a same group and a segregation capability between the two symmetrical groups of cells. More again, they are modular and they can be paralleled and derived to any number of levels. Only single low-voltage (600V) transistor pear cell is used avoiding the short-circuit risk due to an unwanted control signal. Comparisons, taking into account losses, distribution losses, rating and stresses (overvoltage and over-temperature) during the post-operation are presented. Results highlight the proposed 5-level Double-Boost Flying Capacitor topology. This one was patented at the beginning of thesis, as a solution with the best compromise. On the theoretical side, we show that the reliability calculation based only on a "first fault occurrence" criterion is inadequate to really describe this type of topology. The inclusion of fault tolerance capability is needed to evaluate the overall reliability law (i.e. including a second failure). The adaptation of theoretical models with constant failure rate including overvoltage and over-temperature dependencies exhibit an increasing of the reliability over a short time. This property is an advantage for embedded systems with monitoring condition. Local detection and rapid diagnosis of an internal failure were also examined in this work. Two methods are proposed firstly, by a direct flying caps monitoring and secondly, by a realtime and digital synchronous demodulation of the input sampled voltage at the switching frequency (magnitude and phase). Both techniques have been integrated on FPGA and DSP frame and evaluated on a AC230V-7kW DC800V – 31kHz lab. set-up. We put forward the interest of the second method which only uses one input voltage sensor. Finally, we propose in this dissertation a new generic X-level PFC Vienna using, in 5-level version, half transistors and drivers for identical input frequency and levels. At the cost of a slight increase of losses and density losses, this topology appears very attractive for the future. A preliminary lab. set-up and test were also realized and presented at the end of the thesis.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / This Master Thesis presents the study and proposes a digital control system applied to the PFC boost converter operating in mixed conduction mode. The motivation to this subject, a bibliographic review of the existing current control techniques and the objectives of this work are presented in the first chapter. The control system is composed of a current loop, which has the objectives to provide low harmonic content to the input current and high power factor to the converter, and a voltage loop, which has the goal to regulate the output voltage of the converter. Initially, the study of the conduction modes of the PFC boost converter, highlighting their operation conditions, and details of the mixed conduction mode operation are showed. Next, two predictive digital current controllers with feedforward action are approached in details, including the equations deduction, block diagram, operation process, design, simulation results and parametric variation analysis. A comparative analysis between both controllers is also accomplished. The proportional-integral voltage controller is presented following, comprising its structure, design and simulation results. After, issues related to the practical implementation of the converter and control system, as the converter design and the control device programming, are shown. Finally, the experimental results obtained through the implementation of the proposed system, including the waveforms acquired using a prototype constructed in laboratory and the quality indexes as the power factor and the total harmonic distortion, are presented with the purpose to validate and prove the content of this work. / Esta Dissertação de Mestrado apresenta o estudo e propõe um sistema de controle digital para o conversor boost PFC operando no modo de condução mista. A motivação para este assunto, uma revisão bibliográfica das técnicas de controle de corrente existentes e os objetivos do trabalho são apresentados no capítulo introdutório. O sistema de controle é composto de uma malha de corrente, que tem por objetivo proporcionar baixo conteúdo harmônico para a corrente de entrada e alto fator de potência para o conversor, e uma malha de tensão, que tem por objetivo regular a tensão de saída do conversor. Inicialmente, o estudo dos modos de condução do conversor boost PFC, destacando as suas condições de operação, e detalhes da operação no modo de condução mista são mostrados. Em seguida, dois controladores digitais preditivos de corrente com ação feedforward são abordados em detalhes, incluindo o equacionamento, diagrama de blocos, funcionamento, projeto, resultados de simulação e análise da variação paramétrica. Uma análise comparativa entre ambos também é realizada. O controlador proporcional-integral de tensão é abordado na seqüência, compreendendo sua estrutura, projeto e resultados de simulação. Posteriormente, questões relativas à implementação prática do conversor e do sistema de controle, como o projeto do conversor e a programação do dispositivo de controle, são mostradas. Por fim, os resultados experimentais obtidos com a implementação do sistema proposto, incluindo as formas de onda adquiridas em um protótipo construído em laboratório e os índices de qualidade como o fator de potência e a distorção harmônica total, são apresentados com o intuito de validar e comprovar o conteúdo deste trabalho.

Ce travail propose une description et une analyse de la phonologie du français parlé à Bordeaux et dans son agglomération, à partir d’un corpus d’enquêtes réalisées suivant la méthodologie et le protocole développés dans le cadre du Projet de la Phonologie du Français Contemporain (PFC), développé par Jacques Durand (ERSS, Université de Toulouse-Le Mirail), Bernard Laks (MoDyCo, Université de Paris X) et Chantal Lyche (Universités d’Oslo et de Tromsø). Plusieurs aspects de la phonologie du français bordelais sont abordés, en prenant en compte la diversité diastratique des locuteurs et les différences diaphasiques des tâches linguistiques, en particulier la question des lois de position des voyelles, la liaison et le schwa. L’étude détaillée ici se base sur l’analyse d’entretiens enregistrés réalisés auprès de dix-huit adultes venant de Bordeaux et de son agglomération. Les participants à cette enquête ont été interviewés entre juin et juillet 2015, selon le protocole du Projet PFC, et les enregistrements ont été transcrits, codés et analysés par l’auteure, également selon les protocoles du Projet PFC. Les locuteurs ont été sélectionnés de manière à représenter une diversité équilibrée en termes d’âge, de sexe, de niveaux d’études, de milieu socioéconomique/culturel et de situation géographique pendant l’enfance. Nous observons des tendances dans la réalisation de plusieurs phénomènes phonologiques. La liaison et le schwa sont utilisés plus en lecture de texte qu’en conversation libre. Cependant, le schwa est réalisé le moins dans la lecture de la liste de mots. Une analyse diachronique révèle que les Bordelais actuels suivent la Loi de Position davantage comparé aux locuteurs décrits dans les travaux précédents. Nous constatons que l’âge apparaît comme un facteur statistiquement significatif dans la diversité diastratique pour cet échantillon de locuteurs. Nous considérons également la variation diatopique, diaphasique et diachronique. Ce travail contribue à l’étude de la variation du français parlé aujourd’hui. / This study provides a description and an analysis of the French spoken in Bordeaux and the surrounding communities, based on a corpus of studies following the methodology and the protocol developed within the framework of the Contemporary French Phonology (PFC) Project, developed by Jacques Durand (ERSS, University of Toulouse-Le Mirail), Bernard Laks (MoDyCo, University of Paris X) and Chantal Lyche (University of Oslo and University of Tromsø). Several aspects of the phonology of Bordeaux French are studied, taking into consideration the sociolinguistic diversity of the speakers and the stylistic differences of the linguistic tasks, specifically the Loi de Position for vowels, liaison and schwa. The study detailed here is based on the analysis of audio-recorded interviews of eighteen adults from Bordeaux and the surrounding communities. The participants in this study were interviewed between June and July 2015, according to PFC protocol, and the recordings were transcribed, coded and analyzed by the author, also in accordance with PFC protocol. The speakers were selected in order to represent a balanced diversity in terms of age, sex, level of education, socioeconomic/cultural background, and childhood neighborhood. We observe patterns in terms of the realization of several phonological phenomena. Liaison and schwa are used more in the reading task than in conversation. However, schwa is used the least in the word list. A diachronic analysis reveals that the people from Bordeaux today follow the Loi de Position more than the speakers described in previous research did. We conclude that age is shown to be a statistically significant sociolinguistic factor for this sample of speakers. We also take into account variation in terms of geography, style and chronology. This work contributes to the study of phonological variation in spoken French today.

With the development of information technology, power management for telecom and computer applications become a large market for power supply industries. To meet the performance and reliability requirement, distributed power system (DPS) is widely adopted for telecom and computer systems, because of its modularity, maintainability and high reliability. Due to limited space and increasing power consumption, power supplies for telecom and server systems are required to deliver more power with smaller volume. As the key component of DPS system, front-end AC/DC converter is under the pressure of continuously increasing power density. For conventional industry practices, some limitations prevents front-end converter meeting the power density requirement. In this dissertation, different techniques have been investigated to improve power density of front-end AC/DC converters. For PFC stage, at low switching frequency, PFC inductor size is large and limits the power density. Although increasing switching frequency can dramatically reduce PFC inductor size, EMI filter size might be larger at higher switching frequency because of the change of noise spectrum. Since the relationship between EMI filter size and PFC switching frequency is unclear for industry, PFC circuits always operate with switching frequency lower than 150 kHz. Based on the EMI filter design method, together with a simple EMI noise prediction model, relationship between EMI filter corner frequency and PFC switching frequency was revealed. The analysis shows that switching frequency of PFC circuit should be higher than 400 kHz, so that both PFC inductor and EMI filter size can be reduced. Although theoretical analysis and experimental results verify the benefits of high switching frequency PFC, it is essential to find a suitable topology that allows high switching frequency operation while maintains high efficiency. Three PFC topologies, single switch PFC, three-level PFC with range switch and dual Boost PFC, were evaluated with analysis and experiments. By using advanced semiconductor devices, together with proposed control methods, these topologies could achieve high efficiency at high switching frequency. Thus, the benefits of high frequency PFC can be realized. In front-end converter, large holdup time capacitor size is another barrier for power density improvement. To meet the holdup time requirement, bulky holdup time capacitor is normally used to provide energy during holdup time. Holdup time capacitor requirement can be reduced by using wider input voltage range DC/DC converte. Because LLC resonant converter can realized with input voltage range without sacrificing its normal operation efficiency, it becomes an attractive solution for DC/DC stage of front-end converters. Moreover, its small switching loss allows it operating at MHz switching frequency and achieves smaller passive component size. However, lack of design methodology makes the topology difficult to be implemented. An optimal design methodology for LLC resonant converter has been developed based on the analysis on the circuit during normal operation condition and holdup time. The design method is verified by a 1 MHz switching frequency LLC resonant converter with 76W/in3 power density. When front-end converter operates at high switching frequency, negative effects of circuit parasitics become more pronounced. By integrating active devices together with their gate drivers, Active Integrated power electronics module (IPEM) can largely reduce circuit parasitics. Therefore, switching loss and voltage stress on switching devices can be reduced. Moreover, IPEM concept can be extended into passive integration and EMI filter integration By using this power integration technology, power density and circuit performance of front-end converter can be improved, which is verified by theoretical analysis and experimental results. / Ph. D.

<p>Neuroimaging studies of episodic memory, or memory of events from our personal past, have predominantly focused their attention on medial temporal lobe (MTL). There is growing acknowledgement however, from the cognitive neuroscience of memory literature, that regions outside the MTL can support episodic memory processes. The medial prefrontal cortex is one such region garnering increasing interest from researchers. Using behavioral and functional magnetic resonance imaging measures, over two studies, this thesis provides evidence of a mnemonic role of the medial PFC. In the first study, participants were scanned while judging the extent to which they agreed or disagreed with the sociopolitical views of unfamiliar individuals. Behavioral tests of associative recognition revealed that participants remembered with high confidence viewpoints previously linked with judgments of strong agreement/disagreement. Neurally, the medial PFC mediated the interaction between high-confidence associative recognition memory and beliefs associated with strong agree/disagree judgments. In an effort to generalize this finding to well-established associative information, in the second study, we investigated associative recognition memory for real-world concepts. Object-scene pairs congruent or incongruent with a preexisting schema were presented to participants in a cued-recall paradigm. Behavioral tests of conceptual and perceptual recognition revealed memory enhancements arising from strong resonance between presented pairs and preexisting schemas. Neurally, the medial PFC tracked increases in visual recall of schema-congruent pairs whereas the MTL tracked increases in visual recall of schema-incongruent pairs. Additionally, ventral areas of the medial PFC tracked conceptual components of visual recall specifically for schema-congruent pairs. These findings are consistent with a recent theoretical proposal of medial PFC contributions to memory for schema-related content. Collectively, these studies provide evidence of a role for the medial PFC in associative recognition memory persisting for associative information deployed in our daily social interactions and for those associations formed over multiple learning episodes. Additionally, this set of findings advance our understanding of the cognitive contributions of the medial PFC beyond its canonical role in processes underlying social cognition.</p> / Dissertation

Induktion präfrontaler Dysfunktion bei gesunden Probanden durch inhibitorische TMS: Eine NIRS-Messung / Induction of a prefrontal dysfunction on healthy subjects with inhibitory TMS: a near-infrared spectroscopy (NIRS) study

Le Carbure de Silicium, par ses propriétés intrinsèques, offre des perspectives dans le domaine de l'électronique de puissance à même de supplanter le Silicium aujourd'hui sollicité à ses limites. En particulier, le Carbure de Silicium (SiC) permet la réalisation de diodes réunissant la technologie Schottky et supportant une haute tension. Après avoir resitué la filière du SiC dans son contexte, on présente dans ce travail les éléments de physique du semiconducteurappliqués à la diode Schottky SiC et justifiant les propriétés et le dimensionnement du composant. Le comportement électrique statique et dynamique des diodes Schottky SiC est ensuite comparé à l'état de l'art des diodes bipolaires en Silicium, et une simulation fine de la cellule de commutation est présentée. Le comportement électrothermique des diodes Schottky SiC est analysé dans la partie suivante à l'aide d'un outil de simulation dédié, permettant d'intégrer à la fois les phénomènes d'emballement thermique propres aux composants majoritaires et les propriétés de haute tenue en température du SiC, pour fournir une évaluation de la densité de courant utile des diodes. Enfin, la dernière partie propose une évaluation de la technologie Schottky SiC DANS UNE APPLICATION pfc, suivant le régime de fonctionnement du convertisseur. Une amélioration visant à exploiter au mieux les propriétés de cette nouvelle diode dans le PFC est ensuite présentée.

This study aims to design a Shunt Semi-Active Power Factor Correction Circuits , which can be applied to high power circuit by low switching frequency. The designed circuit can avoid power loss working with high switching frequency when using the method of active power factor correction .The experimental configuration based on DSP is applied to a compressor of air conditioner with varied load. The simulation check the developed circuit using Ispice . Both of the experimental and simulation results have guaranteed the derived configuration reach the expected goals.

A single-stage high-power-factor electronic ballast with class E inverter is proposed for driving the fluorescent lamp. The circuit configuration is obtained from the integration of a buck-boost converter for power-factor- correction (PFC) and a class E resonant inverter for ballasting. The integrated ballast circuit requires only one active power switch and simple control. Operating the buck-boost converter in discontinuous conduction mode (DCM) at a fixed frequency, the electronic ballast can achieve nearly unity power factor. With pulse-width-modulation (PWM), the electronic ballast can provide an appropriate filament current for preheating, a high voltage for ignition, and then a desired lamp current for steady-state operation. An additional control circuit is included to eliminate the glow current during preheating stage. The operation of the ballast-lamp circuit is analyzed by fundamental approximation. Computer simulations are made and design equations are derived on basis of the power-dependent resistance model of the fluorescent lamp. With carefully designed circuit parameters, the active power switch can be switched on at zero current to reduce the switching losses leading to a higher efficiency. An experimental circuit designed for a PL-27W compact fluorescent lamp is built and tested to verify the computer simulations and analytical predictions. Experimental results show that satisfactory performances can be obtained on the proposed electronic ballast.

An auxiliary winding with an associated capacitor is added on the single-stage power factor corrector (PFC) based on fly-back conversion to reduce the ripple on the dc output voltage. The associated capacitor takes out partial energy at every switching cycle from the fly-back conversion and releases the stored energy to the load at the valley of the rectified line voltage. The negative effect of such an approach is that the converter does not draw a current from the AC line at the lower voltage near zero crossing, leading to deterioration in the power factor. This thesis analyzes how an auxiliary winding affects the voltage of the associated capacitor, which in turn changes the cut-in angle of the input current and thus the power factor of the AC source. To facilitate the implementation, the fly-back converter is operated at the boundary conduction mode (BCM). A design example is given for the 24 V, 48 W load, based on the derived equations. The laboratory circuit is built and tested to verify the computer simulations and analytical predictions. The experimental results confirm the circuit analyses on the converter performances.