Operating batteries in parallel is attempted to overcome the problems with conventionally used battery bank, in which batteries are connected in series. The problems and the management with the operation of serial connected batteries are first addressed. The related topics to the parallel configuration are reviewed. Then, the parallel configuration with battery power modules is proposed. The battery power module can be realized with different dc-to-dc converters for different applications. When batteries are charged in parallel, the problem of over-charge can be avoided. With parallel operation, the discharging currents of the batteries are independently controlled but are coordinated to execute a full amount load current. This allows for scheduling the discharging profiles under different operating conditions. As a result, a sophisticated discharging profile can be realized to utilize the available stored energy in batteries. On the other hand, some of the batteries may take rest or be isolated from the system for the detections at a time. This facilitates the estimations of the state of charge (SOC) and the state of health (SOH). Moreover, the completely exhausted or damaged batteries can be isolated from the battery power supply bank without interrupting the system operation. Experiments are carried out on battery power modules with lead-acid batteries incorporating with associated buck-boost converters. The experimental results demonstrate that a more efficient utilization of battery energy can be achieved. On the other hand, a more reasonable management can be done with simple estimation methods of the SOC and the SOH.

A novel battery power system configured by the battery power modules (BPMs) is proposed. Each BPM consists of a single battery pack or a battery bank equipped with an associated DC/DC converter. The output ports of BPMs can be connected in series for the high voltage applications, or in parallel to cope with a higher power or energy. For a large scale battery power system, a number of BPMs can be arrayed with combination of series and parallel connections to meet the load requirements. These all configurations allow the BPMs be operated individually. Consequently, the discharging currents of the batteries can be independently controlled, but coordinated to provide a full amount of the load current. The performances of BPMs connected in both parallel and series at outputs are analyzed theoretically and discussed from the experimental results. Batteries operating independently do not suffer from charge imbalance, and thus can avoid being over-charged or over-discharged, so that the life cycle can be prolonged. Furthermore, sophisticated discharging profiles such as intermittent currents can be realized to equalize the charges and thus to efficiently utilize the available stored energy in batteries. During the operation period, some of the batteries may take rest or be isolated from the system for the open-circuit measurement, facilitating the estimation of the state-of-charge (SOC) and the evaluation of the state-of-health (SOH). With the benefit of independent operation, the BPMs can be discharged with a scheduled current profile, such as intermittent discharging. The investigation results show that the average current plays the most important role in current discharging. By detecting the battery voltage at the break time, an SOC estimation method based on the dynamically changed open-circuit voltage exhibits an acceptable accuracy in a shorter time with considerations of the previous charging/discharging currents and the depth-of- discharge (DOD). In addition, the coulomb counting method can be enhanced by evaluating the SOH at the exhausted and fully charged states, which can be intended on the independently operated BPMs. Through the experiments that emulate practical operations, the SOC estimation methods are verified on lead-acid batteries and lithium-ion batteries to demonstrate the effectiveness and accuracy.

Parasitic inductance in power modules generates voltage spikes and current ringing during switching which cause extra stress in power electronic devices, increase electromagnetic interference (EMI), and degrade the performance of the power converter system. As newer power devices have faster switching speeds and higher power ratings, the effect of the parasitic inductance of the power module is more pronounced. This dissertation proposes a novel packaging method for power electronics modules based on the concepts of novel switching cells: P-cell and N-cell. It can reduce the stray inductance in the current commutation path in a phase-leg module and hence improve the switching behavior. Taking an insulated gate bipolar transistor (IGBT) as an example, two phase-leg modules, specifically a conventional module and a P-cell and N-cell based module were designed. Using Ansoft Q3D Extractor, electromagnetic simulation was carried out to extract the stray inductance from the two modules. An ABB 1200 V / 75 A IGBT model and a diode model were built for simulation study. Circuit parasitics were extracted and modeled. Switching behavior with different package parasitics was studied based on the Saber simulation. Two prototype phase-leg modules were fabricated. The parasitics were measured using a precision impedance analyzer. The measurement results agree with the simulation very well. A double pulse tester was built in laboratory. Several approaches were used to reduce the circuit and measuring parasitics. From the switching characteristics of the two modules, it was verified that the larger stray inductance in the layout causes higher voltage overshoot during turn off, which in turn increases the turn off losses. Multichip (two in parallel) IGBT modules applying novel switching cells was also designed. The parasitics were extracted and compared to a conventional design. The overall loop inductance was reduced in the proposed module. However, the mismatch of the paralleled branches was larger.

Circuit assembly and packaging technologies for power electronics have not kept pace with those for digital electronics. Inside those packaged power devices as well as the state-of-the-art power modules, interconnection of power chips is accomplished with wirebonds. Wirebonds in power devices and modules are prone to resistance, noise, parasitic oscillations, fatigue and eventual failure. Furthermore, there has been an increase demand for higher power density and better efficiency for power converters. Power semiconductor suppliers have been concentrating on improving device structure, density, and process technology to lower the on-resistance of MOSFETs and voltage drop of IGBTs. Recent advances made in power semiconductor technology are pushing packaging technology to the limits for performance of these power systems since the resistance and parasitics contribution by the package and the wirebonds are roughly the same as that on the silicon. In recent years, an integrated systems approach to standardizing power electronics components and packaging techniques in the form of power electronics building blocks has emerged as a new concept in the area of power electronics. As a result, it has been envisioned that the packaging of three-dimensional high-density multichip modules (MCMs) can meet the requirement for future power electronics systems. However, the conventional wirebond interconnected power devices are excluded from three-dimensional MCMs because of their large size, limited thermal management, and incompatible processing techniques. On the other hand, advanced solder joint area-array technologies, such as flip-chip technology, has emerged in microelectronics industry due to increased speed, higher packaging density, and performance, improved reliability and low cost these technologies offer. With all these benefits to offer, solder joint area-array technology has yet to be implemented for power electronics packaging. Therefore, the first objective of this study is to design and develop a solder joint area-array interconnection technique for power chips. Solder joint reliability is a major concern for area array technologies and power chip interconnection, thus the second objective of this study is to evaluate solder joint reliability, investigate the fatigue failure behavior of solder joint and improve solder joint reliability by developing a new solder bumping process for improved solder joint geometry, underfilling solder joint with encapsulant and applying flexible substrate in the assembly. The third objective is the implementation of solder joint interconnection technique in developing chip-scale power packages and a three-dimensional integrated power electronics module structure. Solder joint area array interconnection for power chips has been designed with the considerations of parasitic resistance and inductance reduction, current handling capability, thermal management, reliability improvement and manufacturability. A new solder joint fabrication process, which is able to produce high standoff hourglass-shaped solder joint that consists of an inner cap, middle ball and outer cap, as well as the conventional solder bumping process have been successfully developed for power chips by using stencil printing. This solder bumping technology is compatible with the existing surface-mount assembly operations and potentially low cost. The fabricated solder joints have been characterized for their structure integrity, mechanical strength and electrical performances. Solder joint reliability has been improved by optimizing solder joint geometry, underfilling flipped power chip and utilizing compliant substrate. Solder joint reliability was evaluated using accelerated temperate cycling and adhesion tests. The interfaces of the triple-stacked solder joints were examined using scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDX) for the integrity of the joint. Acoustic microscopy imaging (nondestructive evaluation) was utilized to examine the quality of the bonded interfaces and to detect cracks and other defects before and during accelerated fatigue tests. Adhesion strength of both single bump barrel-shaped and stacked hourglass-shaped solder joints to bonding pads was characterized and analyzed. It was found that stacked hourglass-shaped solder joint have higher fracture stress than barrel-shaped solder joint. This verifies that hourglass-shaped solder joint has lower stress singularity at the interface between the solder bump and the silicon die as well as at the interface between the solder bump and substrate than barrel-shaped solder joint, especially around the corners of the interfaces. Furthermore, the adhesion strength of barrel-shaped solder joint decreases much faster than that of high standoff hourglass-shaped solder joint under temperature cycling, which indicates that the latter has high reliability than the former. Our accelerated temperature cycling test clearly shows that solder joint fatigue failure process consists of three phases: crack initiation, crack propagation and catastrophic failure. Solder joint geometry, underfilling and substrate flexibility were proved to affect solder joint reliability. The effects of solder joint shape and standoff height on reliability have been systematically studied experimentally for the first time. Our experimental results indicated that both hourglass shape and great standoff height could improve solder joint fatigue lifetime, with standoff height being the more effective factor. The fatigue lifetime of high standoff hourglass-shaped solder joint is improved mainly by prolonged crack propagation time, with slight improvement in crack initiation time. Experimental data suggested that shape is the dominant factor affecting crack initiation time while standoff height is the major factor influencing crack propagation time. Underfilling and flexible substrate improved the lifetime of both barrel and hourglass-shaped solder joints. The effect of underfill on solder joint reliability is well known in microelectronics packaging field. However, for the first time, it is reported in this study that flex substrate could improve solder joint reliability. It has been found that flex substrate bucks during temperature cycling and thus reduces thermal strain in solder joints, which in turn improves solder joint fatigue lifetime. Chip scale packaging can enable a few very important concepts and advantages in power electronics packaging. It offers high silicon to package footprint ratio, provides a known good die solution to power chips, improves electrical as well as thermal performance and creates an opportunity for power component standardization. Two kinds of chip-scale power packages have been developed in this research. One is called cavity down flip chip on flex; the other is termed Die Dimensional Ball Grid Array (D2BGA). Both utilize solder joint as chip-level interconnection. Electrical tests show that the VCE(sat) of the high speed IGBT chip-scale packages is improved by 20% to 30% by eliminating the device¡¯s wirebonds and other external interconnections, such as leadframe. Double-sided cooling is realized in these CSPs. Temperature cycling test shows that the CSPs are reliable. Integrated power electronics modules (IPEMs) are envisioned as integrated power modules consisting of power semiconductor devices, power integrated circuits, sensors, and protection circuits for a wide range of power electronics applications, such as inverters for motor drives and converters for power processing equipment. We have developed a three-dimensional approach, termed flip chip on flex (FCOF), for packaging high-performance IPEMs. The new concept is based on the use of solder joint (D2BGA chip scale package), not bonding wires, to interconnect power devices. This packaging approach has the potential to produce modules having superior electrical and thermal performance and improved reliability. We have demonstrated the feasibility of this approach by constructing half-bridge converters (consisting of two IGBTs, two power diodes, and a simple gate driver circuitry) which have been successfully tested at power levels over 30 kW. Switching tests have shown that parasitic inductance of the FCOF module has been reduced by 40% to 50% over conventional wire bond power modules. Better thermal management can be achieved in this three-dimensional power module structure. Compared with the state-of-the-art half-bridge power modules, the volume of the half-bridge FCOF power module is reduced by at least 65%. Reliability test shows that this flip chip on flex power module structure is potentially more reliable than wire bond power module. / Ph. D.

Le variateur de vitesse est l’un des convertisseurs de puissance le plus utilisé en industrie ; il alimente les pompes, les ventilateurs, les convoyeurs, les ascenseurs …etc. Dans ces systèmes de conversion, les modules de puissance intégrants des composants IGBT représentent la partie cœur de conversion de l’énergie électrique AC/AC. En fonctionnement, ils sont sujets à des conditions fonctionnelles et environnementales sévères (cycles de température, humidité, vibrations …etc.). En raison de la puissance dissipée au niveau de leurs composants (IGBTs et diodes), le module subit des déformations d’origine thermomécanique, qui s’accumulent au fil du temps en limitant sa durée de vie et en impactant sur sa fiabilité. Dès lors, les industriels se trouvent non seulement face au développement des composants robustes et fiables, mais surtout être capable à élaborer des outils permettant la programmation des phases de maintenance. Dans cette thématique s’inscrivent les travaux de cette thèse. Durant laquelle nous essayons de répondre à ce besoin, en proposant une méthodologie de prédiction de durée de vie restante d’un module de puissance intégré au sein d’un variateur de vitesse de 15kW. En effet, nous développons un modèle de durée de vie restante nécessitant une modélisation électrothermique du système, un algorithme de comptage de cycles de température appelé le Rainflow et une loi de durée de vie obtenue à partir des tests de vieillissement. Le paramètre de durée de vie est ensuite calculé en appliquant la règle de Miner. Enfin nous proposons des stratégies de prise en compte de l’effet de dégradation pour ce modèle. / The motor drive is one of the most used power converters in industry; it drives pumps, fans, conveyers, elevators …etc. In this conversion systems, power modules integrating IGBT devices represent the core part in the AC/AC electrical energy conversion. During operation, they are subjected to severe functional and environmental conditions (temperature cycles, humidity, vibrations …etc.). Due to the dissipated power at the level of their devices (IGBTs and diodes), the module undergoes deformations of a thermomechanical origin, which accumulate over time limiting its lifetime and impacting on its reliability. Therefore, manufacturers are not faced only with the development of robust and reliable components, but above all they need to be able to develop tools for maintenance phases scheduling. In this scope, the thesis work is focused. During it, we try to bring a solution to this need, so we propose a remaining lifetime prediction methodology for an integrated power module inside a 15kW motor drive.Therefore, we develop a remaining lifetime model that requires an electrothermal modeling of the system, a temperature cycles counting algorithm called by the Rainflow and a lifetime law obtained from the aging tests. The lifetime parameter is then calculated by applying the Miner’s rule. Finally, we propose strategies to take into account the degradation effect on this model.

No description available.

Medium-voltage silicon carbide power devices, due to their higher operational temperature, higher blocking voltage, and faster switching speed, promise transformative possibilities for power electronics in grid-tied applications, thereby fostering a more sustainable, resilient, and reliable electric grid. The pursuit of increasing power density, however, escalates the blocking voltage and shrinks the module size, consequently posing unique insulation challenges for the medium voltage power module packaging. The state-of-the-art solutions, such as altering the geometry of the insulated-metal-substrates or thickening or stacking them, exhibit limited efficacy, inflate manufacturing costs, raise reliability concerns, and increase thermal resistance. This dissertation explores a material-based approach that utilizes a nonlinear resistive polymer nanocomposite field-grading coating to enhance insulation performance without compromising thermal performance for medium-voltage power modules. The studied polymer nanocomposite is a mutual effort of this research and NBE Technologies. Instead of using field-grading materials as encapsulation, a thin film coating (about 20 μm) can be achieved by painting the polymer nanocomposite solution to the critical regions to grade the electric field and extend the range of the applicability of the bulk encapsulation. A polymer nanocomposite's electrical properties were characterized and found theoretically and experimentally to be effective in improving the insulation performance or increasing the partial discharge inception voltage, of direct-bonded-copper substrates for medium-voltage power modules. By applying the polymer nanocomposite coating on the direct-bonded- copper triple-point edges, the partial discharge inception voltages of a wide range of direct-bonded-coppers increased by 50-100%. To assure its effectiveness for heated power modules during operation, this field-grading effect was then evaluated at elevated temperatures up to 200°C and found almost unchanged. The nanocomposite's long-term efficacy was further corroborated by voltage endurance tests. Building on these promising characterizations, functional power modules were designed, fabricated, and tested, employing the latest packaging techniques, including double-sided cooling and silver-sintering. Prototypes of 10-kV and 20-kV silicon carbide diode modules confirmed the practicality and efficacy of the polymer nanocomposite. The insulation enhancements observed at the module level mirrored those at the substrate level. Moreover, the polymer nanocomposite coating enabled modules to use insulated-metal-substrates with at least 100% thinner ceramic, resulting in a reduction of at least 30% in the junction-to-case thermal resistance of the module. Subsequently, to test the nanocomposite's performance during fast-switching transients (> 300 V/ns), 15-kV silicon carbide MOSFET modules were designed, fabricated, and evaluated. These more complex modules passed blocking tests, partial discharge tests, and double-pulse tests, further validating the feasibility of the nonlinear resistive polymer nanocomposite field-grading for medium-voltage power modules. In summary, this dissertation presents a comprehensive evaluation of a nonlinear resistive polymer nanocomposite field-grading coating for medium-voltage power modules. The insights and demonstrations provided in this work bring the widespread adoption of this packaging concept for medium-voltage power modules significantly closer to realization. / Doctor of Philosophy / This dissertation delves into a novel approach to improving the resilience and reliability of our electric grid by employing medium-voltage silicon carbide power devices. These power devices, due to their superior performance at higher temperatures and faster switching speeds, can revolutionize grid-tied power electronics. However, the challenge lies in safely packaging these devices, given their high blocking voltage and compact size. To address this, the study explores an innovative solution that uses a material called a nonlinear resistive polymer nanocomposite. This nanocomposite can improve insulation and endure high temperatures, promising a significant boost in performance for these power devices. The study reveals that applying this nanocomposite coating to the edges of direct- bonded-copper, a component of the power module, can enhance the insulation performance by 50-100%. Building on these findings, we designed, made, and tested functional power modules, using cutting-edge packaging techniques that we developed. The tests confirmed the practicality and effectiveness of the polymer nanocomposite, leading to insulation improvements on both the substrate and module levels. Importantly, this coating also reduced the thermal resistance of the module by at least 30%, signifying a more efficient operation. Then we evaluated the nanocomposite's performance during fast-switching transients in more complex silicon carbide modules. The modules passed multiple tests, further validating the feasibility of the nanocomposite coating for medium-voltage power modules. In essence, this dissertation uncovers a promising approach to more efficient and resilient power module packaging, paving the way for potential widespread adoption in the power electronics industry.

Three growing power electronics applications have massive requirements for properly operating their medium-voltage and high-voltage systems: electric transportation, renewable energy, and the power grid. Their needs include dense power systems with higher efficiency and higher voltage and current devices. This requires devices with higher switching frequencies to lower the size of the passives in the converter and devices that can withstand higher operating temperatures as components move closer together to improve power densities. Devices that achieve higher switching speeds and lower specific on-state resistances also reduce losses. Wide bandgap devices (WBG) like silicon carbide (SiC) have a higher bandgap, higher electric field strength, higher thermal conductivity, and lower carrier concentration than silicon (Si). This allows for higher temperature operation, faster switching, higher voltage blocking, and lower power losses, directly meeting the requirements of the previously noted applications. However, the current packaging schemes are limiting the ability of SiC to operate in these applications by applying packaging schemes used for Si. Therefore, it is critical to use and refine advanced packaging techniques so that WBG devices can better operate and meet the growing demands of these power electronic applications. Low-inductance, wirebond-less, high-density, scalable modules are possible due to advanced packaging methods. While beneficial to the operation and design, these techniques introduce new challenges to the fabrication process. This requires refinement to improve the yield of sandwich-structure modules with wirebond-less interconnects. For this module, encapsulated, silver-sintered substrates reduce the peak electric field within the package, improving the partial discharge inception voltage to meet insulation requirements. It is essential to have a uniform bondline between the substrates to achieve all bond connections and improve reliability. Silver sintering is also used to attach the molybdenum (Mo) post interconnects. These interconnects allow for sandwich-structure modules with low inductances; however, they have tolerance variation from manufacturing and bondline thicknesses, which become problematic for multi-chip power modules with an increased number of die and posts. The variation results in tilt, causing some posts to disconnect altogether. Additionally, soldering MCPMs involves a large thermal mass that the soldering reflow profile from a datasheet does not account for. Ultimately, these fabrication concerns can result in misalignment or disconnected post interconnects to the top substrate. Post interconnect planarity and alignment are vital for this multi-chip power module to avoid open or shorted connections that can derate switch positions. This thesis aims to refine each packaging step in assembling a wirebond-less, multi-chip power module. The bond uniformity of silver (Ag) sintering is addressed in dried preform and wet paste cases. The soldering methods are explored and improved by creating a modified reflow profile for large thermal masses and introducing pressure to reduce bondline variation and voiding content. The entire sandwich structure module is analyzed in a statistical tolerance analysis to understand which component introduces the most variation and height mismatch, providing insight as to which packaging techniques need further control to improve the yield of multi-chip power modules. / Master of Science / The electrification of many systems worldwide has increased the need for compact, efficient power electronics. Their applications span electric transportation, renewable energy systems, grid applications, and data centers, to name a few medium-voltage applications. Wide bandgap (WBG) semiconductors can outperform silicon in these applications, offering higher temperature robustness, higher efficiency performance, and higher voltage capabilities. The faster switching will reduce the size and weight of the converters containing these devices. However, using typical packaging schemes such as wirebonds will limit the potential of WBG devices in these applications. Advanced packaging techniques have been developed to increase the electric field strength, reduce the power loop inductances, reduce electromagnetic interference from fast-switching transients, and improve the power densities of multi-chip power modules for medium voltage and current applications. However, these packaging techniques are not trivial to implement and have resulted in a low yield of these modules. This thesis aims to refine each packaging step in assembling a wirebond-less, multi-chip power module. The bond uniformity of silver sintering is addressed in cases of dried preform and wet paste. The soldering methods are explored and improved by creating a modified reflow profile for large thermal masses and introducing pressure to reduce bondline variation and voiding content. The entire sandwich structure module is analyzed in a statistical tolerance analysis to understand which component introduces the most variation and height mismatch, providing insight as to which packaging techniques need further control to improve the yield of multi-chip power modules.

This study focuses on development a planar power module with low thermal impedance and thermo-mechanical stress for high density integration of power electronics systems. With the development semiconductor technology, the heat flux generated in power device keeps increasing. As a result, more and more stringent requirements were imposed on the thermal and reliability design of power electronics packaging. In this dissertation, a boundary-dependent RC transient thermal model was developed to predict the peak transient temperature of semiconductor device in the power module. Compared to conventional RC thermal models, the RC values in the proposed model are functions of boundary conditions, geometries, and the material properties of the power module. Thus, the proposed model can provide more accurate prediction for the junction temperature of power devices under variable conditions. In addition, the transient thermal model can be extracted based on only steady-state thermal simulation, which significantly reduced the computing time. To detect the peak transient temperature in a fully packaged power module, a method for thermal impedance measurement was proposed. In the proposed method, the gate-emitter voltage of an IGBT which is much more sensitive to the temperature change than the widely used forward voltage drop of a pn junction was monitored and used as temperature sensitive parameter. A completed test circuit was designed to measure the thermal impedance of the power module using the gate-emitter voltage. With the designed test set-up, in spite of the temperature dependency of the IGBT electrical characteristics, the power dissipation in the IGBT can be regulated to be constant by adjusting the gate voltage via feedback control during the heating phase. The developed measurement system was used to evaluate thermal performance and reliability of three different die-attach materials. From the prediction of the proposed thermal model, it was found that the conventional single-sided power module with wirebond connection cannot achieve both good steady-state and transient thermal performance under high heat transfer coefficient conditions. As a result, a plate-bonded planar power module was designed to resolve the issue. The comparison of thermal performance for conventional power module and the plate-bonded power module shows that the plate-bonded power module has both better steady-state and transient thermal performance than the wirebonded power module. However, due to CTE mismatch between the copper plate and the silicon device, large thermo-mechanical stress is induced in the bonding layer of the power module. To reduce the stress in the plate-bonded power module, an improved structure called trenched copper plate structure was proposed. In the proposed structure, the large copper plate on top of the semiconductor can be partitioned into several smaller pieces that are connected together using a thin layer copper foil. The FEM simulation shows that, with the improved structure, the maximum von Mises stress and plastic strain in the solder layer were reduced by 18.7% and 67.8%, respectively. However, the thermal impedance of the power module increases with reduction of the stress. Therefore, the trade-off between these two factors was discussed. To verify better reliability brought by the trenched copper plate structure, twenty-four samples with three different copper plate structures were fabricated and thermally cycled from -40°C to 105°C. To detect the failure at the bonding layer, the curvature of these samples were measured using laser scanning before and after cycling. By monitoring the change of curvature, the degradation of bonding layer can be detected. Experimental results showed that the samples with different copper plate structure had similar curvature before thermal cycle. The curvatures of the samples with single copper plate decreased more than 80% after only 100 cycles. For the samples with 2 × 2 copper plate and the samples with 3 × 3 copper plate, the curvatures became 75.8% and 77.5% of the original values, respectively, indicating better reliability than the samples with single copper plate. The x-ray pictures of cross-sectioned samples confirmed that after 300 cycles, the bonding layer for the sample with single copper plate has many cracks and delaminations starting from the edge. / Ph. D.

Conventional wire bond power modules have limited application for high-current operation, mainly because of their poor thermal management capability. Planar power modules have excellent thermal management capability and lower parasitic inductance, which means that the planar packaging method is desirable for high-power applications. For these reasons, a planar power module for an automotive motor drive system was developed, and a gate-driver circuit with an over-current protection was planned to integrate into the module. This thesis discusses a current-sensing method for the planar module, and the integrated gate driver circuit with an over-current protection. After reviewing several current-sensing methods, it becomes clear that most popular current-sensing methods, such as the Hall-Effect sensor, the current transformer, the Shunt resistor, and Rogowski coils, exhibit limitations for the planar module integration. For these reasons, a giant magneto resistive (GMR) magnetic-field detector was chosen as a current-sensing method. The GMR sensor utilizes the characteristics of the giant magneto resistive (GMR) effect in that it changes its resistance when it is exposed to the magnetic-flux. Because the GMR resistor can be fabricated at the wafer level, a packaged GMR sensor is very compact when compared with conventional current sensors. In addition, the sensor detects magnetic-fields, which does not require direct contact to the current-carrying conductor, and the bandwidth of the sensor can be up to 1 MHz, which is wide enough for the switching frequencies of most of motor drive applications. However, there are some limiting factors that need to be considered for accurate current measurement: • Operating temperature • Magnetic-flux density seen by a GMR resistor • Measurement noise If the GMR sensor is integrated into the power module, the ambient temperature of the sensor will be highly influenced by the junction temperature of the power devices. Having a consistent measurement for varying temperature is important for module-integrated current sensors. An experiment was performed to see the temperature characteristics of a GMR sensor. The measurement error caused by temperature variation was quantified by measurement conditions. This thesis also proposes an active temperature error compensation method for the best use of the GMR sensor. The wide current trace of the planar power module helps to reduce the electrical/thermal resistance, but it hinders having a strong and constant magnetic-field-density seen by the GMR sensor. In addition, the eddy-current effect will change the distribution of the current density and the magnetic-flux-density. These changes directly influence the accurate measurement of the GMR sensor. Therefore, analyzing the magnetic-flux distribution in the planar power module is critical for integrating the GMR sensor. A GMR sensor is very sensitive to noise, especially when it is sensing current flowing in a wide trace and exposed to external fields, neither of which can be avoided for the operation of power modules. Post-signal processing is required, and the signal-conditioning circuit was designed to attenuate noise. The signal-conditioning circuit was designed using an instrumentation amplifier, and the circuit attenuated most of the noise that hindered accurate measurement. The over-current protection circuit along with the gate driver circuit was designed, and the concept was verified by experiments. The main achievements of this study can be summarized as: • Characterization of conventional current-sensing methods • Temperature characterization of the GMR resistor • Magnetic-flux distribution of the planar power module • Design of the signal-conditioning circuit and over-current protection circuit / Master of Science