The use of SMPS (Switched mode power supply) in embedded systems is continuously increasing. The technological requirements of these systems include simultaneously a very good voltage regulation and a strong compactness of components. SEPIC ( Single-Ended Primary Inductor Converter) is a DC/DC switching converter which possesses several advantages with regard to the other classical converters. Due to the difficulty in control of its 4th-order and non linear property, it is still not well-exploited. The objective of this work is the development of successful strategies of control for a SEPIC converter on one hand and on the other hand the effective implementation of the control algorithm developed for embedded applications (FPGA, ASIC) where the constraints of Silicon surface and the loss reduction factor are important. To do it, two non linear controls and two observers of states and load have been studied: a control and an observer based on the principle of sliding mode, a deadbeat predictive control and an Extended Kalman observer. The implementation of both control laws and the Extended Kalman observer are implemented in FPGA. An 11-bit digital PWM has been developed by combining a 4-bit Δ-Σ modulation, a 4-bit segmented DCM (Digital Clock Management) phase-shift and a 3-bit counter-comparator. All the proposed approaches are experimentally validated and constitute a good base for the integration of embedded switching mode converters

Made available in DSpace on 2016-12-12T17:38:31Z (GMT). No. of bitstreams: 1 SUZANA RIBAS DE ALMEIDA.pdf: 2655112 bytes, checksum: 346dca905796b24136deb70b7263fb5b (MD5) Previous issue date: 2012-02-15 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Nowadays the competition between companies is increasing. In a production system, efficiency, speed and flexibility are important means for cost reductions. The complexity of automation systems has been increasing, which makes necessary the implementation of more efficient control programs, free of errors and easy to maintain. However, in most practical applications the solution of these problems is dependent on designer's experience and doesn t follow a formal methodology, which results in programs with errors and difficulties to understand and maintain, since only the designer understands the adopted solutions. The Supervisory Control Theory (SCT) is a method extensively researched in academic circles for the synthesis of control logic of automated systems. It allows control problems to be solved in a formal way, ensuring a minimally restrictive and no blocking solution that meets the control specifications. However, this theory is not widely used in industrial environments yet, once the methods for implementation of supervisors obtained by TCS are still deficient. Thus, the intention of this Dissertation consists of showing a methodology for implementation of supervisory control in Programmable Logic Controllers (PLCs). In this work, the synthesis of supervisors is made in accordance to local modular approach, which brings the benefits of a formal methodology and allows exploring the modularity of the plant and the control specifications. The implementation is based on an architecture structured in three levels: supervisor, interface and system to be controlled. For the implementation in CLP three different programming languages are applied: the high-level languages Sequential Function Charts (SFC) and Structured Text and the low-level Ladder Diagram language in some parts. The development of the methodology was based on two works: a doctoral thesis by Vieira (2007) and master thesis by Cruz (2011) and brought together the advantages presented in each one of these. To compare the proposed methodology and the two mentioned methods, several tests were made on a manufacturing cell available at PUCPR and simulations on a PLC and computer as well. The results show that the use of the methodology proposed in this work makes possible to implement PLC programs that are able to treat all non-controllable events occurred in the system to be controlled and treat one controllable event by each control cell in the same scan cycle. Furthermore, the use of high-level languages results in a program of easier interpretation and maintenance, also enabling reutilization of codes. In this work some problems related to CLPs implementations are also showed and proposals for solving them are presented, as properties as well that, if accepted, ensure that the problem does not occur. / Hoje em dia a competitividade entre as empresas está cada vez maior. Em um sistema de produção, a eficácia, a velocidade e a flexibilidade são importantes, pois significam redução de custos. Os sistemas de automação atuais estão cada vez mais complexos, justificando a necessidade de programas de controle mais eficientes, sem erros e de fácil manutenção. Entretanto, na maioria das aplicações práticas a solução destes problemas é feita com base na experiência do projetista, não seguindo uma metodologia formal, o que resulta em programas com erros e de difícil entendimento e manutenção, uma vez que só o projetista entende perfeitamente as soluções adotadas. A Teoria de Controle Supervisório (TCS) é um método para a síntese da lógica de controle de sistemas automatizados. Ela permite que problemas de controle sejam solucionados de modo formal, garantindo uma solução minimamente restritiva e não bloqueante e que atenda às especificações de controle. Entretanto, esta teoria ainda não é amplamente adotada em ambientes industriais, sendo a carência de métodos de implementação dos supervisores obtidos via TCS um elemento que contribui para que isso aconteça. Assim, esta dissertação se propõe a apresentar uma metodologia de implementação de controle supervisório em Controladores Lógicos Programáveis (CLPs). Neste trabalho, a síntese de supervisores é feita de acordo com a abordagem modular local, que traz os benefícios de uma metodologia formal e ainda permite explorar a modularidade da planta e das especificações de controle. A implementação é baseada numa arquitetura estruturada em três níveis: supervisor, interface e sistema a ser controlado. Para a implementação em CLP são empregadas três linguagens distintas de programação, as linguagens de alto nível Sequential Function Charts (SFC) e Structured Text, bem como a linguagem Ladder Diagram em algumas partes. O desenvolvimento da metodologia foi baseado em dois trabalhos: a tese de doutorado de Vieira (2007) e a dissertação de mestrado de Cruz (2011) e permitiu reunir as vantagens apresentadas em cada um destes. Para comparação entre a metodologia proposta e as duas metodologias citadas, foram feitos diversos testes em uma célula de manufatura existente na PUCPR, bem como simulações em CLP e em computador. Os resultados mostram que a metodologia proposta neste trabalho permite a implementação de programas em CLP que, num mesmo ciclo de varredura, são capazes de tratar todos os eventos não controláveis ocorridos na planta e ainda um evento controlável por célula de controle. Além disso, o uso de linguagens de alto nível resulta em um programa de mais fácil interpretação e manutenção, possibilitando ainda o reaproveitamento de códigos. Nesta dissertação também são abordados alguns problemas de implementação da estrutura de controle supervisório em CLPs, apresentando-se propostas para solucioná-los, bem como propriedades que, se atendidas, garantem que o problema não ocorra.

This diploma thesis treats the possibilities of the black-white picture depiction in pseudo colors (Pseudocolor). The individual methods, software or hardware are described there and the detailed block scheme of the system Pseudocolor is suggested. The block scheme is created on the basis of gained theoretical knowledge. In the thesis, individual functional blocks of the scheme are described and their circuit designs are realized. Some of the functional blocks are simulated by the PSpice program and accompanied by corresponding signal process data. The suitable choice of the active and passive components is performed, from which the general integration of the system Pseudocolor is made. All the source materials for the realization of the device are given there – double-sided drawing of the printed circuit, layout and specification of the components.

Master’s thesis describes adaptive optimal controller design which change parameters of algorithm based on the system information regard for optimal criterion. Generally, the optimal controller solves the problem of minimum states vector. Problems of desired value and steady-state error are solved by variation in optimization algorithm.

Master’s thesis describes adaptive optimal controller design and it’s settings. Identification with principles of artificial intelligence and recursive least squares identification with exponential and directional forgetting are compared separately and as part of controller. Adaptive optimal controller is tested on physical model and compared with solidly adjusted PSD controller. Possibilities of implementation of adaptive optimal controller into programmable logic controller B&R are show and tested.

This Graduation Theses dissertate about a creation of a drawing documentation at the professional CAE EPLAN Electric P8 system. One original solution of a remote control and of motor-generator monitoring with a mobile phone, short SMS-aided in this case, was used as an example of the drawing documentation. As has allready been noted in previous Bachelor Thesis, this application can be use not only for a remote control of a motor-generator, but this solution is suitable for other electric devices too, which are out of reach of an attendance for example. In our case a generator with 6kVA power is concerned with rated output voltage 230Vac and rated current 25A. The system of a remote control has the advantage that it is created from standard components (electric instruments, a PLC – programmable automat, a GSM modem, an operating panel and the respective program in the PLC).

L’utilisation des alimentations à découpage (SMPSs : switched mode power supplies) est à présent largement répandue dans des systèmes embarqués en raison de leur rendement. Les exigences technologiques de ces systèmes nécessitent simultanément une très bonne régulation de tension et une forte compacité des composants. SEPIC (Single-Ended Primary Inductor Converter) est un convertisseur à découpage DC/DC qui possède plusieurs avantages par rapport à d’autres convertisseurs de structure classique. Du fait de son ordre élevé et de sa forte non linéarité, il reste encore peu exploité. L’objectif de ce travail est d’une part le développement des stratégies de commande performantes pour un convertisseur SEPIC et d’autre part l’implémentation efficace des algorithmes de commande développés pour des applications embarquées (FPGA, ASIC) où les contraintes de surface silicium et le facteur de réduction des pertes sont importantes. Pour ce faire, deux commandes non linéaires et deux observateurs augmentés (observateurs d’état et de charge) sont exploités : une commande et un observateur fondés sur le principe de mode de glissement, une commande prédictive et un observateur de Kalman étendu. L’implémentation des deux lois de commande et l’observateur de Kalman étendu sont implémentés sur FPGA. Une modulation de largeur d’impulsion (MLI) numérique à 11-bit de résolution a été développée en associant une technique de modulation Δ-Σ de 4-bit, un DCM (Digital Clock Management) segmenté et déphasé de 4-bit, et un compteur-comparateur de 3-bit. L’ensemble des approches proposées sont validées expérimentalement et constitue une bonne base pour l’intégration des convertisseurs à découpage dans les alimentations embarquées. / The use of SMPS (Switched mode power supply) in embedded systems is continuously increasing. The technological requirements of these systems include simultaneously a very good voltage regulation and a strong compactness of components. SEPIC ( Single-Ended Primary Inductor Converter) is a DC/DC switching converter which possesses several advantages with regard to the other classical converters. Due to the difficulty in control of its 4th-order and non linear property, it is still not well-exploited. The objective of this work is the development of successful strategies of control for a SEPIC converter on one hand and on the other hand the effective implementation of the control algorithm developed for embedded applications (FPGA, ASIC) where the constraints of Silicon surface and the loss reduction factor are important. To do it, two non linear controls and two observers of states and load have been studied: a control and an observer based on the principle of sliding mode, a deadbeat predictive control and an Extended Kalman observer. The implementation of both control laws and the Extended Kalman observer are implemented in FPGA. An 11-bit digital PWM has been developed by combining a 4-bit Δ-Σ modulation, a 4-bit segmented DCM (Digital Clock Management) phase-shift and a 3-bit counter-comparator. All the proposed approaches are experimentally validated and constitute a good base for the integration of embedded switching mode converters

Testing, verification and validation of sensors, components and systems is vital in the early-stage development of new cars with computer-in-the-car architecture. This can be done with the help of the existing technique, hardware-in-the-loop (HIL) testing which, in the close loop testing case, consists of four main parts: Real-Time Simulation Platform, Sensor Simulation PC, Interface Unit (IU), and unit under test which is, for instance, a Vehicle Computing Unit (VCU). The purpose of this degree project is to research and develop a proof of concept for in-house development of an image injection solution (IIS) on the IU in the HIL testing environment. A proof of concept could confirm that editing, customizing, and having full control of the IU is a possibility. This project was initiated by Volvo Cars to optimize the use of the HIL testing environment currently available, making the environment more changeable and controllable while the IIS remains a static system. The IU is an MPSoC/FPGA based design that uses primarily Xilinx hardware and software (Vivado/Vitis) to achieve the necessary requirements for image injection in the HIL testing environment. It consists of three stages in series: input, image processing, and output. The whole project was divided in three parts based on the three stages and carried out at Volvo Cars in cooperation by three students, respectively. The author of this thesis was responsible for the output stage, where the main goal was to find a solution for converting, preferably, AXI4 RAW12 image data into data on CSI2 format. This CSI2 data can then be used as input to serializers, which in turn transmit the data via fiber-optic cable on GMSL2 format to the VCU. Associated with the output stage, extensive simulations and hardware tests have been done on a preliminary solution that partially worked on the hardware, producing signals in parts of the design that could be read and analyzed. However, a final definite solution that fully functions on the hardware has not been found, because the work is at the initial phase of an advanced and very complex project. Presented in this thesis is: important theory regarding, for example, protocols CSI2, AXI4, GMSL2, etc., appropriate hardware selection for an IIS in HIL (FPGA, MPSoC, FMC, etc.), simulations of AXI4 and CSI2 signals, comparisons of those simulations with the hardware signals of an implemented design, and more. The outcome was heavily dependent on getting a certain hardware (TEF0010) to transmit the GMSL2 data. Since the wrong card was provided, this was the main problem that hindered the thesis from reaching a fully functioning implementation. However, these results provide a solid foundation for future work related to image injection in a HIL environment.