Global ETD Search

1	Vysokorychlostní paketové DMA přenosy do FPGA / High-Speed Packet Data DMA Transfers to FPGA Kubálek, Jan January 2020 (has links) This thesis deals on the design, implementation, testing and measuring of a firmware module for FPGA chips, which enables DMA transfers of network data from computer RAM to the FPGA chip placed on a network interface card. These transfers are carried out using a PCIe bus on the speed of up to 100 Gbps with the possible support of speeds 200 Gbps and 400 Gbps. The goal of this technology is to allow network data processing for the purpose of maintenance of backbone network nodes and data centers. The module is designed so it can be used on different types of FPGA chips, mainly those produced by companies Xilinx and Intel. Ultrascale+; DMA; Stratix10; FPGA; PCIe
2	Portning av ett Linuxbaserat system / Porting of a Linux based system Johansson, Anton, Stenzelius, Kalle January 2022 (has links) The project is about embedded systems in self-driving vehicles which is a growing andcurrent area. This is important as the automation of vehicles can make different sectorssuch as the mining and logistics industry more effective. This work relates to the topicas it aims to improve part of the self-driving software stack by replacing Ubuntu with aless resource-intensive Linux based system. The main goal of this work is to implementand document improvements. The work contains a research part where advantages anddisadvantages are compared against each other, followed by an implementation thatiteratively solved one problem at a time.The result became instructions and documentation describing the choices madefor a less resource demanding Linux based system. It also includes instructions anddocumentation for two different application that are part of the software stack. / Projektet handlar om inbyggda system i självkörande fordon vilket är ett växande ochaktuellt område. Det är viktigt då automatiseringen av fordon kan effektivisera mångaolika sektorer som till exempel gruv- och logistikindustrin. Detta arbete relaterar tillämnet då det har som mål att effektivisera en del av den självkörande mjukvarustackengenom att byta ut Ubuntu till ett mindre resurskrävande Linux-system. Huvudmålet meddetta arbete är att implementera och dokumentera förbättringar. Arbetet innehåller en ut-redningsdel där för- och nackdelar jämförs mot varandra följt av en implementationsdelsom iterativt hanterar ett problem i taget.Resultatet blev instruktioner och dokumentation över de val som tagits för ett mindreresurskrävande Linux-system samt instruktioner och dokumentation över två applikatio-ner som är en del av mjukvarustacken. yocto linux petalinux xilinx embedded system zcu102 ultrascale ultrascale+ zynq yocto linux petalinux xilinx inbyggt system zcu102 ultrascale ultrascale+ zynq Computer Systems Datorsystem Computer and Information Sciences Data- och informationsvetenskap Computer Sciences Datavetenskap (datalogi)
3	Evaluation of high-level synthesis tools for generation of Verilog code from MATLAB based environments Bäck, Carl January 2020 (has links) FPGAs are of interest in the signal processing domain as they provide the opportunity to run algorithms at very high speed. One possible use case is to sort incoming data in a measurement system, using e.g. a histogram method. Developing code for FPGA applications usually requires knowledge about special languages, which are not common knowledge in the signal processing domain. High-level synthesis is an approach where high-level languages, as MATLAB or C++, can be used together with a code generation tool, to directly generate an FPGA ready output. This thesis uses the development of a histogram as a test case to investigate the efficiency of three different tools, HDL Coder in MATLAB, HDL Coder in Simulink and System Generator for DSP in comparison to the direct development of the same histogram in Vivado using Verilog. How to write and structure code in these tools for proper functionality was also examined. It has been found that all tools deliver an operation frequency comparable to a direct implementation in Verilog, decreased resource usage, a development time which decreased by 27% (HDL Coder in MATLAB), 45% (System Generator) and 64% (HDL Coder in Simulink) but at the cost of increased power consumption. Instructions for how to use all three tools has been collected and summarised. / I ingångssteget på ett mätsystem är det av intresse att använda en FPGA för att uppnå höga hastigheter på de oundvikliga datafiltrering och sorterings algoritmer som körs. Ett problem med FPGAer är att utvecklingen ställer höga krav på specifik kunskap gällande utvecklingsspråk och miljöer vilket för en person specialiserad inom t.ex. signalbehandling kan saknas helt. HLS är en metodik där högnivåspråk kan användas för digital design genom att nyttja ett verktyg för automatgenerering av kod. I detta arbete har utveckling av ett histogram använts som testfall för att utvärdera effektivitet samt designmetodik av tre olika HLS verktyg, HDL Coder till MATLAB, HDL Coder till Simulink och System Generator for DSP. Utvecklingen i dessa verktyg har jämförts mot utvecklingen av samma histogram i Vivado, där språket Verilog använts. Arbetets slutsater är att samtliga verktyg som testats leverar en arbetsfrekvens som är jämförbar med att skriva histogrammet direkt i Verilog, en minskad resursanvändning, utvecklingstid som minskat med 27% (HDL Coder i MATLAB), 45% (System Generator) och 64% (HDL Coder i Simulink) men med en ökad strömförbrukning. En sammanställning av instruktioner för utveckling med hjälp av verktygen har även gjorts. HLS System Generator for DSP Histogram Xilinx Zynq UltraScale+ FPGA design workflow Hardware Description Language Coder HDL Coder Field Programmable Gate Arrays Image processing Elektroteknik och elektronik
4	A 1.8 ps Time-to-Digital Converter (TDC) Implemented in a 20 nm Field-Programmable Gate Array (FPGA) Using a Ones-Counter Encoding Scheme with Embedded Bin-Width Calibrations and Temperature Correction Sven, Engström January 2020 (has links) This thesis investigates the use of field-programmable gate arrays (FPGAs) to implement a time-to-digital converter (TDC) with on-chip calibration and temperature correction.Using carry-chains on the Xilinx Kintex UltraScale architecture to create a tapped delay line (TDL) has previously been proven to give good time resolution.This project improves the resolution further by using a bit-counter to handle bubbles in the TDL without removing any taps.The bit counter also adds the possibility of using a wave-union approach previously dismissed as unusable on this architecture.The final implementation achieves an RMS resolution of 1.8 ps. time-to-digital time-to-digital converter TDC 1.8 ps field-programmable gate array FPGA 20 nm Xilinx Kintex UltraScale tapped delay line TDL taps carry-chain ones-counter bit-counter bubbles wave-union embedded temperature correction Annan elektroteknik och elektronik
5	Modeling, Simulation, and Injection of Camera Images/Video to Automotive Embedded ECU : Image Injection Solution for Hardware-in-the-Loop Testing Lind, Anton January 2023 (has links) Testing, verification and validation of sensors, components and systems is vital in the early-stage development of new cars with computer-in-the-car architecture. This can be done with the help of the existing technique, hardware-in-the-loop (HIL) testing which, in the close loop testing case, consists of four main parts: Real-Time Simulation Platform, Sensor Simulation PC, Interface Unit (IU), and unit under test which is, for instance, a Vehicle Computing Unit (VCU). The purpose of this degree project is to research and develop a proof of concept for in-house development of an image injection solution (IIS) on the IU in the HIL testing environment. A proof of concept could confirm that editing, customizing, and having full control of the IU is a possibility. This project was initiated by Volvo Cars to optimize the use of the HIL testing environment currently available, making the environment more changeable and controllable while the IIS remains a static system. The IU is an MPSoC/FPGA based design that uses primarily Xilinx hardware and software (Vivado/Vitis) to achieve the necessary requirements for image injection in the HIL testing environment. It consists of three stages in series: input, image processing, and output. The whole project was divided in three parts based on the three stages and carried out at Volvo Cars in cooperation by three students, respectively. The author of this thesis was responsible for the output stage, where the main goal was to find a solution for converting, preferably, AXI4 RAW12 image data into data on CSI2 format. This CSI2 data can then be used as input to serializers, which in turn transmit the data via fiber-optic cable on GMSL2 format to the VCU. Associated with the output stage, extensive simulations and hardware tests have been done on a preliminary solution that partially worked on the hardware, producing signals in parts of the design that could be read and analyzed. However, a final definite solution that fully functions on the hardware has not been found, because the work is at the initial phase of an advanced and very complex project. Presented in this thesis is: important theory regarding, for example, protocols CSI2, AXI4, GMSL2, etc., appropriate hardware selection for an IIS in HIL (FPGA, MPSoC, FMC, etc.), simulations of AXI4 and CSI2 signals, comparisons of those simulations with the hardware signals of an implemented design, and more. The outcome was heavily dependent on getting a certain hardware (TEF0010) to transmit the GMSL2 data. Since the wrong card was provided, this was the main problem that hindered the thesis from reaching a fully functioning implementation. However, these results provide a solid foundation for future work related to image injection in a HIL environment. ADAS AD ADS HIL Hardware in the loop Hardware-in-the-loop ECU VCU Automotive Embedded System Systems Camera Image Video Injection FPGA MPSoC Vivado Vitis VHDL Volvo Cars FMC HPC LPC MIPI CSI2 GMSL2 AMBA AXI4 Xilinx RTL Implementation Synthesis Intelectual Property IP Vehicle computing unit Electronic control unit TEB0911 TEF0007 TEF0010 CSI2 Tx CSI2 Tx Subsystem Zynq SerDes AXI4 AXI4-Lite Programmable Logic PL Processor System PS C C++ Video test pattern generator VTPG Axi traffic generator ATG Ultrascale+ Virtual input/output VIO Integrated logic analyzer ILA Interface Unit Embedded Systems Inbäddad systemteknik

1

Page generated in 0.0308 seconds