In this paper a test set embedding based on accumulator driven by an odd additive constant is presented. The problem is formulated around finding the location of the test pattern in the sequence generated by the accumulator, given a odd constant C and test set T, in terms of linear Diophantine equation of two variables. We show that the search space for finding the best constant corresponding to the shortest length, is greatly reduced. Experimental results show a significant improvement in run time with practically acceptable test length.

abstract: Built-in-Self-Test (BiST) for transmitters is a desirable choice since it eliminates the reliance on expensive instrumentation to do RF signal analysis. Existing on-chip resources, such as power or envelope detectors, or small additional circuitry can be used for BiST purposes. However, due to limited bandwidth, measurement of complex specifications, such as IQ imbalance, is challenging. In this work, a BiST technique to compute transmitter IQ imbalances using measurements out of a self-mixing envelope detector is proposed. Both the linear and non linear parameters of the RF transmitter path are extracted successfully. We first derive an analytical expression for the output signal. Using this expression, we devise test signals to isolate the effects of gain and phase imbalance, DC offsets, time skews and system nonlinearity from other parameters of the system. Once isolated, these parameters are calculated easily with a few mathematical operations. Simulations and hardware measurements show that the technique can provide accurate characterization of IQ imbalances. One of the glaring advantages of this method is that, the impairments are extracted from analyzing the response at baseband frequency and thereby eliminating the need of high frequency ATE (Automated Test Equipment). / Dissertation/Thesis / M.S. Electrical Engineering 2012

abstract: As integrated technologies are scaling down, there is an increasing trend in the process,voltage and temperature (PVT) variations of highly integrated RF systems. Accounting for these variations during the design phase requires tremendous amount of time for prediction of RF performance and optimizing it accordingly. Thus, there is an increasing gap between the need to relax the RF performance requirements at the design phase for rapid development and the need to provide high performance and low cost RF circuits that function with PVT variations. No matter how care- fully designed, RF integrated circuits (ICs) manufactured with advanced technology nodes necessitate lengthy post-production calibration and test cycles with expensive RF test instruments. Hence design-for-test (DFT) is proposed for low-cost and fast measurement of performance parameters during both post-production and in-eld op- eration. For example, built-in self-test (BIST) is a DFT solution for low-cost on-chip measurement of RF performance parameters. In this dissertation, three aspects of automated test and calibration, including DFT mathematical model, BIST hardware and built-in calibration are covered for RF front-end blocks. First, the theoretical foundation of a post-production test of RF integrated phased array antennas is proposed by developing the mathematical model to measure gain and phase mismatches between antenna elements without any electrical contact. The proposed technique is fast, cost-efficient and uses near-field measurement of radiated power from antennas hence, it requires single test setup, it has easy implementation and it is short in time which makes it viable for industrialized high volume integrated IC production test. Second, a BIST model intended for the characterization of I/Q offset, gain and phase mismatch of IQ transmitters without relying on external equipment is intro- duced. The proposed BIST method is based on on-chip amplitude measurement as in prior works however,here the variations in the BIST circuit do not affect the target parameter estimation accuracy since measurements are designed to be relative. The BIST circuit is implemented in 130nm technology and can be used for post-production and in-field calibration. Third, a programmable low noise amplifier (LNA) is proposed which is adaptable to different application scenarios depending on the specification requirements. Its performance is optimized with regards to required specifications e.g. distance, power consumption, BER, data rate, etc.The statistical modeling is used to capture the correlations among measured performance parameters and calibration modes for fast adaptation. Machine learning technique is used to capture these non-linear correlations and build the probability distribution of a target parameter based on measurement results of the correlated parameters. The proposed concept is demonstrated by embedding built-in tuning knobs in LNA design in 130nm technology. The tuning knobs are carefully designed to provide independent combinations of important per- formance parameters such as gain and linearity. Minimum number of switches are used to provide the desired tuning range without a need for an external analog input. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

FITNESSGRAM is a battery of fitness tests that assess if a child's fitness level is, according to a health standard, enough to be considered healthy. These tests include the five components of health-related fitness: aerobic endurance, muscular strength and muscular endurance, flexibility, and body composition. Students are not compared to each other, but to health fitness standards specific to their age and gender that indicate good health. The purpose of this qualitative study was to identify children's perceptions of FITNESSGRAM and determine if self-administration of this fitness test provides a positive experience for the students. Specifically, this study evaluated (a) students' perceptions of FITNESSGRAM, administered in a self-testing format, (b) children's understanding of the purpose of fitness testing, and (c) what effect participation in FITNESSGRAM had on students' perceptions of their personal health. This study used questionnaires (n = 78), and follow-up individual interviews (n = 45) to identify students' perceptions of FITNESSGRAM. Results using the constant comparative method identified four main categories: (a) administration of fitness testing, (b) the purpose of fitness testing, (c) components of fitness testing, and (d) overall influence of fitness testing. Findings showed that children clearly understood the importance and role of fitness testing, felt successful and were pleased with their results, preferred doing the tests with a partner or by themselves, and thought the fitness test was fun.

The rapid progress made in integrating enormous numbers of transistors on a single chip is making it possible for hardware designers to implement more complex hardware architectures in their designs. Nowadays digital telecommunication systems are implementing several forms of SOC (System-On-Chip) structures. These SOCs usually contain a microprocessor, several DSP cores (Digital-Signal-Processors), other hardware blocks, on-chip memories and peripherals. As new IC process technologies are deployed, with decreasing geometrical dimensions, the probabilities of hardware faults to occur during operation are increasing. Testing SOCs is becoming a very complex issue due to the increasing complexity of the design and the increasing need of a test mechanism that is able to achieve acceptable fault coverage in a short test application time with low power consumption without the use of external logic testers. As a part of the overall test strategy for a SOC, functional self-testing of a DSP core is considered in this project to be applied in the field. This test is used to verify whether fault indications in systems are caused by permanent hardware faults in the DSP. If so, the DSP where the fault is located needs to be taken out of operation, and the board it sits on will be later replaced. If not, the operational state can be restored, and the system will become fully functional again. The main purpose of this project is to develop a functional self-test of a DSP core, and to evaluate the characteristics of the test. This project also involves proposing a scheme on how to apply a functional test on a DSP core in an embedded environment, and how to retrieve results from the test. The test program shall run at system speed. To develop and measure the quality of the test program, two different coverage metrics were used. The first is the code coverage metric achieved by simulating the test program on the RTL representation of the DSP. The second metric used was the fault coverage achieved. The fault coverage of the test was calculated using a commercial Fault Simulator working on a gate-level representation of the DSP. The results achieved in this report show that this proposed approach can achieve acceptable levels of fault coverage in short execution time without the need for external testers which makes it possible to perform the self-test in the field. This approach has the unique property of not requiring any hardware modifications in the DSP design, and the ability of testing several DSPs in parallel.

The technological development is enabling production of increasingly complex electronic systems. All those systems must be verified and tested to guarantee correct behavior. As the complexity grows, testing is becoming one of the most significant factors that contribute to the final product cost. The established low-level methods for hardware testing are not any more sufficient and more work has to be done at abstraction levels higher than the classical gate and register-transfer levels. This thesis reports on one such work that deals in particular with high-level test generation and design for testability techniques. The contribution of this thesis is twofold. First, we investigate the possibilities of generating test vectors at the early stages of the design cycle, starting directly from the behavioral description and with limited knowledge about the final implementation architecture. We have developed for this purpose a novel hierarchical test generation algorithm and demonstrated the usefulness of the generated tests not only for manufacturing test but also for testability analysis. The second part of the thesis concentrates on design for testability. As testing of modern complex electronic systems is a very expensive procedure, special structures for simplifying this process can be inserted into the system during the design phase. We have proposed for this purpose a novel hybrid built-in self-test architecture, which makes use of both pseudorandom and deterministic test patterns, and is appropriate for modern system-on-chip designs. We have also developed methods for optimizing hybrid built-in self-test solutions and demonstrated the feasibility and efficiency of the proposed technique. / <p>Report code: LiU-Tek-Lic-2002:46.</p>

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A map combines scientific facts with aesthetic perceptions. This study argues that scaling is universal in mapping reality and evoking a sense of beauty. Scaling laws are used to reveal the underlying structures and dynamics of spatial features. Complex systems, such as living cities involve various interacting entities at all scales. Each individual coherently interacts and overlaps with others to create an unbreakable entity. Scaling structures are also known as fractals. Fractal geometry is used to depict a complex system. Natural objects, such as trees, contain a similar geometry (branches) at all scales. This study attempts to effectively visualize the scaling pattern of geographic space. In this regard, the head/tail breaks classification is applied to visualize the scaling pattern of spatial features. A scaling pattern underlies a geographic space. Visualizing the scaling structure using the head/tail breaks classification can further evoke a sense of beauty. This kind of beauty is on the structural level and was identified by Christopher Alexander, who asserted that beauty is not a personal experience but objectively exists in any space. Alexander developed the theory of centers to broaden the concepts of life and beauty.  A structure with a scaling property (with recursive centers) has high quality of life, and a scaling pattern has positive effects on individual’s psychological and physical well-being. To verify the concept of objective beauty, human beings are used as measuring instruments to examine the assumptions. This study adopts the mirror-of-the-self test to examine human reactions to 23 pairs of images, including photographs of buildings and two types of map. The idea is that participants sense the quality of life by comparing a pair of objects and selecting the object that presents a better picture of themselves. Once individuals feel the self in a picture, they are able to detect real beauty. In this manner, individuals can detect real beauty and life that deeply connect to their inner hearts. The tests were conducted through personal interviews and Internet surveys with the public and with professionals, and 392 samples were collected. The study results show that more than 60% of the individuals selected images with a scaling pattern. These results are in accordance with Alexander’s assumption. In particular, more than 65% individuals selected maps that depict scaling forms. Moreover, this study conducted a training test with a particular group of individuals, after which more than 70% of individuals selected scaling maps. The results reveal that scaling laws are applicable for creating maps and evoking a sense of beauty.