O foco desta tese é a descrição e validação de uma arquitetura de interface para processamento de sinais analógicos para SOC de sinais mistos. A abordagem proposta apresenta a possibilidade de cobertura de uma larga faixa de freqüências com performance praticamente constante associada a uma estrutura digital de programação. A premissa é usar uma célula analógica fixa e promover a configuração da aplicação no domínio digital, levando a uma arquitetura de interface de sinais mistos. O emprego de um bloco analógico fixo busca eliminar a perda inerente de performance decorrente da própria estrutura de programação em circuitos reconfiguráveis analógicos. A emprego da programação no domínio digital abre espaço para usos da vasta gama de ferramentas disponíveis para o projeto em alto nível de abstração, simulação e síntese automática para implementar a aplicação alvo com excelente predição do desempenho final. A abordagem proposta baseia-se no conceito de translação em freqüência (mixagem) do sinal de entrada seguida pela sua conversão para o domínio ΣΔ. A estrutura de processamento possibilita o emprego de um bloco analógico constante, e também, um processamento uniforme de sinais de entrada indo de DC até altas freqüências. A aplicação é configurada no domínio ΣΔ onde a performance pode ser predita de acordo com as especificações alvo. Objetivando a exploração do espaço de projeto foi desenvolvido o modelo de performance teórico e de simulação. Os modelos desenvolvidos auxiliam no também no projeto físico da interface proposta. Objetivando, tanto a validação dos modelos propostos, bem como o desenvolvimento de aplicações, foram construídos dois protótipos. São apresentados os usos da interface como um ADC paramétrico multi-banda e como um multiplicador e um somador de sinais analógicos. É proposta também uma arquitetura para uma interface analógica multi-canal. Os resultados experimentais empregados para a caracterização da interface proposta suportam as vantagens da mesma. / The focus of this thesis is to discuss the development and modeling of an interface architecture to be employed for interfacing analog signals in mixed-signal SOC. We claim that the approach that is going to be presented is able to achieve wide frequency range, and covers a large range of applications with constant performance, allied to digital configuration compatibility. Our primary assumptions are to use a fixed analog block and to promote application configurability in the digital domain, which leads to a mixed-signal interface. The use of a fixed analog block avoids the performance loss common to configurable analog blocks. The usage of configurability on the digital domain makes possible the use of all existing tools for high level design, simulation and synthesis to implement the target application, with very good performance prediction. The proposed approach utilizes the concept of frequency translation (mixing) of the input signal followed by its conversion to the ΣΔ domain, which makes possible the use of a fairly constant analog block, and also, a uniform treatment of input signal from DC to high frequencies. The programmability is performed in the ΣΔ digital domain where performance can be closely achieved according to application specification. The interface performance theoretical and simulation model are developed for design space exploration and for physical design support. Two prototypes are built and characterized to validate the proposed model and to implement some application examples. The usage of this interface as a multi-band parametric ADC and as a two channels analog multiplier and adder are shown. The multi-channel analog interface architecture is also presented. The characterization measurements support the main advantages of the approach proposed.

The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope. / The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope.

Cette thèse porte sur l’estimation spatiale de la teneur superficielle en carbone organiquedu sol ou teneur en SOC (pour ’Soil Organic Carbon content’), à l’échelle d’une petite région agricolefrancilienne. La variabilité de la teneur en SOC a été identifiée comme étant l’une des principales sourcesd’incertitude de la prédiction des stocks de SOC, dont l’accroissement favorise la fertilité des sols etl’atténuation des émissions de gaz à effet de serre. Nous utilisons des données provenant de sourceshétérogènes décrites selon différentes résolutions spatiales (prélèvements de sol, carte pédologique, imagessatellitaires multispectrales, etc) dans le but de produire d’une part une information spatiale exhaustive,et d’autre part des estimations précises de la teneur en SOC sur la région d’étude ainsi qu’une uneévaluation des incertitudes associées. Plusieurs modèles originaux, dont certains tiennent compte duchangement du support, sont construits et plusieurs approches et méthodes de prédiction sont considérées.Parmi elles, on retrouve des méthodes bayésiennes récentes et performantes permettant non seulementd’inférer des modèles sophistiqués intégrant conjointement des données de résolution spatiale différentemais aussi de traiter des données en grande dimension. Afin d’optimiser la qualité de la prédictiondes modélisations multi-sources, nous proposons également une approche efficace et rapide permettantd’accroître l’influence d’un type de données importantes mais sous-représentées dans l’ensemble de toutesles données initialement intégrées. / In this thesis, we are interested in the spatial estimation of the topsoil organic carbon(SOC) content over a small agricultural area located West of Paris. The variability of the SOC contenthas been identified as one of the main sources of prediction uncertainty of SOC stocks, whose increasepromotes soil fertility and mitigates greenhouse gas emissions. We use data issued from heterogeneoussources defined at different spatial resolutions (soil samples, soil map, multispectral satellite images, etc)with the aim of providing on the one hand an exhaustive spatial information, and on the other accurateestimates of the SOC content in the study region and an assessment of the related uncertainties. Severaloriginal models, some of which incorporate the change of support, are built and several approaches andprediction methods are considered. These include recent and powerful Bayesian methods enabling notonly the inference of sophisticated models integrating jointly data of different spatial resolutions butalso the exploitation of large data sets. In order to optimize the quality of prediction of the multi-sourcedata modellings, we also propose an efficient and fast approach : it allows to increase the influence of animportant but under-represented type of data, in the set of all initially integrated data.

Les activités scientifiques que nous présentons dans ce manuscrit de thèse s’inscrivent dans la thématique de l’intelligence ambiante, axe stratégique ADREAM au sein du LAAS-CNRS. Depuis plusieurs années notre équipe de recherche N2IS fédère l’approche technologique de la SHM avec pour objectif la surveillance de santé structurelle. En effet, la maturité des matériaux innovants tels que les composites suscitent un intérêt certain auprès des constructeurs aéronautiques, ou bien encore l’utilisation des matériaux de type béton pour des ouvrages d’art, sont autant de structures hétérogènes qui nécessitent une surveillance périodique et/ou continue. Ceci, afin de détecter des cracks, des fissures, des corrosions surfaciques ou bien encore des délaminages. Pour ce faire, les solutions existantes s’appuient usuellement sur des technologies de contrôle non destructif (CND) qui intègrent le plus souvent des réseaux de capteurs à faible consommation interfacés avec des systèmes d’analyses des signaux. Ces approches CND présentent des limitations fonctionnelles majeures : elles ne sont pas versatiles et ne permettent pas d’assurer une continuité de service dans un mode « dégradé » lors d’un fonctionnement sur batterie avec un niveau d’énergie minimal. Notre travail de recherche se situe dans une perspective liée à la quantification d’un niveau de robustesse de structure hétérogène. Il a pour ambition le développement et l’intégration de systèmes matériels mixtes (analogiques/numériques) reconfigurables. Au terme d’une investigation sur les principales solutions technologiques matérielles reprogrammables et compte tenu de la problématique liée aux développements d’algorithmes d’analyse embarqués et de la minimisation de la consommation énergétique des capteurs, le choix s’est porté sur des technologies complémentaires FPAA et FPGA. Initialement nos études de recherche se sont focalisées sur l'étude de fonction analogique matérielle reconfigurable analogique. L'objectif est de démontrer une faisabilité conceptuelle en intégrant un système de conditionnement complexe (implémentation d'une technique de détection synchrone), ceci en considérant le compromis entre la prise de décision d’une reconfiguration à la volée vis-à-vis d’une gestion rationnelle de l'énergie du système. Dès lors, se pose la question de comment intégrer et stocker des données nécessaires au développement d’un traitement numérique performant ? Une solution repose sur une approche hybride avec une puce de type Zynq produite par Xilinx et embarquée sur une Zedboard. Cette solution, plus performante qu’une approche PSoC a permis le développement et l’implémentation de techniques de traitement de signal grâce à des outils d'optimisation et de génération de code de haut niveau. Au terme de ce travail de recherche, les résultats obtenus démontrent la validité des concepts mis en œuvre et permettent d'engager dès à présent le développement d’architectures intelligentes de nouvelle génération / Scientific activities described in this PhD thesis are part of the theme of smart environment, strategy axes of ADREAM with the LAAS-CNRS. Since several years, our research team (N2IS) had a field of interest in SHM (Structural Health Monitoring) with the objective of doing a smart diagnostic on different heterogeneous structures. Indeed, the maturity of innovative materials such as composites triggering interest among aircraft manufacturers, or even the use of materials like concrete structures of civil engineering, all those heterogeneous structures that require periodic monitoring and / or continuous one. This is to detect cracks, disbond, surface corrosion or even delamination. To do this, existing solutions usually rely on technologies of nondestructive testing (NDT) that incorporate mostly sensor networks low-power systems interfaced with analysis of signals. These approaches have significant functional limitations: they are not versatile and do not allow for continuity of service in a "degraded" when operating on battery power with a minimum level of energy mode. Our research is a view related to the quantization level of robustness of a heterogeneous structure. Its aim is the development and integration of hardware reconfigurable mixed (A / D ) systems. After an investigation of the main technological solutions reprogrammable hardware and given the problems associated with developments in analytical embedded and minimizing the energy consumption of sensor algorithms. The choice was based on technologies like FPAA and FPGA. Initially our research studies have focused on the study of reconfigurable analog hardware analog. The objective was to show a conceptual feasibility of integrating a complex conditioning system (implementation of a synchronous detection technique), considering the tradeoff between a decision on the fly reconfiguration and a rational energy management system. Therefore, the question of how to integrate and store data necessary for the development of an efficient digital processing. A solution based on a hybrid approach with a chip produced by Xilinx called Zynq and embedded on a Zedboard. This solution is more efficient than a PSoC approach and allowed the development and implementation of signal processing techniques with tools for optimization and provided a solution of self-generation code trough a graphic interface. Following this research, the results obtained demonstrate the validity of the concepts implemented and allow us to imagine the next smart generation architectures

Bakgrund: Känsla av sammanhang (SOC) är en salutogen modell som beskriver hur människor ser livet och hanterar situationer med hjälp av resurser för att främja hälsa. Psoriasis är en kronisk och autoimmun sjukdom med en prevalens på två procent i Skandinavien. Den vanligaste formen av psoriasis är plackpsoriasis som karaktäriseras av rodnad, fjällning och förtjockning av epidermis. Syfte: Syftet var att belysa psykosociala aspekter av att leva med psoriasis. Metod: En allmän litteraturstudie där 11 resultatartiklar granskades i sin helhet och analyserades i enlighet med en databearbetningsmodell för litteraturöversikter med tre steg. Resultat: Genom dataanalysen identifierades tre huvudteman: Att skämmas över sin kropp, Att uppleva hinder i livet och Att hantera psoriasis. Resultatet påvisade flertalet psykosociala begränsningar som präglade vardagen och livskvaliteten negativt. Hälsofrämjande hanteringsstrategier identifierades dessutom. Konklusion: Ytterligare omvårdnadsforskning om levda erfarenheter hos personer med psoriasis behövs då området är begränsat utforskat. I vårdsammanhang bör personen ses som en helhet och inte enbart utifrån ett patogent perspektiv. / Background: Sence of coherence (SOC) is a salutogenic model that describe how people perceive life and deal with situations using their own resources to develop health. Psoriasis is a chronic and autoimmune disease with a prevalence of two percent in Scandinavia. The most common type of psoriasis is plaque psoriasis, which is characterized by raised skin patches, together with redness and scaling.  Aim: The aim was to illustrate the psychosocial aspects of living with psoriasis. Method: A general literature review in which 11 outcome articles were reviewed in their entirety and analyzed according to a three-step data processing model for literature reviews. Results: Through the data analysis, three main themes were identified: to be ashamed of one’s body, experiencing obstacles in life and dealing with psoriasis. The results revealed a large number of psychosocial limitations that negatively affected everyday life and quality of life. Health promoting coping strategies were also identified. Conclusion: Further nursing research is required to explore the lived life of people with psoriasis, as the current knowledge is limited. In the context of care, the person should be seen as a whole and not solely from a pathogenic perspective.

Aujourd'hui, les appareils sans fil disposent généralement de plusieurs technologies d'accès radio (LTE, WiFi,WiMax, ...) pour gérer une grande variété de normes ou de technologies. Ces appareils doivent être suffisamment intelligents et autonomes pour atteindre un niveau de performance donné ou sélectionne automatiquement la meilleure technologie sans fil disponible en fonction de la disponibilité des normes. Du point de vue matériel, les périphériques System on Chip (SoC) intègrent des processeurs et des structures logiques FPGA sur la même puce avec une interconnexion rapide. Cela permet de concevoir des systèmes logiciels / matériels et de mettre en oeuvre de nouvelles techniques et méthodologies qui améliorent considérablement les performances des systèmes de communication. Dans ces dispositifs, la reconfiguration partielle dynamique (DPR) constitue une technique bien connue pour reconfigurer seulement une zone spécifique dans le FPGA tandis que d'autres parties continuent à fonctionner indépendamment. Pour évaluer quand il est avantageux d'effectuer un DPR, des techniques adaptatives ont été proposées. Ils consistent à reconfigurer automatiquement des parties du système en fonction de paramètres spécifiques. Dans cette thèse, un système de communication sans fil intelligent visant à implémenter un émetteur OFDM adaptatif et à effectuer un transfert vertical dans des réseaux hétérogènes est présenté. Une couche physique unifiée pour les réseaux WiFi-WiMax est également proposée. Un algorithme de transfert vertical intelligent (VHA) basé sur les réseaux neuronaux (NN) a été proposé pour sélectionner le meilleur standard sans fil disponible dans un réseau hétérogène. Le système a été implémenté et testé sur un ZedBoard équipé d'un Xilinx Zynq-7000-SoC. La performance du système est décrite et des résultats de simulation sont présentés afin de valider l'architecture proposée. Des mesures de puissance en temps réel ont été appliquées pour calculer l'énergie de surcharge pour l'opération de RP. De plus, des démonstrations ont été effectuées pour tester et valider le système mis en place. / Today, wireless devices generally feature multiple radio access technologies (LTE, WiFi, WiMax, ...) to handle a rich variety of standards or technologies. These devices should be intelligent and autonomous enough in order to either reach a given level of performance or automatically select the best available wireless standard. On the hardware side, System on Chip (SoC) devices integrate processors and FPGA logic fabrics on the same chip with fast inter-connection. This allows designing Software/Hardware systems. In these devices, Dynamic Partial Reconfiguration (DPR) constitutes a well-known technique for reconfiguring only a specific area within the FPGA while other parts continue to operate independently. To evaluate when it is advantageous to perform DPR, adaptive techniques have been proposed. They consist in reconfiguring parts of the system automatically according to specific parameters. In this thesis, an intelligent wireless communication system aiming at implementing an adaptive OFDM based transmitter is presented. An unified physical layer for WiFi-WiMax networks is also proposed. An intelligent Vertical Handover Algorithm (VHA) based on Neural Networks (NN) was proposed to select best available wireless standard in heterogeneous network. The system was implemented and tested on a ZedBoard which features a Xilinx Zynq-7000-SoC. The performance of the system is described and simulation results are presented in order to validate the proposed architecture. Real time power measurements have been applied to compute the overhead power for the PR operation. In addition demonstrations have been performed to test and validate the implemented system.

Efter att ha medverkat i mindfulness-programmet ”Mitt Lugn” två till tre gånger i veckan under sex veckor anmälde sig tolv gymnasieelever till en intervju. En kvalitativ innehållsanalys valdes för att analysera intervjuerna. Mindfulness-komponenterna uppmärksamhet- och acceptansförmågan, kognitiv, emotionell och beteendemässig flexibilitet, självreglering och värderingsklarifikation visade sig började fungera främjande inom studiens undersökta områden. Välbefinnandet ökade till följd av ett mer flexibelt sätt att tänka och känna i olika situationer. Studietekniken förbättrades som ett resultat av det nya, kontrollerade och självreflekterande sättet att studera. Dessutom menade eleverna dels att de utvecklat en distans mellan sina och andras tankar och känslor, dels att mindfulness-praktik i klassrummet både fungerande lugnande och hade en spridande effekt i klassen. Eleverna ansåg även att det var viktigt att förstå avsikten med olika övningar, då det både ökar insikten om syftet med praktiken och motiverar elever att vilja delta. / High school students who implemented the mindfulness program "My Claim " describe how different mindfulness components such as attention and acceptance have contributed to their perceived well-being, and their view and management of their schoolwork and school environment. Twelve students participated in a voluntary, self-reported interview after the program and the the interviews were analyzed with a qualitative content analysis. The welfare of most students increased as a result of a more flexible way of thinking and feeling in different situations. Study technique was improved as a result of a focused and self-reflecting way of studying. As far as the school environment is concerned, the pupils did not experience any general improvement, however, the students meant that they developed a distance between their own and other’s thoughts and feelings, and partly that a mindfulness practice in classrooms affects itself. The pupils also considered it important to understand the purpose of different exercises, as it both increases the insight about the purpose of the practice and motivates students to want to participate.

Jusqu'à présent, le test de circuits intégrés et des systèmes au niveau wafer est basé sur un contact physique entre l'équipement de test et les circuits sur le wafer. Cette méthode basée sur le contact est limitée par plusieurs facteurs, tels que le nombre de circuits testés en parallèle, la réduction de la taille et de l'espacement entre les plots de contact, le nombre de contact avant que les plots soient endommagés, le coût des opérations de test, entre autres. Pour résoudre ces problèmes, nous proposons une nouvelle approche de test basée sur la communication sans fil entre le testeur et les circuits à tester (DUT). Pour cela, un Wireless Test Control Bloc (WTCB) est ajouté à chaque DUT sur le wafer comme une interface sans fil entre le testeur et les structures de test internes du DUT. Ce WTCB intègre une pile protocolaire de communication pour gérer la communication avec le testeur, et un Test Control Bloc (TCB) pour gérer l'application de test au niveau DUT. Profitant d'une transmission sans fil, le testeur peut diffuser les données de test à tous les DUT sur le wafer , maximisant le test simultané et réduisant donc le temps de test. En outre, notre architecture de WTCB permet une comparaison locale de la réponse de DUT avec la réponse correcte attendue par le testeur. En effectuant cette comparaison dans le WTCB du DUT, le testeur recueille de chaque DUT 1 seul bit comme résultat de la comparaison, au lieu d'une réponse complète, conduisant à un test sans fil plus rapide qui réduit le temps d'essai. Le WTCB a été mis en oeuvre sur FPGA, et une épreuve de test sans fil d'un circuit réel a été réalisée, prouvant la conception efficace de notre WTCB, et soulignant le potentiel de notre méthode de test sans fil, où elle peut être étendue et utilisée pour des applications de test in situ à distance. / So far, the test of integrated circuits and systems at wafer level relies on a physical contact between the test equipment and the devices under test on the wafer. This contact-based method is limited by several factors, such as the number of devices tested in parallel, the reduction of the size and the pitch of the bond pads, the number of touchdowns before bond pads are damaged, the cost of the test operations, among others. To solve these issues, we propose a novel test approach and architecture based on wireless communication between the tester and the devices under test (DUT). For that, a Wireless Test Control Block (WTCB) is added to every DUT on the wafer as a wireless interface between the tester and the internal test structures of the DUT. This WTCB embeds a communication protocol stack to manage the communication with the tester, and a Test Control Block to manage the test application at DUT level. Taking advantage of a wireless transmission, the tester can broadcast the test data to all DUT on the wafer in one path, maximizing the concurrent test, and reducing therefore the test time. Moreover, our WTCB architecture allows a local comparison of the DUT response with the correct response expected by the tester. By performing this comparison in the WTCB of the DUT, the tester collects from every DUT its 1-bit comparison result instead of a complete response, leading to a faster wireless test and extremely reduced test time. The WTCB has been implemented on FPGA, and a successful wireless test of a real circuit was performed, proving the efficient design of our WTCB, and highlighting the potential of our wireless test method, where it can be extended and used to perform a remote in-situ test.

SoCs (System on Chips) are complex designs with heterogeneous modules (CPU, memory, etc.) integrated in them. Verification is one of the important stages in designing an SoC. Verification is the process of checking if the transformation from architectural specification to design implementation is correct. Verification involves creating the following components: (i) a testplan that identifies the conditions to be verified, (ii) a testcase that generates the stimuli to verify the conditions identified, and (iii) a test-bench that applies the stimuli and monitors the output from the design. Verification consumes upto 70% of the total design time. This is largely due to the complex and manual nature of the verification task. To reduce the time spent in verifying the design, the components used for verification can be generated automatically or created at an abstract level (to reduce the complexity) and reused. In this work we present a methodology to synthesize testcases from reusable code segments and abstract specifications. Our methodology consists of the following major steps: (i) identifying the structure of testcases, (ii) identifying code segments of testcases that can be reused from one SoC to another, (iii) identifying properties of an SoC and its modules that can be used to synthesize the SoC specific code segments of the testcase, and (iv) proposing a synthesizer that uses the code segments, the properties and the abstract specification to synthesize testcases. We discuss two specific classes of testcases. These are testcases for verifying the memory modules and the testcases for verifying the data transfer modules. These are considered since they form a significantly large subset of the device functionality. We implement a prototype testcase generator and also present an example to illustrate the use of methodology for each of these classes. The use of our methodology enables (i) the creation of testcases automatically that are correct by construction and (ii) reuse of the testcase code segments from one SoC to another. Some of the properties (of the modules and the SoC) presented in our work can be easily made part of the architectural specification, and hence, can further reduce the effort needed to create them.

Together with industrial partners Hasso-Plattner-Institut (HPI) is currently establishing a “HPI Future SOC Lab,” which will provide a complete infrastructure for research on on-demand systems. The lab utilizes the latest, multi/many-core hardware and its practical implementation and testing as well as further development. The necessary components for such a highly ambitious project are provided by renowned companies: Fujitsu and Hewlett Packard provide their latest 4 and 8-way servers with 1-2 TB RAM, SAP will make available its latest Business byDesign (ByD) system in its most complete version. EMC² provides high performance storage systems and VMware offers virtualization solutions. The lab will operate on the basis of real data from large enterprises. The HPI Future SOC Lab, which will be open for use by interested researchers also from other universities, will provide an opportunity to study real-life complex systems and follow new ideas all the way to their practical implementation and testing. This technical report presents results of research projects executed in 2011. Selected projects have presented their results on June 15th and October 26th 2011 at the Future SOC Lab Day events. / In Kooperation mit Partnern aus der Industrie etabliert das Hasso-Plattner-Institut (HPI) ein “HPI Future SOC Lab”, das eine komplette Infrastruktur von hochkomplexen on-demand Systemen auf neuester, am Markt noch nicht verfügbarer, massiv paralleler (multi-/many-core) Hardware mit enormen Hauptspeicherkapazitäten und dafür konzipierte Software bereitstellt. Das HPI Future SOC Lab verfügt über prototypische 4- und 8-way Intel 64-Bit Serversysteme von Fujitsu und Hewlett-Packard mit 32- bzw. 64-Cores und 1 - 2 TB Hauptspeicher. Es kommen weiterhin hochperformante Speichersysteme von EMC². SAP stellt ihre neueste Business by Design (ByD) Software zur Verfügung und auch komplexe reale Unternehmensdaten stehen zur Verfügung, auf die für Forschungszwecke zugegriffen werden kann. Interessierte Wissenschaftler aus universitären und außeruniversitären Forschungsinstitutionen können im HPI Future SOC Lab zukünftige hoch-komplexe IT-Systeme untersuchen, neue Ideen / Datenstrukturen / Algorithmen entwickeln und bis hin zur praktischen Erprobung verfolgen. In diesem Technischen Bericht werden die Ergebnisse der Forschungsprojekte des Jahres 2011 vorgestellt. Ausgewählte Projekte stellten ihre Ergebnisse am 15. Juni 2011 und 26. Oktober 2011 im Rahmen der Future SOC Lab Tag Veranstaltungen vor.