The miniaturization of dc–dc switch-mode power supplies (SMPS) is of a key importance in volume-sensitive portable devices, such as cell phones, tablet computers, and digital cameras. In these systems, multiple SMPS are required to provide well regulated voltage and power to various electronic components such as the central processing unit (CPU) and random-access memory (RAM). The combined volume, weight, and surface area footprint of these SMPS is usually the largest component. Traditionally, SMPS volume reduction has been achieved through increased switching frequencies; however, for power-sensitive applications this is undesirable due to the increased switching losses. This thesis presents two alternative, power-efficient, SMPS miniaturization methods: one control and one topology based. The presented controller recovers from load transients with virtually minimum possible output voltage deviation, reducing the reactive component size. The controller utilizes a simple algorithm, requiring no knowledge of the converter parameters and virtually no processing power. The simplicity of the control concept enabled the design of an area and power efficient integrated circuit (IC) implementation. The entire IC is implemented in a CMOS 0.18µm process on a 0.26 mm2 silicon area, which is comparable to the state-of-the-art analog solutions. For the experimental system the deviation (output capacitor size) is about four times smaller than that of a fast PID compensator having a 1/10th of the switching frequency bandwidth. The second solution is a complementary converter topology that has a smaller output filter volume, improved dynamic response, and lower switching losses compared to the state-of-the-art solutions. To reduce the volume and switching losses, the input-to-output voltage difference is decreased with a capacitive attenuator that replaces the input filter capacitor and has approximately the same volume. Both the attenuator and the downstream buck converter share the same set of switches, minimizing conduction losses. A single multi-mode digital controller governs operation of both stages, seamlessly regulating the output and input center-tap voltages. Experiments with a 5–1.5-V, 2.5-A, 1-MHz prototype show that, compared to the conventional buck, the merged topology has 43% smaller inductor, 36% smaller output capacitor, up to 30% lower power losses, and a 25% faster transient response.

The miniaturization of dc–dc switch-mode power supplies (SMPS) is of a key importance in volume-sensitive portable devices, such as cell phones, tablet computers, and digital cameras. In these systems, multiple SMPS are required to provide well regulated voltage and power to various electronic components such as the central processing unit (CPU) and random-access memory (RAM). The combined volume, weight, and surface area footprint of these SMPS is usually the largest component. Traditionally, SMPS volume reduction has been achieved through increased switching frequencies; however, for power-sensitive applications this is undesirable due to the increased switching losses. This thesis presents two alternative, power-efficient, SMPS miniaturization methods: one control and one topology based. The presented controller recovers from load transients with virtually minimum possible output voltage deviation, reducing the reactive component size. The controller utilizes a simple algorithm, requiring no knowledge of the converter parameters and virtually no processing power. The simplicity of the control concept enabled the design of an area and power efficient integrated circuit (IC) implementation. The entire IC is implemented in a CMOS 0.18µm process on a 0.26 mm2 silicon area, which is comparable to the state-of-the-art analog solutions. For the experimental system the deviation (output capacitor size) is about four times smaller than that of a fast PID compensator having a 1/10th of the switching frequency bandwidth. The second solution is a complementary converter topology that has a smaller output filter volume, improved dynamic response, and lower switching losses compared to the state-of-the-art solutions. To reduce the volume and switching losses, the input-to-output voltage difference is decreased with a capacitive attenuator that replaces the input filter capacitor and has approximately the same volume. Both the attenuator and the downstream buck converter share the same set of switches, minimizing conduction losses. A single multi-mode digital controller governs operation of both stages, seamlessly regulating the output and input center-tap voltages. Experiments with a 5–1.5-V, 2.5-A, 1-MHz prototype show that, compared to the conventional buck, the merged topology has 43% smaller inductor, 36% smaller output capacitor, up to 30% lower power losses, and a 25% faster transient response.

This master´s thesis describes switch mode power supply and discusses the design of its individual parts. It also contains a simulation of the power part of the converter and a reseach in the area of DC/DC converters.

This project deals with a design of power and control circuits for a laboratory power supply source, consisting of a continuous conduction mode active rectifier and DC/DC converter. Detailed design of input rectifier with active power factor correction, DC/DC converter and control circuits with their implementation to digital signal processor are the project results.

This Master of Applied Science thesis proposes a new design of low power, power factor corrected (PFC), power supplies. By lifting the hold up time restriction for devices that have a battery built in, the energy storage elements of the converter can be reduced, permitting a small and inexpensive power converter to be built. In addition, a new control technique for controlling cascaded converters is presented, named duty mode control (DMC). Its advantages are shown through simulations. The system was proven using a prototype developed in the laboratory designed for a universal ac input voltage (85 - 265VRMS at 50 - 60Hz) and a 40W output at 12V. It consisted of two interleaved phases sensed and digitally controlled on the isolated side of the converter. The prototype was able to achieve a power factor of greater than 0.98 for all operating conditions, and input harmonic current distortion well below any set of standards.

This Master of Applied Science thesis proposes a new design of low power, power factor corrected (PFC), power supplies. By lifting the hold up time restriction for devices that have a battery built in, the energy storage elements of the converter can be reduced, permitting a small and inexpensive power converter to be built. In addition, a new control technique for controlling cascaded converters is presented, named duty mode control (DMC). Its advantages are shown through simulations. The system was proven using a prototype developed in the laboratory designed for a universal ac input voltage (85 - 265VRMS at 50 - 60Hz) and a 40W output at 12V. It consisted of two interleaved phases sensed and digitally controlled on the isolated side of the converter. The prototype was able to achieve a power factor of greater than 0.98 for all operating conditions, and input harmonic current distortion well below any set of standards.

This master´s thesis describes switch mode power supply. The aim of this master´s thesis is the design and the construction of the switch mode power supply, which will be used as a laboratory tool.

In the thesis the design of the Data Storage System (DSS) is proposed with the respect to the V-Model methodology. The design is based on users requirements, from which the system requirements are created and the technical specification of the DSS is developed. In the technical specifications the functionality of the DMM and HMI DSS subsystems are described and sub-system requirements are assigned to them, then they are subdivided and assigned to individual DMM (Data memory module) and HMI hardware items. Moreover, requirements are analyzed on hardware items, specific electronic components, are selected and implemented into the block design of the DMM hardware. Based on the block design of hardware, the hardware of the DMM subsystem is designed, selectively simulated and implemented along with the printed circuit board. On the implemented hardware of the DMM subsystems measurements are performed in order to verify the basic functionality of the hardware and the calculated, assimilated and measured values are compared as well. At the end of the thesis there is a short description of the implementation of the software design and its use for basic initialization of the selected processor, together with the verification of its basic function - measuring the frequency of the internal clock sources and the clock domains. The work is completed by sending a message of defined parameters to the selected communication line and sapling it by an oscilloscope, so that the basic function of the DMM subsystem is verified.

Tato dizertační práce představuje novou techniku laterární rezonanční vazby, která je využita v návrhu galvanicky izolovaného posouvače úrovně, který je následně implementován v 800 V půlmůstkovém kontroléru pro průmyslové aplikace. Ve srovnání s tradičními galvanickými izolátory jsou výrobní náklady tohoto řešení nižší. Pro aplikace vyžadující vyšší úroveň galvanické izolace je popsán následný vývoj galvanicky izolovaného posouvače úrovně, který využívá pouze jeden galvanicky oddělený posouvač úrovní pro komunikaci v obou směrech, což výrazně snižuje plochu struktury izolátoru. Jako součást následného návrhu je představen galvanický izolátor který je schopen přenášet analogovou hodnotu napětí. Analogový izolátor byl testován v reálné aplikaci síťového spínaného zdroje jako náhrada standardního optočlenu. Tato konstrukce umožňuje integraci primárních a sekundárních obvodů v jednom pouzdře, což umožní snížit složitost a cenu spínaného zdroje.

The main goal of this thesis is to develop practical digital controller architectures for multi-phase dc-dc converters utilized in low power (up to few hundred watts) and cost-sensitive applications. The proposed controllers are suitable for on-chip integration while being capable of providing advanced features, such as dynamic efficiency optimization, inductor current estimation, converter component identification, as well as combined dynamic current sharing and fast transient response. The first part of this thesis addresses challenges related to the practical implementation of digital controllers for low-power multi-phase dc-dc converters. As a possible solution, a multi-use high-frequency digital PWM controller IC that can regulate up to four switching converters (either interleaved or standalone) is presented. Due to its configurability, low current consumption (90.25 μA/MHz per phase), fault-tolerant work, and ability to operate at high switching frequencies (programmable, up to 10 MHz), the IC is suitable to control various dc-dc converters. The applications range from dc-dc converters used in miniature battery-powered electronic devices consuming a fraction of watt to multi-phase dedicated supplies for communication systems, consuming hundreds of watts. A controller for multi-phase converters with unequal current sharing is introduced and an efficiency optimization method based on logarithmic current sharing is proposed in the second part. By forcing converters to operate at their peak efficiencies and dynamically adjusting the number of active converter phases based on the output load current, a significant improvement in efficiency over the full range of operation is obtained (up to 25%). The stability and inductor current transition problems related to this mode of operation are also resolved. At last, two reconfigurable digital controller architectures with multi-parameter estimation are introduced. Both controllers eliminate the need for external analog current/temperature sensing circuits by accurately estimating phase inductor currents and identifying critical phase parameters such as equivalent resistances, inductances and output capacitance. A sensorless non-linear, average current-mode controller is introduced to provide fast transient response (under 5 μs), small voltage deviation and dynamic current sharing with multi-phase converters. To equalize the thermal stress of phase components, a conduction loss-based current sharing scheme is proposed and implemented.