This thesis describes the design, implementation and testing of a UHF frequency synthesizer. The synthesizer is designed to provide a sine wave output programmable from 400 MHz to 500 MHz in 0.1 MHz increments. The synthesis technique utilized is Digital Coherent Indirect Synthesis. This technique uses phase locking to provide a range of stable output frequencies all derived from a single crystal reference. Component design and system level analysis are presented in detail.

by C.Y. Ho. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1989. / Bibliography: leaves [147]-[148]

Existem inúmeras técnicas de síntese de áudio utilizadas atualmente em instrumentos musicais profissionais, dentre as quais as mais fundamentais são a síntese aditiva e a síntese subtrativa. A síntese subtrativa se tornou popular e foi muito explorada entre as décadas de 60 e 70 com a criação de módulos analógicos de hardware que podiam ser interconectados, criando o conceito de sintetizador analógico modular. Apesar do uso deste tipo de sintetizador ter diminuído durante as décadas subsequentes, nos últimos anos sua utilização voltou a crescer e diversos modelos deste tipo de instrumento são vendidos atualmente, porém em geral a preços elevados. Sintetizadores digitais também disponibilizam a técnica de síntese subtrativa utilizando componentes eletrônicos customizados e desenvolvidos pelos fabricantes de sintetizadores com o intuito de utilizar avançadas técnicas de processamento de sinais, o que ainda mantém seus preços elevados. Neste trabalho investigamos a hipótese de que é possível desenvolver um instrumento musical funcional e de qualidade com recursos limitados de processamento, e exploramos essa hipótese implementando síntese subtrativa em uma plataforma acessível e de baixo custo. O desenvolvimento é baseado em linguagem orientada a objetos para criação de módulos de software replicando as características dos módulos encontrados em sintetizadores analógicos modulares. Com esta abordagem, obtemos um software modular que pode ser facilmente modificado baseado nas preferências do programador. A implementação foi testada na plataforma Arduino Due, que é uma plataforma de baixo custo e contém um processador 32-bits ARM 84 MHz. Foi possível adicionar osciladores com algoritmo anti-aliasing, filtros, geradores de envelope, módulo de efeito, uma interface MIDI e um teclado externo, obtendo assim um sintetizador subtrativo completo. Além disto, incluímos no desenvolvimento a implementação de um órgão baseado em síntese aditiva, com polifonia completa e inspirado na arquitetura de órgãos clássicos, mostrando a possibilidade de possuir dois importantes e poderosos métodos de síntese em uma plataforma acessível e de baixo custo. Com esta implementação aberta e pública, buscamos contribuir com o movimento maker e faça-você-mesmo, incentivando novos desenvolvimentos nesta área, em especial na computação e engenharia, aumentando o uso e acesso a instrumentos musicais eletrônicos e a criatividade musical. / Subtractive and additive synthesis are two powerful sound synthesis techniques that caused a revolution when the first electronic and electro mechanic music instruments started to appear some decades ago. Subtractive synthesis became very popular during the 60s and 70s after the creation of analog hardware modules that could be interconnected, creating the concept of the modular synthesizers. After the initial impact, for some years these instruments faced a slow-down in its usage, a tendency that was reverted on the past decade. Nevertheless, the prices of these instruments are often high. Digital synthesizers also offer the subtractive synthesis technique, by using customized electronic components designed and developed by the synthesizers vendors in order to use the most up-to-date technologies and signal processing techniques, which also leads to high prices. In this project, we investigate the hypothesis that it is possible to design and develop a good quality music instrument with low budget electronic components and limited processing capabilities, by implementing this on a low budget and easy to use platform. The development is based on object oriented design, creating software modules that replicates the functionalities of analog synthesizer hardware modules. With this approach, we have a modular software that can be easily changed based on programmers’ preferences. The implementation was tested on the Arduino Due board, which is a cheap, easy to use and widely available platform and powered by a 32-bits ARM 84Mhz processor. We were able to add oscillators with anti-aliasing algorithms, filters, envelope generators, delay effects, a MIDI interface and a keybed, making a complete synthesizer. In addition to this, we included an additive synthesis organ design with full polyphony based on classic organs design, demonstrating the possibility of having two powerful synthesis methods on a cheap and widely available platform. With this design, suitable for low cost platforms, we intend to contribute to the maker movement and encourage new implementations in this area, especially in the computing and engineering fields, increasing the usage and access to (electronic) musical instruments and musical creativity.

Arbetet fokuserar på hur min musikaliska röst förändras efter ny kunskap inom programmering av synthljud. Syftet är inte att lära mig allt om synthesizers, utan snarare identifiera vad jag behöver kunna för att på bästa sätt utnyttja kunskapen i mitt filmmusik-arbete och skapa mina egna ljud. I texten beskrivs denna process och mina tankar kring det hela. / <p>Till uppsatsen följer bilagor i form av ljudexempel på de syntljud som jag har programmerat för detta arbete.</p>

The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications like high-resolution imaging and ranging, and the emerging 5-G communication space. RADAR techniques when expanded to optical frequencies can enable micrometers of resolution for 3D imaging. These applications, however, impose upto 100x more exacting specifications on power and spectral purity at much higher frequencies than conventional RF synthesizers. This generation of applications will present unconventional challenges for transistor technologies - whether it is to squeeze performance in the conventionally used spectrum, already wrung dry, or signal generation and system design in the relatively emptier mm-Wave to sub-mmWave spectrum, much of the latter falling in the ``Terahertz Gap". Indeed, transistor scaling and innovative device physics leading to new transistor topologies have yielded higher cut-off frequencies in CMOS, though still lagging well behind SiGe and III-V semiconductors. To avoid multimodule solutions with functionality partitioned across different technologies, CMOS must be pushed out of its comfort zone, and technology scaling has to have accompanying breakthroughs in design approaches not only at the system but also at the block level. In this thesis, while not targeting a specific application, we seek to formulate the obstacles in synthesizing high frequency, high power and low noise signals in CMOS and construct a coherent design methodology to address them. Based on this, three novel prototypes to overcome the limiting factors in each case are presented. The first half of this thesis deals with high frequency signal synthesis and power generation in CMOS. Outside the range of frequencies where the transistor has gain, frequency generation necessitates harmonic extraction either as harmonic oscillators or as frequency multipliers. We augment the traditional maximum oscillation frequency metric (fmax), which only accounts for transistor losses, with passive component loss to derive an effective fmax metric. We then present a methodology for building oscillators at this fmax, the Maximum Gain Ring Oscillator. Next, we explore generating large signals beyond fmax through harmonic extraction in multipliers. Applying concepts of waveform shaping, we demonstrate a Power Mixer that engineers transistor nonlinearity by manipulating the amplitudes and relative phase shifts of different device nodes to maximize performance at a specific harmonic beyond device cut-off. The second half proposes a new architecture for an ultra-low noise phase-locked loop (PLL), the Reference-Sampling PLL. In conventional PLLs, a noisy buffer converts the slow, low-noise sine-wave reference signal to a jittery square-wave clock against which the phase of a noisy voltage-controlled oscillator (VCO) is corrected. We eliminate this reference buffer, and measure phase error by sampling the reference sine-wave with the 50x faster VCO waveform already available on chip, and selecting the relevant sample with voltage proportional to phase error. By avoiding the N-squared multiplication of the high-power reference buffer noise, and directly using voltage-mode phase error to control the VCO, we eliminate several noisy components in the controlling loop for ultra-low integrated jitter for a given power consumption. Further, isolation of the VCO tank from any varying load, unlike other contemporary divider-less PLL architectures, results in an architecture with record performance in the low-noise and low-spur space. We conclude with work that brings together concepts developed for clean, high-power signal generation towards a hybrid CMOS-Optical approach to Frequency-Modulated Continuous-Wave (FMCW) Light-Detection-And-Ranging (LIDAR). Cost-effective tunable lasers are temperature-sensitive and have nonlinear tuning profiles, rendering precise frequency modulations or 'chirps' untenable. Locking them to an electronic reference through an electro-optic PLL, and electronically calibrating the control signal for nonlinearity and ambient sensitivity, can make such chirps possible. Approaches that build on the body of advances in electrical PLLs to control the performance, and ease the specification on the design of optical systems are proposed. Eventually, we seek to leverage the twin advantages of silicon-intensive integration and low-cost high-yield towards developing a single-chip solution that uses on-chip signal processing and phased arrays to generate precise and robust chirps for an electronically-steerable fine LIDAR beam.

Ng Chong Chon. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 100-103). / Abstract in English and Chinese. / 摘要 --- p.iii / Acknowledgments --- p.iv / Contents --- p.vi / List of Figures --- p.ix / List of Tables --- p.xii / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Thesis Organization --- p.4 / Chapter Chapter 2 --- DMP Architecture --- p.6 / Chapter 2.1 --- Conventional DMP --- p.6 / Chapter 2.1.1 --- Operating Principle --- p.7 / Chapter 2.1.2 --- Disadvantages --- p.10 / Chapter 2.2 --- Pre-processing Clock Architecture --- p.10 / Chapter 2.2.1 --- Operating Principle --- p.11 / Chapter 2.2.2 --- Advantages and Disadvantages --- p.12 / Chapter 2.3 --- Phase-switching Architecture --- p.13 / Chapter 2.3.1 --- Operating Principle --- p.13 / Chapter 2.3.2 --- Advantages and Disadvantages --- p.14 / Chapter 2.4 --- Summary --- p.15 / Chapter Chapter 3 --- Full-Speed Divider Design --- p.16 / Chapter 3.1 --- Introduction --- p.16 / Chapter 3.2 --- Working Principle --- p.16 / Chapter 3.3 --- Design Issues --- p.18 / Chapter 3.4 --- Device Sizing --- p.19 / Chapter 3.5 --- Layout Considerations --- p.20 / Chapter 3.6 --- Input Sensitivity --- p.22 / Chapter 3.7 --- Modeling --- p.24 / Chapter 3.8 --- Review on Different Divider Designs --- p.28 / Chapter 3.8.1 --- Divider with Dynamic-Loading Technique --- p.28 / Chapter 3.8.2 --- Divider with Negative-Slew Technique --- p.30 / Chapter 3.8.3 --- LC Injection-Locked Frequency Divider --- p.32 / Chapter 3.8.4 --- Dynamic True Single Phase Clock Frequency Divider --- p.34 / Chapter 3.9 --- Summary --- p.42 / Chapter Chapter 4 --- 3V 900MHz Low Noise DMP --- p.43 / Chapter 4.1 --- Introduction --- p.43 / Chapter 4.2 --- Proposed DMP Topology --- p.46 / Chapter 4.3 --- Circuit Design and Implementation --- p.49 / Chapter 4.4 --- Simulation Results --- p.51 / Chapter 4.5 --- Summary --- p.53 / Chapter Chapter 5 --- 1.5V 2.4GHz Low Power DMP --- p.54 / Chapter 5.1 --- Introduction --- p.54 / Chapter 5.2 --- Proposed DMP Topology --- p.56 / Chapter 5.3 --- Circuit Design and Implementation --- p.59 / Chapter 5.3.1 --- Divide-by-4 stage --- p.59 / Chapter 5.3.2 --- TSPC dividers --- p.63 / Chapter 5.3.3 --- Phase-selection Network --- p.63 / Chapter 5.3.4 --- Mode-control Logic --- p.64 / Chapter 5.3.5 --- Duty-cycle Transformer --- p.65 / Chapter 5.3.6 --- Glitch Problem --- p.66 / Chapter 5.3.7 --- Phase-mismatch Problem --- p.70 / Chapter 5.4 --- Simulation Results --- p.70 / Chapter 5.5 --- Summary --- p.74 / Chapter Chapter 6 --- 1.5V 2.4GHz Wideband DMP --- p.75 / Chapter 6.1 --- Introduction --- p.75 / Chapter 6.2 --- Proposed DMP Architecture --- p.75 / Chapter 6.3 --- Divide-by-4 Stage --- p.76 / Chapter 6.3.1 --- Current-switch Combining --- p.76 / Chapter 6.3.2 --- Capacitive Load Reduction --- p.77 / Chapter 6.4 --- Simulation Results --- p.81 / Chapter 6.5 --- Summary --- p.83 / Chapter Chapter 7 --- Experimental Results --- p.84 / Chapter 7.1 --- Introduction --- p.84 / Chapter 7.2 --- Equipment Setup --- p.84 / Chapter 7.3 --- Measurement Results --- p.85 / Chapter 7.3.1 --- 3V 900GHz Low Noise DMP --- p.85 / Chapter 7.3.2 --- 1.5V 2.4GHz Low Power DMP --- p.88 / Chapter 7.3.3 --- 1.5V 2.4GHz Wideband DMP --- p.93 / Chapter 7.3 --- Summary --- p.96 / Chapter Chapter 8 --- Conclusions and Future Works --- p.98 / Chapter 8.1 --- Conclusions --- p.98 / Chapter 8.2 --- Future Works --- p.99 / References --- p.100 / Publications --- p.104

This thesis presents the design of a 2.4 GHz sub-integer-N PLL for IEEE 802.llb/g WLAN applications. The proposed PLL not only acquires the advantages of the integer-N PLL, such as simple structure and good spurious performance, but also offers some benefits (for example, faster settling time and better phase noise performance) as in the fractional-N PLL design. In this design, a novel quadrature-input programmable fractional frequency divider provides fractional division ratio in steps of 0.5 by the phase-switching technique. Its key building block is a dual divide-by-4 injection-locked frequency divider (ILFD), which is realized by coupling two conventional divide-by-4 ILFDs. Two different coupling schemes are introduced, namely the cross-coupling type and coherent-coupling type. In both schemes, symmetric configuration is maintained and hence does not degrade the PLL output phase quadrature accuracy. Furthermore, the generated phase pattern for phase switching is uniquely defined, which simplifies the phase-switching circuitry and suppresses the possibility of incorrect frequency division due to glitches. / To demonstrate the feasibility of the two proposed coupling methodologies, two subinteger-N PLLs with different fractional frequency dividers have been fabricated in a 0.35 11m standard CMOS process. In design 1, the dual divide-by-4 ILFD in the fractional frequency divider is implemented with the cross-coupling scheme while the coherent-coupling scheme is used in design 2. The measured spurious tones of both designs are under -64 dBc and their measured phase noise at 1 MHz frequency offset is less than -115 dBc/Hz. The two proposed frequency synthesizers settle at approximately 32 us and their phase mismatches of the quadrature outputs are better than 38 dB (characterized by image rejection ratio). Moreover, both designs individually occupy a chip area as small as 0.70 mm2. At a supply of 1.5 V, the total power consumption for each design is below 24.1 mW. / Wireless local area networks (WLANs) are being extensively deployed since their introduction in the late 1990s. Low cost, high performance frequency synthesizers are indispensable in WLAN telecommunication systems. Meanwhile, integer-N phase-locked loop (PLL) architecture is commonly chosen due to its low circuit complexity and clean output spectrum with few spurs. However, designers have to face the tradeoffs between frequency resolution, phase noise performance and switching time. To solve the above dilemma, fractional-N PLL architecture is proposed, but fractional spurs emerge in the output spectrum, degrading the spectrum purity. Sub-integer-N PLL is thus a compromise between the integer-N and fractional-N PLL. Its structure is same as that of the integer-N while fractional division is achieved by a fractional frequency divider that is not relied on time-varying modulus control as in the fractional-N PLL. / Chang, Ka Fai. / Adviser: Kwok-Keung Cheng. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 176-188). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Today a growing number of applications in design engineering, production and environmental testing, and system service require specific analog waveforms and digital patterns. Such requirements are neither satisfactorily nor easily met by the use of standard function or single purpose, custom generators. Traditional methods of waveform generation suffer from undesirable complexity or mediocre performance and are otherwise limited. For the majority of arbitrary waveform generation applications, including medical engineering, modal analysis and electronic engineering, direct digital synthesis techniques are satisfactory. Direct digital synthesis, based generally on periodic retrieval of predetermined amplitude values, may be used to 2 generate such waveforms. Within the limits imposed by the system's maximum sample rate and the Nyquist criteria, any waveform may be produced using these techniques. The objective of this inquiry, within a particular set of constraints, is to extend the cost/performance envelope of direct digital synthesis techniques for the generation of arbitrary waveforms. Performance is enhanced, particularly in the areas of output bandwidth and signal purity.

Silicon Germanium BiCMOS technology has been demonstrated as an ideal platform for highly integrated systems requiring both high performance analog and RF circuits as well as large-scale digital functionality. Frequency synthesizers are ideal candidates for this technology because the mixed-signal nature of modern frequency synthesis designs fundamentally requires both digital and analog signal processing. This research targets three areas to improve SiGe frequency synthesizers. A majority of this work focuses on applying SiGe frequency synthesizers to extreme environment applications such as space, where low temperatures and ionizing radiation are significant design issues to contend with. A second focus area involves using SiGe HBTs to minimize noise in frequency synthesizer circuits. Improved low frequency "pink" noise in SiGe HBTs provide a significant advantage over CMOS devices, and frequency synthesis circuits are significantly affected by this type of noise. However, improving thermal "white" noise is also considered. Finally, an analysis of AM-PM distortion is considered for SiGe HBTs. The studies presented focus on identifying the physical mechanisms of observed phenomena, such as single event transients or phase noise characteristics in oscillators. The ultimate goal of this research is to provide a reference of effective design parameters for circuit and system designers seeking to take advantage of the properties of SiGe device physics.

Στα πλαίσια αυτής της διπλωματικής εργασίας μελετήθηκε η θεωρία των Direct Digital Synthesizers, ενώ σχεδιάστηκε και υλοποιήθηκε ένας Dual Direct Digital Synthesizer. Στο πρώτο κεφάλαιο αναφερόμαστε με συντομία στην ιστορική εξέλιξη, στα πλεονεκτήματα και τις εφαρμογές της τεχνολογίας DDS. Στο δεύτερο κεφάλαιο αναλύουμε τον τρόπο λειτουργίας ενός συνθέτη DDS και στην συνέχεια δίνουμε έμφαση, στα λειτουργικά μπλόκ που τον αποτελούν και στο μοντέλο θορύβου του. Στην συνέχεια αναφέρουμε το πρωτόκολλο επικοινωνίας του Dual Synthesizer με τον υπολογιστή καθώς ο έλεγχος πραγματοποιείται απο PC. Η ιδέα αυτή αποτελεί μέρος, ενός μεγαλύτερου σχεδιόυ που διεξάγεται στο Εργαστήριο Ηλεκτρονικών Εφαρμογών του τμήματος Ηλεκτρολόγων Μηχανικών του Πανεπιστημίου Πατρών. Στόχος της ιδέας αυτής είναι η δημιουργία ενος Εργαστηρίου Ηλεκτρονικών Οργάνων (Desktop Lab) το οποίο αφενός δεν θα υστερεί σε τίποτα απο τα συνηθισμένα εργαστήρια αφετέρου ο οποιοσδήποτε θα μπορεί να έχει πρόσβαση σε αυτό μέσω διαδικτύου. Στο τέταρτο κεφάλαιο γίνεται αναφορά του σχεδιασμού του Hardware της γεννήτριας, ενώ στο πέμπτο επικεντρονόμαστε στον προγραμματισμό του FPGA του συστήματος. Στο έκτο κεφάλαιο αναλύεται το software του Dual Synthesizer. Τέλος στο έβδομο κεφάλαιο παραθέτουμε μερικές μετρήσεις που επιβεβαιώνουν την ορθότητα της σχεδίασης και της κατασκευής. / Throughout this dissertation the theody of Direcl Digital Synthesizers was studied while at the same time a Dual Direct Digital Synthesizer was designed and implemented. In the first part we briefly mentioned the evolution, the advantages and some applications of DDS technology. In the second part we analyzed the method of operation of DDS synthesizer and followed up by placing emphasis on the operational blocks which it consists of, and the noise model. After which we noted the communication protocol of the Dual Synthesizer with the computer since it tis controlled by it. This concept is part of a greater ongoing plan in the applied Electronics Laboratory of the department of Electrical Engineering of Upatras. The goal of this idea is the development of an electronic instrument laboratory which would not only have everything a conventional laboratory would have but also could be accessed through the internet. In the fourth part we noted the design of the hardware while in the fifth part, we focused on the programming of the FPGA of the system. In the sixth part we analyzed the software of the Dual Synthesizer. Finally in the seventh part we depicted some measurements that validate the accuracy of the design and implementation.