Les MOSFET en SiC sont appelées à remplacer les IGBT en Silicium pour des applications de demandant une plus forte vitesse de commutation. Cependant, les MOSFET en SiC ont encore quelques problèmes de fiabilité, tels que la robustesse de la diode interne ou bien la robustesse de l'oxyde de grille. Cette dernière est liée à l’oxyde de grille des composants du type MOSFET. Des instabilités de la tension de seuil sont aussi signalées. Cette thèse aborde ces deux sujets sur des MOSFET commerciaux 1200 V. L'étude de la diode interne met en évidence que les caractéristiques I-V (de la diode intrinsèque) demeurent stables après l'application d'un stress. Cependant, une dérive surprenante de la tension de seuil apparaît. Des tests complémentaires, en stressant le canal à la place de la diode, avec les mêmes contraintes n'ont pas montré de dérive significative de la tension de seuil. Donc, l'application d'un stress en courant quand le composant est en mode d'accumulation semble favoriser l'apparition des instabilités de la tension de seuil. La robustesse de l'oxyde de grille concerne les instabilités de la tension de seuil, mais aussi l'estimation de la durée de vie à des conditions d'opération nominales. Les résultats obtenus montrent que la durée de vie de l'oxyde de grille n'est plus un problème. Pourtant, le suivi du courant de grille pendant les tests ainsi que les caractérisations de la capacité de grille mettent en évidence des translations de la courbe C(V) à cause des phénomènes d’injection des porteurs et de piégeage, mais aussi la possible présence d’ions mobiles. Aussi, une bonne analyse des dégradations et dérives liées à l’oxyde de grille doit être réalisée. / SiC power MOSFETs are called to replace Si IGBT for some medium and high power applications (hundreds of kVA). However, even if crystallographic defects have been drastically reduced, SiC MOSFETs are always concerned by some robustness issues such as the internal diode robustness or the robustness of the gate oxide. The last one especially affects MOSFETs devices and is linked to the apparition of instabilities in the threshold voltage. This thesis focuses on these two issues. The study of the internal diode robustness highlighted that the I-V curve (of the intrinsic diode) remains stable after the application of a current stress in static mode, but also with the DUT placed in a converter with inductive switchings. These are the most stressful conditions. However, a surprising drift in the threshold voltage has been observed when some devices operates under these conditions; in static mode or in a converter. Complementary tests stressing the channel instead of the internal diode in the same temperature and dissipated power, have not resulted in a drift of the threshold voltage. Thus, the application of a current stress when the device is in accumulation regime could favour the apparition of instabilities in the threshold voltage. The study of the gate oxide focus in the instabilities of the threshold voltage, but also on the expected lifetime of the oxide at nominal conditions. Results obtained shown that the expected lifetime (TDDB) of the oxide is no longer a problem. Indeed, tests realized in static mode, but also in a converter under inductive switching conditions resulted in expected lifetimes well above 100 years. However, the monitoring of the gate current during the test and gate capacitance characterizations C(V) highlighted a shift in the capacitance due to carrier injection and trapping phenomena and probably to the presence of mobile-ions. Still regarding the instabilities of the threshold voltage, classic tests resulted in no significant variations of the threshold voltage at 150 _C. However, at 200 _C the drift observed for some manufacturers is higher than +30%. This is unacceptable for high-temperature applications and evidence that the quality of the gate oxide and the SiC=SiO2 interface must continue to be improved, together with the manufacturing methods to minimize the presence of mobile ions in the substrate.

In the last three decades, the electronic industry has registered a tremendous progress. The continuous and aggressive downsizing of the transistor feature sizes (CMOS scaling) has been the main driver of the astonishing growth and advancement of microelectronic industry. Currently, the CMOS scaling is almost reaching its limits. The gate oxide is now only a few atomic layers thick, and this extremely thin oxide causes a huge leakage current through the oxide. Therefore, a further reduction of the gate oxide thickness is extremely difficult and new materials with higher dielectric constant are being explored. However, the phenomena of oxide breakdown and reliability are still serious issues in these thin oxides. Oxide breakdown exhibits a soft breakdown behavior at low voltages, and this is posing as one of the most crucial reliability issues for scaling of the ultra-thin oxides. In addition, the stress-induced leakage current (SILC) due to oxide has emerged as a scaling problem for the non-volatile memory technologies. In this dissertation, a percolation modeling approach is introduced to study and understand the dramatic changes in the conductivity of a disordered medium. Two different simulation methods of percolative conduction, the site and bond percolation, are studied here. These are used in simulating the post-breakdown conduction inside the oxide. Adopting a Monte-Carlo method, oxide breakdown is modeled using a 2-D percolation theory. The breakdown statistics and post-breakdown characteristics of the oxide are computed using this model. In this work, the effects of different physical parameters, such as dimension and the applied stress are studied. The simulation results show that a thinning of oxide layer and increasing the oxide area result in softening of breakdown. It is observed that the breakdown statistics appear to follow Weibull characteristics. As revealed by simulations, the Weibull slope changes linearly with oxide thickness, while not having a significant change when the area is varied and when the amount of the applied stress is varied. It is shown that the simulation results are well correlated with the experimental data reported in the literature. In this thesis, studying the conduction through the oxide using percolation model, it was discovered that a critical or a quasi-critical phenomenon occurs depending on the oxide dimensions. The criticality of the phase-transition results in a hard breakdown while the soft breakdown occurs due to a quasi-critical nature of percolation for ultra-thin oxides. In the later part of the thesis, a quantum percolation model is studied in order to explain and model the stress induced leakage current. It is explained that due to the wave nature of electrons, the SILC can be modeled as a tunneling path through the stressed oxide with the smaller tunneling threshold compared to the virgin oxide. In addition to the percolation model, a Markov chain theory is introduced to simulate the movement of electron as a random walk inside the oxide, and the breakdown is simulated using this random-walk of electron through the accumulated traps inside the oxide. It is shown that the trapping-detrapping of electrons results in an electrical noise in the post-breakdown current having 1/f noise characteristics. Using simulation of a resistor network with Markov theory, the conductance of the oxide is computed. An analytical study of a 2-D site percolation system is conducted using recursive methods and useful closed-form expressions are derived for specialized networks.

In the last three decades, the electronic industry has registered a tremendous progress. The continuous and aggressive downsizing of the transistor feature sizes (CMOS scaling) has been the main driver of the astonishing growth and advancement of microelectronic industry. Currently, the CMOS scaling is almost reaching its limits. The gate oxide is now only a few atomic layers thick, and this extremely thin oxide causes a huge leakage current through the oxide. Therefore, a further reduction of the gate oxide thickness is extremely difficult and new materials with higher dielectric constant are being explored. However, the phenomena of oxide breakdown and reliability are still serious issues in these thin oxides. Oxide breakdown exhibits a soft breakdown behavior at low voltages, and this is posing as one of the most crucial reliability issues for scaling of the ultra-thin oxides. In addition, the stress-induced leakage current (SILC) due to oxide has emerged as a scaling problem for the non-volatile memory technologies. In this dissertation, a percolation modeling approach is introduced to study and understand the dramatic changes in the conductivity of a disordered medium. Two different simulation methods of percolative conduction, the site and bond percolation, are studied here. These are used in simulating the post-breakdown conduction inside the oxide. Adopting a Monte-Carlo method, oxide breakdown is modeled using a 2-D percolation theory. The breakdown statistics and post-breakdown characteristics of the oxide are computed using this model. In this work, the effects of different physical parameters, such as dimension and the applied stress are studied. The simulation results show that a thinning of oxide layer and increasing the oxide area result in softening of breakdown. It is observed that the breakdown statistics appear to follow Weibull characteristics. As revealed by simulations, the Weibull slope changes linearly with oxide thickness, while not having a significant change when the area is varied and when the amount of the applied stress is varied. It is shown that the simulation results are well correlated with the experimental data reported in the literature. In this thesis, studying the conduction through the oxide using percolation model, it was discovered that a critical or a quasi-critical phenomenon occurs depending on the oxide dimensions. The criticality of the phase-transition results in a hard breakdown while the soft breakdown occurs due to a quasi-critical nature of percolation for ultra-thin oxides. In the later part of the thesis, a quantum percolation model is studied in order to explain and model the stress induced leakage current. It is explained that due to the wave nature of electrons, the SILC can be modeled as a tunneling path through the stressed oxide with the smaller tunneling threshold compared to the virgin oxide. In addition to the percolation model, a Markov chain theory is introduced to simulate the movement of electron as a random walk inside the oxide, and the breakdown is simulated using this random-walk of electron through the accumulated traps inside the oxide. It is shown that the trapping-detrapping of electrons results in an electrical noise in the post-breakdown current having 1/f noise characteristics. Using simulation of a resistor network with Markov theory, the conductance of the oxide is computed. An analytical study of a 2-D site percolation system is conducted using recursive methods and useful closed-form expressions are derived for specialized networks.

The impact of physical design characteristics on backend dielectric reliability was modeled. The impact of different interconnect geometries on backend low-k time dependent dielectric breakdown was reported and modeled. Physical design parameters that are crucial to backend dielectric reliability were identified. A methodology was proposed for determining chip reliability but combining the insights gathered by modeling the impact of physical design on backend dielectric breakdown. A methodology to model variation in device parameters and characteristics was proposed. New methods of electrical and physical parameter extraction were proposed. Models that consider systematic and random source of variation in electrical and physical parameters of CMOS devices were proposed, to aid in circuit design and timing analysis.

Afin de pouvoir continuer la miniaturisation de la brique de base des circuits électroniques, le transistor MOS, l'introduction d'oxyde de grille à haute permittivité était inévitable. Un empilement de type high-k/grille métal en remplacement du couple SiO2 /Poly-Si est introduit afin de limiter le courant de fuite tout en conservant un bon contrôle électrostatique du canal de conduction. L'introduction de ces matériaux pose naturellement des questions de fiabilité des dispositifs obtenus et ce travail s'inscrit dans ce contexte. Afin de réaliser des mesures de durée de vie sans avoir à finir les dispositifs, une méthode utilisant le C-AFM sous ultravide est proposée. Le protocole expérimental repose sur une comparaison systématique des distributions des temps de claquage obtenues à l'échelle du composant et à l'échelle nanométrique. La comparaison systématique des mesures s'avère fiable si l'on considère une surface de contact entre la pointe et le diélectrique de l'ordre du nm². Des distributions de Weibull présentant une même pente et un même facteur d'accélération en tension sont rapportées montrant une origine commune pour le mécanisme de rupture aux deux échelles.Une résistance différentielle négative, précédant la rupture diélectrique, est rapportée lors de mesures courant-tension pour certaines conditions de rampe. Ce phénomène de dégradation de l'oxyde, visible grâce au C-AFM , est expliqué et modélisé dans ce manuscrit par la croissance d'un filament conducteur dans l'oxyde. Ce même modèle permet aussi de décrire la rupture diélectrique.Finalement, l'empilement de grille bicouche du noeud 28nm est étudié. Une preuve expérimentale montrant que la distribution du temps de claquage du bicouche est bien une fonction des caractéristiques de tenue en tension propres de chaque couche est présentée.

Methods for reliability assessment and a deep understanding of degradation mechanisms are important for product and process development. In this work, reliability under electrical stress of a state-of-the-art integrated low-temperature PVD PZT Film stack is discussed. DC and AC lifetime under electric stress are investigated experimentally over wide ranges of temperature and applied electric field. Empirical Weibull analysis and comparison of the obtained Weibull slope is used to evaluate suitable acceleration ranges for empirical testing. Changes of the Weibull slope above a temperature of 150 °C and gradual change over voltage acceleration in the range of 100 kV/cm to 200 kV/cm were found. This indicates that accelerated lifetime testing in the temperature range below 150 °C is possible and caution is required for voltage acceleration. The results of this study are also published in Ref. (a). Closing the literature gap, time to breakdown data under unipolar AC electric stress is presented. Comparison with results obtained under DC electric stress reveals that the DC degradation mechanism still dominates under unipolar AC load. This observation was found to hold over tested AC frequency, DC offset, and temperature ranges. As consequence, AC lifetime can be predicted based on DC time to breakdown experiments (b). To enhance the physical understanding of degradation and breakdown, variation of the leakage current over time during electrical load is analyzed. An enhanced physical model for leakage current degradation is proposed and degradation kinetics are studied experimentally. For the first time, more than one defect species being active and manifesting in leakage current degradation of perovskite oxides are proposed and experimental evidence is presented to substantiate the hypotheses. Model predictions and experimental results are found to be in excellent agreement. The proposed characterization method allows for characterization of contributing defect types by associated charge and true activation energy (c). Based on experimental observations, a direct connection between leakage current degradation mechanism and time dependent dielectric breakdown (TDDB) mechanism is proposed and formulated in a physical model. For the first time, kinetics of leakage current degradation and TDDB are successfully linked, using new evaluation methods for the experimental data obtained under DC and AC electrical stress. This pioneering connection between leakage current and breakdown ultimately leads to the fundament of a comprehensive HALT model. Fundamental implications of the new findings on reliability testing of high-k dielectrics are discussed. / Methoden zur Zuverlässigkeitsbewertung und ein tiefes Verständnis der Degradationsmechanismen sind wichtig für die Produkt- und Prozessentwicklung. In dieser Arbeit wird die Zuverlässigkeit eines auf dem Stand der Technik befindlichen integrierten niedertemperatur PVD PZT Dünnschichtstapels unter elektrischer Last diskutiert. Lebenszeit unter Gleichstrom- (DC) und Wechselstromlast (AC) werden experimentell über weite Bereiche der Temperatur und angelegter Feldstärke untersucht. Empirische Weibull Analyse und Vergleich der erhaltenen Weibull-Module werden verwendet, um Beschleunigungsbereiche für empirische Testverfahren zu bewerten. Eine Veränderung der Weibull-Module oberhalb von 150 °C und eine graduelle Veränderung für Spannungsbeschleunigung im Bereich von 100 kV/cm bis 200 kV/cm wurden festgestellt. Dies weist darauf hin, dass beschleunigte Lebenszeittests im Temperaturbereich unterhalb von 150 °C möglich sind, Spannungsbeschleunigung jedoch mit hoher Vorsicht zu bewerten ist. Die Ergebnisse dieser Untersuchung sind ebenfalls in Ref. (a) veröffentlicht. Durch die Präsentation von Durchbruchzeiten unter unipolarer AC-Belastung wird eine Forschungslücke geschlossen. Ein Vergleich mit Ergebnissen, die unter Gleichstrombelastung erhoben wurden zeigt, dass Degradationsmechanismen, die unter DC aktiv sind unter unipolarer AC-Belastung das Durchbruchverhalten weiterhin dominieren. Diese Beobachtung hat Bestand über die untersuchten Bereiche von AC-Frequenz, DC-Versatz und Temperatur. Daraus folgt, dass Lebenszeit unter AC-Belastung durch Experimente unter DC vorhergesagt werden kann (b). Um das physikalische Verständins von Degradation und Durchbruch zu erweitern, wird die Veränderung des Leckstroms über elektrischer Belastungszeit analysiert. Ein erweitertes physikalisches Modell für die Leckstromdegradation wird vorgeschlagen und die Degradationskinetik wird experimentell untersucht. Zum ersten Mal, werden mehr als zwei aktive Defektarten, die sich in der Leckstromdegradation von Perowskit Oxiden abzeichnen eingebracht und durch experimentelle Befunde untermauert. Modellvorhersagen und experimentelle Ergebnisse zeigen eine exzellente Übereinstimmung. Die vorgeschlagene Charakterisierungsmethode erlaubt die Charakterisierung der beteiligten Defektarten über zugeordneter Ladung und wahrer Aktivierungsenergie (c). Basierend auf experimentellen Beobachtungen wird ein direkter Zusammenhang zwischen Leckstromdegradation und zeitabhängigem dielektrischen Durchbruchmechanismus (TDDB) vorgeschlagen und in einem physikalischen Modell abgebildet. Zum ersten Mal werden die Kinetik hinter Leckstromdegradation und TDDB über neue Auswerteverfahren der erhobenen experimentellen Daten unter DC- und AC-Belastung erfolgreich verknüpft. Dieser wegweisende Zusammenhang zwischen Leckstromdegradation und Durchbruch legt das Fundament zu einer verständnisbasierten stark beschleunigten Grenzlastprüfung. Grundlegende Auswirkungen der neuen Ergebnisse auf Zuverlässigkeitstestmethoden von high-k Dielektrika werden diskutiert.