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11	High Speed On-Chip Measurment Circuit / Inbyggd krets för höghastighetsmätning på chip Stridfelt, Arvid January 2005 (has links) <p>This master thesis describes a design exploration of a circuit capable of measuring high speed signals without adding significant capacitive load to the measuring node. </p><p>It is designed in a 0.13 CMOS process with a supply voltage of 1.2 Volt. The circuit is a master and slave, track-and-hold architecture incorporated with a capacitive voltage divider and a NMOS source follower as input buffer to protect the measuring node and increase the input voltage range. </p><p>This thesis presents the implementation process and the theory needed to understand the design decisions and consideration throughout the design. The results are based on transistor level simulations performed in Cadence Spectre. </p><p>The results show that it is possible to observe the analog behaviour of a high speed signal by down converting it to a lower frequency that can be brought off-chip. The trade off between capacitive load added to the measuring node and input bandwidth of the measurment circuit is also presented.</p> Electronics CMOS 0.13 sampling periodic sampling digital oscilloscope time equivalent sampling track and hold master and slave sampling clock generator voltagedivider source follower sampling switch transmission gate RLC-line Elektronik Electronics Elektronik
12	High Speed On-Chip Measurment Circuit / Inbyggd krets för höghastighetsmätning på chip Stridfelt, Arvid January 2005 (has links) This master thesis describes a design exploration of a circuit capable of measuring high speed signals without adding significant capacitive load to the measuring node. It is designed in a 0.13 CMOS process with a supply voltage of 1.2 Volt. The circuit is a master and slave, track-and-hold architecture incorporated with a capacitive voltage divider and a NMOS source follower as input buffer to protect the measuring node and increase the input voltage range. This thesis presents the implementation process and the theory needed to understand the design decisions and consideration throughout the design. The results are based on transistor level simulations performed in Cadence Spectre. The results show that it is possible to observe the analog behaviour of a high speed signal by down converting it to a lower frequency that can be brought off-chip. The trade off between capacitive load added to the measuring node and input bandwidth of the measurment circuit is also presented. Electronics CMOS 0.13 sampling periodic sampling digital oscilloscope time equivalent sampling track and hold master and slave sampling clock generator voltagedivider source follower sampling switch transmission gate RLC-line Elektronik Electronics Elektronik
13	Etude, Conception et Caractérisation de circuits pour la Conversion Analogique Numérique à très hautes performances en technologie TBH InP 0.7µm / Study, Design and Characterization of high performances ADC integrated circuits in 0.7 µm-InP-HBT technology Deza, Julien 13 June 2013 (has links) Ce travail de thèse concerne les circuits ultra-rapides pour la conversion analogique numérique performante en technologie bipolaire à hétérojonctions sur substrat Indium Phosphore (TBDH/InP). L'étude s'intéresse à la fonction principale qui est l'échantillonnage blocage. Elle a été menée par simulation de l'ensemble des blocs composant cette fonction. En particulier une étude extensive des cœurs des circuits Echantillonneurs/Bloqueurs a été effectuée pour différents paramètres électriques pour aboutir à des valeurs optimales réalisant un compromis entre la bande passante la résolution et la linéarité.Des architectures de circuits Echantillonneurs/Bloqueurs (E/B) avec ou sans l'étage d'amplification à gain variable ont été conçues, optimisées, réalisées et caractérisées et des performances à l'état de l'art ont été obtenues : des circuits E/B de bande passante supérieure à 50 GHz et cadencées à 70 Gs/s ont été réalisés pour les applications de communications optiques et des circuits de bande passante supérieure à 16 GHz cadencés à (2-8) Gs/s ont été réalisés pour la transposition de fréquence. / This thesis concerns the design of high speed circuits in Indium phosphide heterojunction Bipolar technology for High performance analog to digital conversion (ADC).The study focuses on the Track and Hold block (THA) which is the main function of the ADC. The study was conducted by simulating all blocks of the THA circuit. In particular, an extensive study of the THA main block was performed for various electrical parameters to achieve optimal conditions in order to obtain a good tradeoff between resolution bandwidth and linearity. THA architectures circuits with or without Voltage Gain Amplifier stage were designed, optimized and characterized. High THA performances were achieved: THA circuit with a bandwidth greater than 50 GHz at 70 Gs/s were achieved for optical communications and circuits of bandwidth more than16 GHz at (2-8 GS /s) have been realized for down conversion operation. Échantillonneur bloqueur (E/B) Sef Amplificateur à gain variable (VGA) InP Tbh Analog-to-digital converter (ADC) Track-and-hold amplifier (THA) Variable gain amplifier (VGA) Switched emitter follower (SEF) InP Hbt
14	Design of a Low Power, High Performance Track-and-Hold Circuit in a 0.18µm CMOS Technology / Design av en lågeffekts högprestanda track-and-hold krets i en 0.18µm CMOS teknologi. Säll, Erik January 2002 (has links) This master thesis describes the design of a track-and-hold (T&H) circuit with 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. The circuit is supposed to work together with a 10bit pipelined analog to digital converter. A switched capacitor topology is used for the T&H circuit and the amplifier is a folded cascode OTA with regulated cascode. The switches used are of transmission gate type. The thesis presents the design decisions, design phase and the theory needed to understand the design decisions and the considerations in the design phase. The results are based on circuit level SPICE simulations in Cadence with foundry provided BSIM3 transistor models. They show that the circuit has 10bit resolution and 7.6mW power consumption, for the worst-case frequency of 30MHz. The requirements on the dynamic performance are all fulfilled, most of them with large margins. Electronics track-and-hold CMOS 0.18 low power high performance 10-bit folded cascode switch theory correlated double sampling CDS fully differential gain boosting regulated cascode transmission gate transmission gate switch clock generator clock driver bias bias circuit amplifier design switch design common mode feedback CMFB 80MSPS 80MS/s Elektronik Electronics Elektronik
15	Design of a Low Power, High Performance Track-and-Hold Circuit in a 0.18µm CMOS Technology / Design av en lågeffekts högprestanda track-and-hold krets i en 0.18µm CMOS teknologi. Säll, Erik January 2002 (has links) <p>This master thesis describes the design of a track-and-hold (T&H) circuit with 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. The circuit is supposed to work together with a 10bit pipelined analog to digital converter. </p><p>A switched capacitor topology is used for the T&H circuit and the amplifier is a folded cascode OTA with regulated cascode. The switches used are of transmission gate type. </p><p>The thesis presents the design decisions, design phase and the theory needed to understand the design decisions and the considerations in the design phase. </p><p>The results are based on circuit level SPICE simulations in Cadence with foundry provided BSIM3 transistor models. They show that the circuit has 10bit resolution and 7.6mW power consumption, for the worst-case frequency of 30MHz. The requirements on the dynamic performance are all fulfilled, most of them with large margins.</p> Electronics track-and-hold CMOS 0.18 low power high performance 10-bit folded cascode switch theory correlated double sampling CDS fully differential gain boosting regulated cascode transmission gate transmission gate switch clock generator clock driver bias bias circuit amplifier design switch design common mode feedback CMFB 80MSPS 80MS/s Elektronik Electronics Elektronik

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