Réalisées au début du processus de fabrication des circuits intégrés, les tranchées d'isolation permettent d'éviter les fuites de courant latérales qui pourraient avoir lieu entre les transistors. Les tranchées sont remplies par un film d'oxyde de silicium réalisé par des procédés de dépôt chimiques en phase vapeur (aussi appelés CVD). Le remplissage des tranchées est couramment réalisé par un procédé CVD à pression sub-atmosphérique (SACVD TEOS/O3). Cependant, la capacité de remplissage de ce procédé pour les nœuds technologiques CMOS 28 nm et inférieurs est dégradée à cause de profils trop verticaux dans les tranchées. Cela induit la formation de cavités dans l'oxyde et entraine des courts-circuits. Afin de pallier ce problème, une nouvelle stratégie de remplissage en trois étapes est proposée pour la technologie CMOS 14 nm. Dans la première étape, un film mince d'oxyde est déposé dans les tranchées. Puis, dans la deuxième étape, les flancs du film sont gravés à l'aide d'un procédé de gravure innovant, basé sur un plasma délocalisé de NF3/NH3, permettant de créer une pente favorable au remplissage final réalisé au cours de la troisième étape. Le développement de cette nouvelle stratégie de remplissage s'est déroulé selon plusieurs axes. Tout d'abord, le procédé de dépôt a été caractérisé afin de sélectionner les conditions optimales pour la première étape de la stratégie. Puis, le procédé de gravure innovant a été caractérisé en détail. L'influence des paramètres de gravure a été étudiée sur pleine plaque et sur plaques avec motifs afin de comprendre les mécanismes de gravure et de changement de pente dans les tranchées. Enfin, dans un troisième temps, la stratégie de remplissage a été développée et intégrée pour la technologie CMOS 14 nm. Nous montrons ainsi qu'il est possible de contrôler le changement de pente avec les conditions de gravure et que cette stratégie permet un remplissage des tranchées d'isolation sans cavités. / Achieved at the beginning of the integrated circuits manufacturing, shallow trench isolation permits to electrically isolate transistors from each other's to avoid current leakage. Trenches are filled with silicon dioxide film deposited by chemical vapor deposition (also called CVD). Trenches gap-filling is usually performed by TEOS/O3 Sub-Atmospheric Chemical Vapor Deposition (TEOS/O3 SACVD). However, trenches gap-filling with SACVD process reveals some limitations for advanced technology nodes (mainly 28 nm & 14 nm) due to quasi-vertical trenches profile and slope sensitivity of SACVD, which can lead to voids formation in gap-filling oxide and consequently to electrical isolation failure. To solve this issue, a new three steps gap-fill strategy is proposed for the CMOS 14 nm technology node. During the first step, a thin oxide liner is deposited into trenches. Then, in the second step, film sidewalls are etched with an innovative process, based on downstream plasma of NF3/NH3, to create tapered profile favorable for final SACVD gap-fill achieved in the third step. The development of this strategy has followed three work leads. First, the deposition process has been characterized to select best conditions for the first step. Then, the innovative etching process has been widely characterized. The influence of etching parameters has been studied on blanket and patterned wafers to understand etching mechanisms and slope modification. Finally, the gap-fill strategy has been developed and integrated for the CMOS 14 nm technology node. We demonstrate that it is possible to control the slope modification by tuning etching conditions and that strategy allows a void-free trenches filling.

Diffuse water pollution in urban areas is growing due to polluted runoffs. Therefore, there is a need to treat this kind of pollution. Different structural treatment practices can be used for these purposes. However, little is known about their environmental, economic and social impacts. Therefore, the aim of this study has been to develop an integrated methodology for sustainability evaluation of structural treatment practices, considering environmental, economic and social aspects. Both environmental and economic evaluations have been carried out on a life cycle basis, using life cycle assessment and life cycle costing, respectively. For social evaluation, a number of social indicators, identified and developed in this research, have been used. The methodology has been applied to the case of the Magdalena river catchment in Mexico City. Three structural treatment practices have been analysed: bio-retention unit, infiltration trench and porous pavement. Based on the assumptions and the results from this work, the bio-retention unit appears to be environmentally the most sustainable option for treatment of diffuse water pollution. It is also the second-best option for social sustainability, slightly behind the porous pavement. However, if the costs of treatment are the priority, then the porous pavement would be the cheapest option. If all the sustainability aspects evaluated here are considered of equal importance, then the bio-retention unit is the most sustainable option. Therefore, trade-offs between the different sustainability aspects are important and should be considered carefully before any decisions are made on diffuse water pollution treatment. This also includes the trade-offs with the additional life cycle impacts generated by the treatment options compared to the impacts from the untreated runoff. The decisions can only be made by the appropriate stakeholders; however, some recommendations are given, based on the outcomes of this research.

Efficient power conversion is essential to face the continuously increasing energy consumption of our society. GaN based vertical power field effect transistors provide excellent performance figures for power-conversion switches, due to their capability of handling high voltages and current densities with very low area consumption. This work focuses on a vertical trench gate metal oxide semiconductor field effect transistor (MOSFET) with conceptional advantages in a device fabrication preceded GaN epitaxy and enhancement mode characteristics. The functional layer stack comprises from the bottom an n+/n- drift/p body/n+ source GaN layer sequence. Special attention is paid to the Mg doping of the p-GaN body layer, which is a complex topic by itself. Hydrogen passivation of magnesium plays an essential role, since only the active (hydrogen-free) Mg concentration determines the threshold voltage of the MOSFET and the blocking capability of the body diode. Fabrication specific challenges of the concept are related to the complex integration, formation of ohmic contacts to the functional layers, the specific implementation and processing scheme of the gate trench module and the lateral edge termination. The maximum electric field, which was achieved in the pn- junction of the body diode of the MOSFET is estimated to be around 2.1 MV/cm. From double-sweep transfer measurements with relatively small hysteresis, steep subthreshold slope and a threshold voltage of 3 - 4 V a reasonably good Al2O3/GaN interface quality is indicated. In the conductive state a channel mobility of around 80 - 100 cm2/Vs is estimated. This obtained value is comparable to device with additional overgrowth of the channel. Further enhancement of the OFF-state and ON-state characteristics is expected for optimization of the device termination and the high-k/GaN interface of the vertical trench gate, respectively. From the obtained results and dependencies key figures of an area efficient and competitive device design with thick drift layer is extrapolated. Finally, an outlook is given and advancement possibilities as well as technological limits are discussed.:1 Motivation and boundary conditions 1.1 A comparison of competitive semiconductor materials 1.2 Vertical GaN device concepts 1.3 Target application for power switches 2 The vertical GaN MOSFET concept 2.1 Incomplete ionization of dopants 2.2 The pseudo-vertical approach 2.3 Considerations for the device OFF-state 2.3.1 The pn-junction in reverse operation 2.3.2 The gate trench MIS-structure in OFF-state 2.3.3 Dimensional constraints and field plates 2.4 Static ON-state and switching considerations 2.4.1 The pn-junction in forward operation 2.4.2 Resistance contributions 2.4.3 Device model and channel mobility 2.4.4 Threshold voltage and subthreshold slope 2.4.5 Interface and dielectric trap states in wide band semiconductors 2.4.6 The body bias effect 3 Fabrication and characterisation 3.1 Growth methods for GaN substrates and layers 3.2 Substrates and the desired starting material 3.2.1 Physical and micro-structural characterisation 3.2.2 Dislocations and impurities 3.3 Pseudo- and true-vertical MOSFET fabrication 3.3.1 Processing routes 3.3.2 Inductively-coupled plasma etching 3.3.3 Process flow modification 3.4 Electrical characterisation, structures and process control 3.4.1 Current voltage characterisation 3.4.2 C(V) measurements and charge carrier profiling 3.4.3 Cooperative characterisation structures 4 Properties of the functional layers 4.1 Morphology of the MOVPE grown layers 4.2 Hydrogen out-diffusion treatment 4.3 Morphology of the n+-source layer grown by MBE 4.4 N-type doping of the functional layers 4.5 P-type GaN by magnesium doping 4.6 Structural properties after the etching and gate module formation 4.7 Electrical layer characterization 4.7.1 Gate dielectric and interface evaluation 5 Pseudo- and true vertical device operation 5.1 Influences of the metal-line sheet resistance 5.2 Formation and characterisation of ohmic contacts 5.2.1 Ohmic contacts to n-type GaN 5.2.2 Ohmic contacts to p-GaN 5.3 The pn- body diode 5.4 MOSFET operation 5.4.1 ON-state and turn-ON operation 5.4.2 The body bias effect on the threshold voltage 5.4.3 Device OFF-state 6 Summary and conclusion 6.1 Device performance 6.2 Current limits of the vertical device technology 6.3 Possibilities for advancements Bibliography A Appendix A.1 Deduction: Forward diffusion current of the pn-diode A.2 Deduction: Operation regions in the EKV model Figures Tables Abbreviations Symbols Postamble and Acknowledgement

Abstract Beneficial Reuse of Corrugated Paperboard in Civil Engineering Applications Gregory Michael Stone An investigation was conducted to explore the potential for reuse of corrugated paperboard. Corrugated paperboard represents a large fraction of the municipal solid waste generated and discarded in the United States. Alternative applications for reuse can provide a significant benefit by reducing the volume of waste being disposed and by reducing the use of raw materials. Four civil engineering applications were examined for potential beneficial reuse of corrugated paperboard: slurry trench construction, vertical drilling, directional drilling, and controlled low strength materials (CLSM). For the purpose of this project, corrugated paperboard was pulped and added to bentonite slurry or CLSM mixtures. Bentonite slurry mixtures were tested for viscosity, density, filtrate loss, and permeability. The behavior of the bentonite slurries was greatly influenced by interaction and interlocking of corrugate fibers; in general resulting in increased viscosity, filtrate loss, and permeability and decreased density. CLSM mixtures were tested for flow consistency, unit weight, air content, and compressive strength. CLSM mixtures prepared with corrugated paperboard showed an increased water demand due to high absorption of the corrugate. The higher water content was a significant factor contributing to decreased unit weight and compressive strength. CLSM mixtures containing corrugated paperboard also exhibited increased air contents, possibly due to entrapment of air within the corrugate pulp. Corrugated paperboard was used to successfully replace up to 27% of bentonite for slurry trench applications, 60% of bentonite for vertical drilling applications, and 59% of bentonite for directional drilling applications while maintaining acceptable engineering properties. For CLSM mixtures up to 1% of fine aggregate was replaced with corrugated paperboard while maintaining satisfactory engineering properties. Incorporation of corrugated paper board into bentonite slurry, CLSM, and drilling fluid applications provides a viable option for beneficial reuse.

As the world’s population is migrating more into urban areas, landcover changes follow. Natural pervious areas are being converted to impervious areas, which when subjected to rain generates more stormwater runoff. Stormwater management is a problem that cities today are challenged with, infrastructure is getting older and precipitation patterns are changing due to climate change. Due to climate change extreme precipitation events are likely to increase and therefore increase the probability of urban flooding. Urban flooding can be caused by extreme precipitation events with a short duration, or so-called flash floods. These flash floods can overwhelm the drainage system in place which therefore can cause flooding. This problem has inspired engineers to rethink stormwater management, moving from traditional grey drainage systems to more green and sustainable drainage systems. Sustainable Urban Drainage System (SuDS) are drainage systems that aim to regain the properties of non-urbanised areas, retain the natural hydrological cycle, and have recreational values for the surrounding societies. This study investigated how different SuDS behave when subjected to flash floods. A model of a synthetic case study was built in the Storm Water Management Model (SWMM) and sustainable urban drainage systems implemented. The solutions investigated were bioretention cells, rain gardens, infiltration trenches, green roofs, and permeable pavements. Three different rain events were analysed, all with different precipitation depth but with the same duration of 1 hour. Results showed that bioretention cells could reduce runoff volumes to the highest extent while green roofs could reduce the peak runoff the most. Other results were analysed like efficiency and cost. Bioretention cell came out on top in efficiency but had the highest cost. Overall, all the solutions showed promise in reducing runoff during flash floods, but the reduction capacity goes down with increased precipitation. / När en större del av världens befolkning flyttar in till tätortsområden så medföljer en ändring av markytans beskaffenhet. Vanligtvis genomträngliga ytor omvandlas till hårdgjorda ytor vilket generar mer dagvattenavrinning när de utsätts för regn. Dagvattenhanteringen är en utmaning för många städer idag eftersom infrastrukturen blir äldre och nederbördsmönstren förändras på grund av klimatförändringar. Extrema nederbördshändelser väntas öka med anledning av dessa klimatförändringar och ökar därigenom sannolikheten för översvämningar i städer. Översvämningar i städer kan orsakas av korta nederbördshändelser med hög intensitet, så kallade Skyfall, vilket kan överbelasta dagvattensystemets kapacitet. Det har lett till att ingenjörer ändrat sitt tankesätt på hur dagvatten ska hanteras och börjat gå från konventionella till mer gröna och hållbara dräneringssystem. Hållbar dagvattenhantering är dräneringssystem som syftar till att använda egenskaperna hos naturliga områden, behålla det naturliga hydrologiska kretsloppet och skapa rekreationsvärden för de omkringliggande samhällena. Denna studie har undersökt hur olika hållbara dräneringssystem beter sig när de utsätts för översvämningar. En modell på en syntetisk fallstudie byggdes i Storm Water Management Model (SWMM) där hållbara dräneringssystem implementerades i en urban miljö. Lösningarna som undersöktes var biofilterbäddar, regnträdgårdar, infiltrationsbäddar, gröna tak och permeabla trottoarer. Tre olika nederbördshändelser analyserades, alla med olika nederbördsmängder men med samma varaktighet på en timme. Resultaten visade att biofilterbäddar kunde minska avrinningsvolymerna i största grad medan gröna tak minskade ytavrinningen mest. Effektivitet och kostnad analyserades också. Där visade biofilterbäddarna högst effektivitet men hade den högsta kostnaden. Sammantaget visade det sig att alla lösningar var lovande vad gäller minskning av avrinning under översvämningar, men reduktionskapaciteten minskar med ökad nederbörd.

Evolutions in integrated circuit technology require the use of a high-frequency synchronous buck converter in order to achieve low cost, low profile, fast transient response and high power density. However, high frequency operation leads to increased power MOSFET switching losses. Optimization of the MOSFETs plays an important role in improving converter performance. This dissertation focuses on revealing the power loss mechanism of power MOSFETs and the relationship between power MOSFET structure and its power loss. The analytical device model, combined with circuit modeling, cannot reveal the relationship between device structure and its power loss due to the highly non-linear characteristics of power MOSFETs. A physically-based mixed device/circuit modeling approach is used to investigate the power losses of the MOSFETs under different operating conditions. The physically based device model, combined with SPICE-like circuit simulation, provides an expeditious and inexpensive way of evaluating and optimizing circuit and device concepts. Unlike analytical or other SPICE models of power MOSFETs, the numerical device model, relying little on approximations or simplifications, faithfully represents the behavior of realistic power MOSFETs. The impact of power MOSFET parameters on efficiency of synchronous buck converters, such as gate charge, on resistance, reverse recovery, is studied in detail in this thesis. The results provide a good indication on how to optimize power MOSFETs used in VRMs. The synchronous rectifier plays an important role in determining the performance of the synchronous buck converter. The reverse recovery of its body diode and the Cdv/dt induced false trigger-on are two major mechanisms that impact SyncFET's performance. This thesis gives a detailed analysis of the SyncFET operation mechanism and provides several techniques to reduce its body-diode influence and suppress its false Cdv/dt trigger-n. This thesis also investigates the influence of several circuit level parameters on the efficiency of the synchronous buck converter, such as input voltage, circuit parasitic inductance, and gate resistance to provide further optimization of synchronous buck converter design.

The third quadrant (3rd-quad) conduction (or reverse conduction) of power transistors is critical for synchronous power converters. For power metal-oxide-semiconductor field-effect-transistors (MOSFETs), there are two current paths in the 3rd-quad conduction, namely the MOS channel path and the body diode path. It is well known that, for 1.2 kV silicon carbide (SiC) planar MOSFETs, the conduction loss in the 3rd-quad is reduced by turning on the MOS channel with a positive gate bias (VGS) and keeping the dead time as small as possible. Under this scenario, the current is conducted through both paths, allowing the device to take advantage of the zero 3rd-quad forward voltage drop (VF3rd) of the MOS channel path and the small differential resistance of the body diode path. However, in this thesis work, this popular belief is found to be invalid for power MOSFETs with higher voltage ratings (e.g., 3.3 kV and 10 kV), particularly at high temperatures and current levels. The aforementioned MOS channel and body diode paths compete in the device’s 3rd-quad conduction, and their competition is affected by VGS and device structure. This thesis work presents a comparative study on the 3rd-quad behavior of 1.2 kV to 10 kV SiC planar MOSFET through a combination of device characterization, TCAD simulation and analytical modeling. It is revealed that, once the MOS channel turns on, it changes the potential distribution within the device, which further makes the body diode turn on at a source-to-drain voltage (VSD) much higher than the built-in potential of the pn junction. In 10 kV SiC MOSFETs, with the MOS channel on, the body diode does not turn on over the entire practical VSD range. As a result, the positive VGS leads to a completely unipolar conduction via the MOS channel, which could induce a higher VF3rd than the bipolar body diode at high temperatures. Circuit test is performed, which validates that a negative VGS control provides the smallest 3rd-quad voltage drop and conduction loss at high temperatures in 10 kV SiC planar MOSFET. The study is also extended to the trench MOSFET, another major structure of commercial SiC MOSFETs. Based on the revealed physics for planar MOSFETs, the optimal VGS control for the 3rd-quad conduction in different types of commercial trench MOSFETs is discussed, which provides insights for the design of high-voltage trench MOSFETs. These results provide key guidelines for the circuit applications of medium-voltage SiC power MOSFETs. / M.S. / Recent years, the prosperity of power electronics applications such as electric vehicle and smart grid has led to a rapid increase in the adoption of wide bandgap (WBG) power devices. Silicon Carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) is one of the most attractive candidates in WBG devices, owing to its good tradeoff between breakdown voltage and on resistance, capability of operation at high temperatures, and superior device robustness over other WBG power devices. In most power converters, power device is required to conduct current in its third quadrant (3rd-quad) (i.e., conduct reverse current) either for handling current during the dead time or acting as a commutation switch. In a SiC MOSFET, there are two current paths in the 3rd-quad conduction, namely the MOS channel path and the body diode path. It is widely accepted that by turning on the MOS channel with a positive gate-to-source bias (VGS), both paths are turned on in parallel such that the 3rd-quad conduction loss can be reduced. In this thesis work, it is shown that this long-held opinion does not hold for SiC MOSFETs with high voltage ratings (e.g., 3.3 kV and 10 kV). Through a combination of device characterization, TCAD simulation, and analytical modeling, this thesis work unveils the competing current sharing between the MOS channel and the body diode. Once the MOS channel turns on, it delays the turn-on of the body diode and suppresses the diode current. This effect is more pronounced in MOSFETs with higher voltage ratings. In 10 kV SiC MOSFETs, with the MOS channel on, the body diode does not turn on in the practical operation conditions. At high temperatures, as the bipolar diode path possesses the conductivity modulation, which can significantly lower the voltage drop and is absent in the MOS channel, it would be optimal to turn off the MOS channel. Circuit test is also performed to validate these device findings and evaluate their impact on device applications. Finally, the study is also extended to the commercial SiC trench MOSFET, the other mainstream type of SiC power MOSFETs. These results provide key guidelines for the circuit applications of medium-voltage SiC power MOSFETs.

Samples from 13 different sites along the south coast of West Java yield 7 candidate paleo-tsunami sands, which may represent 4 different paleo-tsunami events. Ages obtained from one deposit may document a tsunami and coastal subsidence from an earthquake in 1,053 AD. The tsunami deposit from this event is preserved in an uplifted marine terrace exposed at Panto Cape, Banten Province. We speculated that the terrace has been uplifted about 4.6 m to the present height of 2 m above sea level, since the 1053 AD event at a rate of 4.8 mm/a. This uplift is strong evidence that strain is accumulating at the Java Trench and enough has already accumulated to generate a megathrust earthquake event.Numerical models using ComMIT of possible megathrust earthquake scenarios were constructed using the 2004 Sumatra earthquake, 30-m fault slip, and the 2011 Japan earthquake as proxies. These three scenarios yield earthquakes of Mw 9.3, 9.5 and 8.9, respectively. The worst case scenario is used to estimate the extent of tsunami inundation of the SW coast of Java, which totals 643 km2. The total number of people who inhabit the inundation area is around 451,000. Some coastal configurations cause a no escape situation where the modeled tsunami arrives in less than 20 minutes, which is not enough time for those near the coast to escape far enough inland or to a sufficient elevation to avoid the tsunami. These areas include the coastlines of Sukabumi, Cianjur and west Garut Regencies and the Pameungpeuk area.

Samples from 13 different sites along the south coast of West Java yield 7 candidate paleo-tsunami sands, which may represent 4 different paleo-tsunami events. Ages obtained from one deposit may document a tsunami and coastal subsidence from an earthquake in 1,053 AD. The tsunami deposit from this event is preserved in an uplifted marine terrace exposed at Panto Cape, Banten Province. We speculated that the terrace has been uplifted about 4.6 m to the present height of 2 m above sea level, since the 1053 AD event at a rate of 4.8 mm/a. This uplift is strong evidence that strain is accumulating at the Java Trench and enough has already accumulated to generate a megathrust earthquake event.Numerical models using ComMIT of possible megathrust earthquake scenarios were constructed using the 2004 Sumatra earthquake, 30-m fault slip, and the 2011 Japan earthquake as proxies. These three scenarios yield earthquakes of Mw 9.3, 9.5 and 8.9, respectively. The worst case scenario is used to estimate the extent of tsunami inundation of the SW coast of Java, which totals 643 km2. The total number of people who inhabit the inundation area is around 451,000. Some coastal configurations cause a no escape situation where the modeled tsunami arrives in less than 20 minutes, which is not enough time for those near the coast to escape far enough inland or to a sufficient elevation to avoid the tsunami. These areas include the coastlines of Sukabumi, Cianjur and west Garut Regencies and the Pameungpeuk area.

<p> A gabbroic intrusion within the Goulburn group of sediments near the west margin of Bathurst trench was studied and mapped using a TV-1 scintillometer. Petrographic examination of the sill was carried out and geochemical whole rock and trace element data were obtained using X.R.F. methods. </p> <p> The 1308 Lake sill was injected conformably between the Western River (argillite/greywacke) and Burnside River (pink quartzite) units of the Goulburn group of sediments. The sill subsequently underwent minor fractional crystallization and differentiation. Generally the sill exhibits poor phase layering, but can be divided into six basic units. </p> 1) Upper Chilled Margin Gabbro 2) Leuco-Micro-Syenite Lens 3) Diabasic Gabbro 4) Pyroxene Granophyre 5) Diabasic Gabbro 6) Basal Sheared Chilled Margin Gabbro These units are evident in this section and are distinguishable both modally and texturally. In most cases, variations in the chemistry and norms reflect the units mapped in the field. Comparisons have been drawn and theories incorporated from other gabbroic intrusions to help explain some features of the 1308 Lake sill. </p> / Thesis / Bachelor of Arts (BA)