In this thesis the design of a MMIC vector modulator operating in 9GHz-10GHz band is investigated and performed. Sub-sections of the vector modulator are 4-port (4.8dB) 1200 phase shift relative to the dedicated port power splitter, digitally controlled variable gain amplifier and the in phase power combiner. Alternative methods are searched in order to implement the structure properly in the given frequency band. The final design is appropriate for MMIC structure. 4-port (4.8dB) 1200 phase shift relative to the dedicated port power splitter is studied. The performance is simulated and optimized first on Microwave Office, then on Advanced Design System (ADS) tools. Various methods to design a digitally controlled variable gain amplifier are studied. The final topology is simulated and optimized on ADS tool. An in phase power combiner is designed. The performance of the combiner is simulated and optimized on ADS tool. Lumped element models are replaced with CASWELL H-40 models to achieve a MMIC structure and a layout is drawn. The finalized vector modulator is simulated and optimized on ADS tool. Key words: MMIC, Vector Modulator, Digitally Controlled Variable Gain Amplifier, Layout

Die vorliegende Arbeit ist der analytischen Untersuchung und Weiterentwicklung von Methoden und Schaltungen zur Einstellung der Signalphase und -amplitude gewidmet. Hierbei wird zum Ziel gesetzt, die Leistungsfähigkeit dieser Schaltungen als analoge Hochfrequenz-Baugruppen in Empfangs- und Sendeschaltkreisen mit einem vergleichbaren oder geringerem schaltungstechnischen Aufwand und Strombedarf zu verbessern und dies anhand von Implementierungsbeispielen zu bestätigen. Die Dämpfungsglied-Topologien , T, überbrücktes T und X werden modelliert und hinsichtlich der Phasenbeeinflussung analysiert, sodass eine Bewertung ihrer Eignung durchgeführt werden kann. Weiterhin wird ein innovativer Ansatz zur Linearisierung der Steuerkennlinie vorgestellt und mit Hilfe einer Beispielschaltung mit einem Phasenfehler von 3 ° und einem Steuerlinearitätsfehler von 0,35 dB innerhalb der 1 dB Grenzfrequenz und einem Steuerbereich von 20 dB nachgewiesen. Die Arbeit bietet darüber hinaus eine analytische Betrachtung zu aktiven steuerbaren Verstärkern, welche die besondere Eignung der Gilbert-Zelle aufzeigt und eine geeignete Ansteuerschaltung ableitet. Am Beispiel nach diesem Prinzip entworfener Schaltkreise werden Phasenfehler von nur 0,4 ° innerhalb eines besonders hohen Stellbereichs von 36 dB demonstriert, wodurch eine Vergrößerung des Stellbereichs um den Faktor 4 und eine Verbesserung des Phasenfehlers um den Faktor 2 im Vergleich zum Stand der Technik erreicht wurde. Es wird der Zirkulator-Phasenschieber maßgeblich durch eine neuartige geeignete Ansteuerung verbessert. Damit werden die sonst für die Amplitudenbeeinflussung im Wesentlichen verantwortlichen Varaktoren überflüssig, ohne dabei den schaltungstechnischen Aufwand zu erhöhen. Eine Messung der entsprechenden Schaltung bestätigt dies mit einem Amplitudenfehler von nur 0,9 dB für einen Phasenstellbereich von 360 °, was einer Verringerung des Fehlers um den Faktor 3 im Vergleich zu herkömmlichen Zirkulator-Phasenschiebern entspricht. Abschließend wird der Funktionsnachweis mehrerer entworfener Vektor-Modulatoren mit einer effektiven Genauigkeit von bis zu 6 bit in Einzelschaltungen, Hybridaufbauten und schließlich im Rahmen eines vollständig integrierten Empfängerschaltkreises erbracht. Dieser erzielt eine Verdopplung der Reichweite bei einer um nur 35% höheren Leistungsaufnahme gegenüber einem herkömmlichen Kommunikationsverfahren (SISO). / The present work is dedicated to the investigation and enhancement of amplitude and phase control methods and circuits. The aim is to enhance the performance of these circuits in modern radio frequency transceivers with a comparable or even lower effort and power consumption. A prove of concept will be delivered with implementation examples. By means of models of the passive attenuator topologies , T, bridged-T and X, a thorough analysis is performed in order to compare them regarding their impact on the signal phase. Additionally, a novel approach to increase the control linearity of the attenuators is proposed and verified by measurements, showing a phase error of 3 ° and a control linearity error of 0,35 dB at the 1 dB corner frequency, successfully. The work also presents an investigation on variable gain amplifiers and reveals the superior performance of the Gilbert cell with respect to low phase variations. A cascode biasing circuit that supports these properties is proposed. Measurements prove this concept with relative phase errors of 0,4 ° over a wide attenuation control range of 36 dB thus cutting the error by half in a four times wider control range. The circulator based phase shifting approach is chosen and improved significantly by means of tuning the transconductor instead of the varactors thus removing their impact on signal amplitude. The approach is supported by measurements yielding an amplitude error of only 0,9 dB within a phase control range of 360 ° which corresponds to an improvement by a factor of three compared to recent circulator phase shifters. Finally, the design of several vector modulator topologies is shown with hardware examples of single chips, hybrid printed circuit boards and highly integrated system level ICs demonstrating a full receiver. By using improved variable gain amplifiers, an effective vector modulator resolution of 6 bit without calibration is achieved. Furthermore, a multiple-input multiple-output system is demonstrated that doubles the coverage range of common SISO systems with only 35% of additional power consumption.

O desenvolvimento de tecnologias de integração para circuitos integrados junto com a demanda de cada vez mais processamento digital de sinais, como em sistemas de telecomunicações e aplicações SOC, resultaram na crescente necessidade de circuitos mistos em tecnologia CMOS integrados em um único chip. Em um trabalho anterior, a arquitetura de uma interface analógica para ser usada em aplicações SOC mistas foi desenvolvida e implementada. Basicamente esta interface é composta por uma célula analógica fixa (fixed analog cell – FAC), que translada o sinal de entrada para uma freqüência de processamento fixa, e por um bloco digital que processa este sinal. Primeiramente, as especificações de sistema foram determinadas considerando o processamento de sinais de três bandas de freqüência diferentes: FM, vídeo e celular, seguido por simulações de alto-nível do sistema da FAC. Então, uma arquitetura heteródina integrada CMOS para o front-end que integrará a FAC, composto por 2 mixers ativos e um amplificador de ganho variável, foi apresentada, enumerando-se e propondo-se soluções para os desafios de projeto e metodologia. Os blocos analógicos/RF, juntamente com o front-end, foram projetados e implementados em tecnologia CMOS IBM 0.18μm, apresentando-se simulações e medidas de um protótipo físico. / The development of IC technologies coupled with the demand for more digital signal processing integrated in a single chip has created an increasing need for design of mixed-signal systems in CMOS technology. Previously, a general analog interface architecture targeted to mixed-signal systems on-chip applications was developed and implemented, which is composed by a fixed analog cell (FAC), that translates the input signal to a processing frequency, and a digital block, that processes the signal. The focus of this thesis is to analyze, design and implement analog/RF building blocks suitable for this system. First, a set of system specifications is developed and verified through system level simulations for the FAC system, aiming the signal processing of three target applications: FM, video and digital cellular frequency bands. Then, a fully CMOS integrated dual-conversion heterodyne front-end architecture with 2 active mixers and a variable-gain amplifier is presented, enumerating and proposing solutions for the design challenges and methodology. The stand-alone building blocks and the front-end system are designed and implemented in IBM 0.18μm CMOS process, presenting simulations and experimental data from an actual physical prototype.

O desenvolvimento de tecnologias de integração para circuitos integrados junto com a demanda de cada vez mais processamento digital de sinais, como em sistemas de telecomunicações e aplicações SOC, resultaram na crescente necessidade de circuitos mistos em tecnologia CMOS integrados em um único chip. Em um trabalho anterior, a arquitetura de uma interface analógica para ser usada em aplicações SOC mistas foi desenvolvida e implementada. Basicamente esta interface é composta por uma célula analógica fixa (fixed analog cell – FAC), que translada o sinal de entrada para uma freqüência de processamento fixa, e por um bloco digital que processa este sinal. Primeiramente, as especificações de sistema foram determinadas considerando o processamento de sinais de três bandas de freqüência diferentes: FM, vídeo e celular, seguido por simulações de alto-nível do sistema da FAC. Então, uma arquitetura heteródina integrada CMOS para o front-end que integrará a FAC, composto por 2 mixers ativos e um amplificador de ganho variável, foi apresentada, enumerando-se e propondo-se soluções para os desafios de projeto e metodologia. Os blocos analógicos/RF, juntamente com o front-end, foram projetados e implementados em tecnologia CMOS IBM 0.18μm, apresentando-se simulações e medidas de um protótipo físico. / The development of IC technologies coupled with the demand for more digital signal processing integrated in a single chip has created an increasing need for design of mixed-signal systems in CMOS technology. Previously, a general analog interface architecture targeted to mixed-signal systems on-chip applications was developed and implemented, which is composed by a fixed analog cell (FAC), that translates the input signal to a processing frequency, and a digital block, that processes the signal. The focus of this thesis is to analyze, design and implement analog/RF building blocks suitable for this system. First, a set of system specifications is developed and verified through system level simulations for the FAC system, aiming the signal processing of three target applications: FM, video and digital cellular frequency bands. Then, a fully CMOS integrated dual-conversion heterodyne front-end architecture with 2 active mixers and a variable-gain amplifier is presented, enumerating and proposing solutions for the design challenges and methodology. The stand-alone building blocks and the front-end system are designed and implemented in IBM 0.18μm CMOS process, presenting simulations and experimental data from an actual physical prototype.

O desenvolvimento de tecnologias de integração para circuitos integrados junto com a demanda de cada vez mais processamento digital de sinais, como em sistemas de telecomunicações e aplicações SOC, resultaram na crescente necessidade de circuitos mistos em tecnologia CMOS integrados em um único chip. Em um trabalho anterior, a arquitetura de uma interface analógica para ser usada em aplicações SOC mistas foi desenvolvida e implementada. Basicamente esta interface é composta por uma célula analógica fixa (fixed analog cell – FAC), que translada o sinal de entrada para uma freqüência de processamento fixa, e por um bloco digital que processa este sinal. Primeiramente, as especificações de sistema foram determinadas considerando o processamento de sinais de três bandas de freqüência diferentes: FM, vídeo e celular, seguido por simulações de alto-nível do sistema da FAC. Então, uma arquitetura heteródina integrada CMOS para o front-end que integrará a FAC, composto por 2 mixers ativos e um amplificador de ganho variável, foi apresentada, enumerando-se e propondo-se soluções para os desafios de projeto e metodologia. Os blocos analógicos/RF, juntamente com o front-end, foram projetados e implementados em tecnologia CMOS IBM 0.18μm, apresentando-se simulações e medidas de um protótipo físico. / The development of IC technologies coupled with the demand for more digital signal processing integrated in a single chip has created an increasing need for design of mixed-signal systems in CMOS technology. Previously, a general analog interface architecture targeted to mixed-signal systems on-chip applications was developed and implemented, which is composed by a fixed analog cell (FAC), that translates the input signal to a processing frequency, and a digital block, that processes the signal. The focus of this thesis is to analyze, design and implement analog/RF building blocks suitable for this system. First, a set of system specifications is developed and verified through system level simulations for the FAC system, aiming the signal processing of three target applications: FM, video and digital cellular frequency bands. Then, a fully CMOS integrated dual-conversion heterodyne front-end architecture with 2 active mixers and a variable-gain amplifier is presented, enumerating and proposing solutions for the design challenges and methodology. The stand-alone building blocks and the front-end system are designed and implemented in IBM 0.18μm CMOS process, presenting simulations and experimental data from an actual physical prototype.

Thesis discusses the possibility of using MEMS microphones in measuring systems. Describes the characteristics of MEMS components and shows possible realization of analog to digital signal convertor when a microphone with analog output is used. Design of the amplifier is made with respect to low noise and low power consumption. Also is shown the possibility of using antialliasing filter as microphone frequency response correction at the same time.

Designing CMOS linear transmitter front-end, specially the power amplifiers (PAs), in multi-band wireless transceivers is a major challenge for the single-chip integration of a CMOS radio. In some of the linear PA systems, for example, polar- or predistortion-PA system, amplitude and phase control circuits are used to suppress the distortion produces by the PA core. The requirements of these controlling circuits are much different from their conventional role in a receiver or a phase array system. In this dissertation, the special design issues will be addressed, and the circuit topologies of the amplitude and phase controllers will be proposed. In attempt to control the high-power input signal of a PA system, a highly linear variable attenuator with adaptive body biasing is first introduced. The voltage swing on the signal path is intentionally coupled to the body terminal of the triple-well NMOS devices to reduce their impedance variation. The fabricated variable attenuator shows a significant improvement on linearity as compared to previous CMOS works. The results of this research are then used to build a variable gain amplifier for linear PA systems that requires gain of its amplitude tuning circuits. Different from the conventional attenuator-based VGAs, the high linearity of the suggested attenuator allows it to be put after the gain stage in the presented VGA topology. This arrangement along with the current boosting technique gives the VGA a better noise performance while having a linear-in-dB tuning curve and better worst-case linearity. The following part of the dissertation is about a compact, linear-in-degree tuned variable phase shifter as the phase controller in the PA system. This design uses a modified RC poly-phase filter to produce a set of an orthogonal phase vectors with smaller loss. A specially designed control circuit combines these vectors and generates an output signal with different phases, while having very small gain mismatches at different phase setting. The proposed amplitude and phase control circuits are then verified with a system level analysis. The results show that the proposed designs successfully reduce the non-linear effect of a wireless transmitter.

An electrostatic actuator driven by conventional voltage control and charge control requires high actuation voltage and suffers from the pull-in phenomenon that limits its operation range, much less than its entire gap. To provide effective solutions to these problems, we present complete analytical and numerical models of various electrostatic actuators coupled with resonant drive circuits that are able to drive electrostatic actuators at much lower input voltage than that of conventional actuation methods and to extend their operation range beyond their conventional pull-in points in the presence of high parasitic capacitance. Moreover, in order to validate the analytical and numerical models of various electrostatic actuators coupled with the resonant drive circuits, we perform the experiment on the microplate and the micromirror coupled with the resonant drive circuit. For instance, using a high voltage amplifier, we manage to rotate the micromirror with sidewall electrodes by 6 ° at 180 V. However, using the resonant drive circuit, we are able to rotate the same micromirror by 6 ° at much lower input voltage, 8.5 V. In addition, the presented work also facilitates the stability analysis of electrostatic actuators coupled with the resonant drive circuits and provides how the effect of the parasitic capacitance can be minimized. For example, the resonant drive circuit placed within a positive feedback loop of a variable gain amplifier is able to extend the operation range much further even in the presence of very high parasitic capacitance. The resonant drive circuit with the proposed feedback controllers is also able to minimize the detrimental effects of the parasitic capacitance and to displace a parallel-plate actuator over its entire gap without the saddle-node bifurcation. Finally, we present a new displacement measurement method of electrostatic actuators coupled with the resonant drive circuits by sensing the phase delay of an actuation voltage with respect to an input voltage. This new measurement method allows us to easily implement feedback control into existent systems employing an electrostatic actuator without any modification or alteration to the electrostatic actuator itself. Hence, this research work presents the feasibility of electrostatic actuators coupled with the resonant drive circuit in various industrial and medical applications, in which the advantages of miniaturization, low supply voltage, and low power consumption are greatly appreciated.

Emerging technologies such as Bluetooth and 802.11b (Wi-Fi) have fuelled the growth of the short-range communication industry. Bluetooth, the leading WPAN (wireless personal area network) technology, was designed primarily for cable replacement applications. The first generation Bluetooth products are focused on providing low-cost radio connections among personal electronic devices. In the WLAN (wireless local area network) arena, Wi-Fi appears to be the superior product. Wi-Fi is designed for high speed internet access, with higher radio power and longer distances. Both technologies use the same 2.4GHz ISM band. The differences between Bluetooth and Wi-Fi standard features lead to a natural partitioning of applications. Nowadays, many electronics devices such as laptops and PDAs, support both Bluetooth and Wi-Fi standards to cover a wider range of applications. The cost of supporting both standards, however, is a major concern. Therefore, a dual-mode transceiver is essential to keep the size and cost of such system transceivers at a minimum. A fully integrated low-IF Bluetooth receiver is designed and implemented in a low cost, main stream 0.35um CMOS technology. The system includes the RF front end, frequency synthesizer and baseband blocks. It has -82dBm sensitivity and draws 65mA current. This project involved 6 Ph.D. students and I was in charge of the design of the channel selection complex filter is designed. In the Bluetooth transmitter, a frequency modulator with fine frequency steps is needed to generate the GFSK signal that has +/-160kHz frequency deviation. A low power ROM-less direct digital frequency synthesizer (DDFS) is designed to implement the frequency modulation. The DDFS can be used for any frequency or phase modulation communication systems that require fast frequency switching with fine frequency steps. Another contribution is the implementation of a dual-mode 802.11b/Bluetooth receiver in IBM 0.25um BiCMOS process. Direct-conversion architecture was used for both standards to achieve maximum level of integration and block sharing. I was honored to lead the efforts of 7 Ph.D. students in this project. I was responsible for system level design as well as the design of the variable gain amplifier. The receiver chip consumes 45.6/41.3mA and the sensitivity is -86/-91dBm.

An electrostatic actuator driven by conventional voltage control and charge control requires high actuation voltage and suffers from the pull-in phenomenon that limits its operation range, much less than its entire gap. To provide effective solutions to these problems, we present complete analytical and numerical models of various electrostatic actuators coupled with resonant drive circuits that are able to drive electrostatic actuators at much lower input voltage than that of conventional actuation methods and to extend their operation range beyond their conventional pull-in points in the presence of high parasitic capacitance. Moreover, in order to validate the analytical and numerical models of various electrostatic actuators coupled with the resonant drive circuits, we perform the experiment on the microplate and the micromirror coupled with the resonant drive circuit. For instance, using a high voltage amplifier, we manage to rotate the micromirror with sidewall electrodes by 6 ° at 180 V. However, using the resonant drive circuit, we are able to rotate the same micromirror by 6 ° at much lower input voltage, 8.5 V. In addition, the presented work also facilitates the stability analysis of electrostatic actuators coupled with the resonant drive circuits and provides how the effect of the parasitic capacitance can be minimized. For example, the resonant drive circuit placed within a positive feedback loop of a variable gain amplifier is able to extend the operation range much further even in the presence of very high parasitic capacitance. The resonant drive circuit with the proposed feedback controllers is also able to minimize the detrimental effects of the parasitic capacitance and to displace a parallel-plate actuator over its entire gap without the saddle-node bifurcation. Finally, we present a new displacement measurement method of electrostatic actuators coupled with the resonant drive circuits by sensing the phase delay of an actuation voltage with respect to an input voltage. This new measurement method allows us to easily implement feedback control into existent systems employing an electrostatic actuator without any modification or alteration to the electrostatic actuator itself. Hence, this research work presents the feasibility of electrostatic actuators coupled with the resonant drive circuit in various industrial and medical applications, in which the advantages of miniaturization, low supply voltage, and low power consumption are greatly appreciated.