Die vorliegende Arbeit ist der analytischen Untersuchung und Weiterentwicklung von Methoden und Schaltungen zur Einstellung der Signalphase und -amplitude gewidmet. Hierbei wird zum Ziel gesetzt, die Leistungsfähigkeit dieser Schaltungen als analoge Hochfrequenz-Baugruppen in Empfangs- und Sendeschaltkreisen mit einem vergleichbaren oder geringerem schaltungstechnischen Aufwand und Strombedarf zu verbessern und dies anhand von Implementierungsbeispielen zu bestätigen. Die Dämpfungsglied-Topologien , T, überbrücktes T und X werden modelliert und hinsichtlich der Phasenbeeinflussung analysiert, sodass eine Bewertung ihrer Eignung durchgeführt werden kann. Weiterhin wird ein innovativer Ansatz zur Linearisierung der Steuerkennlinie vorgestellt und mit Hilfe einer Beispielschaltung mit einem Phasenfehler von 3 ° und einem Steuerlinearitätsfehler von 0,35 dB innerhalb der 1 dB Grenzfrequenz und einem Steuerbereich von 20 dB nachgewiesen. Die Arbeit bietet darüber hinaus eine analytische Betrachtung zu aktiven steuerbaren Verstärkern, welche die besondere Eignung der Gilbert-Zelle aufzeigt und eine geeignete Ansteuerschaltung ableitet. Am Beispiel nach diesem Prinzip entworfener Schaltkreise werden Phasenfehler von nur 0,4 ° innerhalb eines besonders hohen Stellbereichs von 36 dB demonstriert, wodurch eine Vergrößerung des Stellbereichs um den Faktor 4 und eine Verbesserung des Phasenfehlers um den Faktor 2 im Vergleich zum Stand der Technik erreicht wurde. Es wird der Zirkulator-Phasenschieber maßgeblich durch eine neuartige geeignete Ansteuerung verbessert. Damit werden die sonst für die Amplitudenbeeinflussung im Wesentlichen verantwortlichen Varaktoren überflüssig, ohne dabei den schaltungstechnischen Aufwand zu erhöhen. Eine Messung der entsprechenden Schaltung bestätigt dies mit einem Amplitudenfehler von nur 0,9 dB für einen Phasenstellbereich von 360 °, was einer Verringerung des Fehlers um den Faktor 3 im Vergleich zu herkömmlichen Zirkulator-Phasenschiebern entspricht. Abschließend wird der Funktionsnachweis mehrerer entworfener Vektor-Modulatoren mit einer effektiven Genauigkeit von bis zu 6 bit in Einzelschaltungen, Hybridaufbauten und schließlich im Rahmen eines vollständig integrierten Empfängerschaltkreises erbracht. Dieser erzielt eine Verdopplung der Reichweite bei einer um nur 35% höheren Leistungsaufnahme gegenüber einem herkömmlichen Kommunikationsverfahren (SISO). / The present work is dedicated to the investigation and enhancement of amplitude and phase control methods and circuits. The aim is to enhance the performance of these circuits in modern radio frequency transceivers with a comparable or even lower effort and power consumption. A prove of concept will be delivered with implementation examples. By means of models of the passive attenuator topologies , T, bridged-T and X, a thorough analysis is performed in order to compare them regarding their impact on the signal phase. Additionally, a novel approach to increase the control linearity of the attenuators is proposed and verified by measurements, showing a phase error of 3 ° and a control linearity error of 0,35 dB at the 1 dB corner frequency, successfully. The work also presents an investigation on variable gain amplifiers and reveals the superior performance of the Gilbert cell with respect to low phase variations. A cascode biasing circuit that supports these properties is proposed. Measurements prove this concept with relative phase errors of 0,4 ° over a wide attenuation control range of 36 dB thus cutting the error by half in a four times wider control range. The circulator based phase shifting approach is chosen and improved significantly by means of tuning the transconductor instead of the varactors thus removing their impact on signal amplitude. The approach is supported by measurements yielding an amplitude error of only 0,9 dB within a phase control range of 360 ° which corresponds to an improvement by a factor of three compared to recent circulator phase shifters. Finally, the design of several vector modulator topologies is shown with hardware examples of single chips, hybrid printed circuit boards and highly integrated system level ICs demonstrating a full receiver. By using improved variable gain amplifiers, an effective vector modulator resolution of 6 bit without calibration is achieved. Furthermore, a multiple-input multiple-output system is demonstrated that doubles the coverage range of common SISO systems with only 35% of additional power consumption.

No description available.

This thesis presents the design, layout, and measurements of a bi-directional amplifier with variable vector (in-phase / quadrature) gain control that will be part of an electronically steered phased array system. The electronically steered phased array has many advantages over the conventional mechanically steered antennas including rapid scanning of the beam and adaptively creating nulls in desired locations. The 10-bit bi-directional Vector Variable Gain Amplifier (VVGA) is part of the transmit and receive module of each antenna element where transmit and receive functionality is determined through a simple switch. The VVGA performs amplification of the IF IQ pair by an adjustable complex coefficient. At receive, the VVGA functions as a Vector Variable Gain Current Amplifier (VVGCA) and at transmit, the VVGA functions as a Vector Variable Gain Transadmittance Amplifier (VVGTA). Design procedure, layout entry, schematic and parasitic extracted simulation results, and measurements are presented in this thesis.

Τα τελευταία χρόνια η ανάγκη για αναλογικά ολοκληρωμένα κυκλώματα με χαμηλή τάση τροφοδοσίας και χαμηλή ισχύ γίνεται κάτι περισσότερο από επιτακτική. Ο βασικότερος λόγος για την ανάγκη αυτή είναι η ραγδαία ανάπτυξη από φορητές ηλεκτρονικές συσκευές για εφαρμογές πολυμέσων (laptops, netbooks, mobiles) έως ολοκληρωμένων συστημάτων βιοιατρικών εφαρμογών. Μάλιστα σε πολλές περιπτώσεις απαιτείται αυτές οι ηλεκτρονικές συσκευές να έχουν δυνατότητα διασύνδεσης σε ασύρματα δίκτυα (WLANs) και επομένως επιβάλλεται η ενσωμάτωση συστημάτων πομποδεκτών. Έτσι, οι απαιτήσεις για όσο το δυνατόν μικρότερη κατανάλωση και επομένως χαμηλότερη τροφοδοσία είναι επιβεβλημένες. Ένα από τα βασικότερα «δομικά» κυκλώματα σχεδίασης αναλογικών κυκλωμάτων είναι οι διαφορικοί ενισχυτές τάσης. Στην παρούσα διατριβή παρουσιάζονται πλήρεις λύσεις διαφορικών ενισχυτών χαμηλής τάσης τροφοδοσίας σε τυπική CMOS τεχνολογία των 0.35μm και 0.18μm. Οι προτεινόμενοι ενισχυτές σχεδιάστηκαν με την τεχνική οδήγησης τρανζίστορ από το υπόστρωμα (Bulk-driven technique). Αρχικά σχεδιάστηκαν διαφορικοί ενισχυτές τάσεις με τοπολογία αρνητικής αντίστασης στην βαθμίδα εισόδου. Με τον τρόπο αυτό έγινε αύξηση της μικρής διαγωγιμότητας εισόδου που παρουσιάζει η τεχνική οδήγησης τρανζίστορ από το υπόστρωμα. Έτσι, προέκυψαν πρωτότυπες δομές ενισχυτών με χαμηλή τροφοδοσία μέχρι και 0.8V. Οι επιδόσεις των ενισχυτών χαρακτηρίστηκαν από κατάλληλες προσομοιώσεις αλλά και από πειραματικές μετρήσεις καθώς κατασκευάστηκε ολοκληρωμένο κύκλωμα ενισχυτή. Η σύγκλιση των αποτελεσμάτων των προσομοιώσεων με των πειραματικών απέδειξε πως τόσο τα προτεινόμενα κυκλώματα όσο και η ίδια η τεχνική σχεδίασης αποτελούν σημαντική λύση όπου απαιτούνται διαφορικοί ενισχυτές τάσης χαμηλής τροφοδοσίας. Στη συνέχεια σχεδιάστηκε βαθμίδα διαφορικού ακόλουθου τάσης με την τεχνική οδήγησης τρανζίστορ από το υπόστρωμα και τροφοδοσία 1V. Η βαθμίδα αυτή χρησιμοποιήθηκε ως διαφορική βαθμίδα εισόδου διαφορικού ενισχυτή τάσης με τροφοδοσία 1V. Ο ενισχυτής αυτός λειτουργεί για μεταβολή του κοινού σήματος εισόδου μεταξύ των άκρων της τροφοδοσίας. Ο ακόλουθος τάσης τροποποιήθηκε κατάλληλα ώστε να λειτουργεί με τροφοδοσία 0.5V και χρησιμοποιήθηκε ως διαφορική βαθμίδα εισόδου σε διαφορικό ενισχυτή τάσης ίδιας τροφοδοσίας. Και οι δυο προτεινόμενες τοπολογίες ενισχυτών αποτελούν πλήρεις λύσεις για εφαρμογές ενισχυτών τάσης με χαμηλή και πολύ χαμηλή τροφοδοσία αντίστοιχα. Τέλος με την τεχνική οδήγησης τρανζίστορ από το υπόστρωμα σχεδιάστηκε ενισχυτής μεταβλητού κέρδους. Για το σκοπό αυτό αναπτύχθηκε τεχνική γραμμικής μεταβολής διαγωγιμότητας διαγωγών. Ο ενισχυτής μεταβλητού κέρδους που σχεδιάστηκε λειτουργεί με τροφοδοσία 0.8V ενώ το κέρδος έχει εύρος μεταβολής 17dB και μπορεί να ενσωματωθεί σε βρόχο αυτομάτου ελέγχου κέρδους χαμηλής τροφοδοσίας. Για το σκοπό αυτό σχεδιάστηκαν με την τεχνική οδήγησης τρανζίστορ από το υπόστρωμα και δυο κυκλώματα τετραγωνικής συνάρτησης με τροφοδοσία 0.8V και 0.5V αντίστοιχα. / In recent years the need for analog integrated circuits with low-voltage and low-power is more than urgent. The main reason for this need is the rapid growth of portable electronic devices for multimedia applications (laptops, netbooks, mobiles, etc.) and even more for biomedical devices applications. In many cases, these electronic devices provide connectivity to wireless networks (WLANs) and therefore they incorporate transceiver systems. Thus, requirements such as low-voltage and low-power are a necessity. One of the basic analog “building blocks” for circuit design is differential voltage amplifiers. This thesis presents complete solutions for low-voltage differential amplifiers in standard CMOS technology of 0.35μm and 0.18μm. The proposed amplifiers were designed with bulk-driven technique. In the first place are designed differential voltage amplifiers that include input stage with negative resistance circuitry. This way the proposed amplifiers improve the small input transconductance due to bulk-driven transistors. Thus, novel amplifier structures are obtained with a voltage supply equal even to 0.8V. The amplifiers performance is characterized both through simulation and experimental results. The convergence of simulation and experimental results demonstrate that the proposed amplifiers circuits designed with bulk-driven technique are significant solution in the design of low-voltage amplifiers. In the next step a differential bulk-driven voltage follower is designed with 1V voltage supply. The proposed follower is used as a differential input stage for a differential voltage amplifier with the same voltage supply. The proposed amplifier is capable to operate rail-to-rail for common mode input signals. Also, the proposed voltage follower is modified in order to operate in extreme voltage supply of 0.5V. The modified voltage follower is used, again, as a differential input stage for a differential voltage amplifier while the whole amplifier used a voltage supply equal to 0.5V. Both proposed amplifiers topologies that use bulk-driven differential voltage followers as input stages are complete solutions for low-voltage and ultra low-voltage amplifiers applications. Finally, a new technique for linear transconductance variation, applicable in any kind of transconductor, is introduced. The proposed technique is used to build a bulk-driven variable gain amplifier (VGA). The proposed VGA operate with 0.8V voltage supply while produce a gain range variation equal to 17dB. The amplifier could incorporate in an automatic gain control loop (AGC) for low-voltage applications. For this purpose, two bulk-driven voltage squarers circuits with voltage supply 0.8V and 0.5V was also proposed.

Ce travail de thèse concerne les circuits ultra-rapides pour la conversion analogique numérique performante en technologie bipolaire à hétérojonctions sur substrat Indium Phosphore (TBDH/InP). L'étude s'intéresse à la fonction principale qui est l'échantillonnage blocage. Elle a été menée par simulation de l'ensemble des blocs composant cette fonction. En particulier une étude extensive des cœurs des circuits Echantillonneurs/Bloqueurs a été effectuée pour différents paramètres électriques pour aboutir à des valeurs optimales réalisant un compromis entre la bande passante la résolution et la linéarité.Des architectures de circuits Echantillonneurs/Bloqueurs (E/B) avec ou sans l'étage d'amplification à gain variable ont été conçues, optimisées, réalisées et caractérisées et des performances à l'état de l'art ont été obtenues : des circuits E/B de bande passante supérieure à 50 GHz et cadencées à 70 Gs/s ont été réalisés pour les applications de communications optiques et des circuits de bande passante supérieure à 16 GHz cadencés à (2-8) Gs/s ont été réalisés pour la transposition de fréquence. / This thesis concerns the design of high speed circuits in Indium phosphide heterojunction Bipolar technology for High performance analog to digital conversion (ADC).The study focuses on the Track and Hold block (THA) which is the main function of the ADC. The study was conducted by simulating all blocks of the THA circuit. In particular, an extensive study of the THA main block was performed for various electrical parameters to achieve optimal conditions in order to obtain a good tradeoff between resolution bandwidth and linearity. THA architectures circuits with or without Voltage Gain Amplifier stage were designed, optimized and characterized. High THA performances were achieved: THA circuit with a bandwidth greater than 50 GHz at 70 Gs/s were achieved for optical communications and circuits of bandwidth more than16 GHz at (2-8 GS /s) have been realized for down conversion operation.

L’évolution des systèmes de télécommunications, liée à une demande sans cesse croissante en termes de débit et de volume de données, se concrétise par le développement de systèmes proposant des bandes passantes très larges, des modulations à très hautes efficacités spectrales, de la flexibilité en puissance et en fréquence d’émission. Par ailleurs, la mise en œuvre de ces dispositifs doit se faire avec un souci permanent d’économie d’énergie d’où la problématique récurrente de l’amplification de puissance RF qui consiste à allier au mieux rendement, linéarité et bande passante. L’architecture conventionnelle d’une chaine d’émission RF consiste dans une première étape à réaliser l’opération de modulation-conversion de fréquence (Modulateur IQ) puis dans une deuxième étape l’opération de conversion d’énergie DC-RF (Amplificateur de Puissance), ces deux étapes étant traditionnellement traitées de manière indépendante. L’objectif de ces travaux de thèse est de proposer une approche alternative qui consiste à combiner ces deux opérations dans une seule et même fonction : le modulateur vectoriel de puissance à haute efficacité énergétique. Le cœur du dispositif, conçu en technologie GaN, repose sur un circuit à deux étages de transistors HEMT permettant d’obtenir un gain en puissance variable en régime de saturation. Il est associé à un modulateur de polarisation multi-niveaux spécifique également en technologie GaN. Le dispositif réalisé a permis de générer directement, à une fréquence de 2.5 GHz, une modulation vectorielle 16QAM (100Msymb/s) de puissance moyenne 13 W, de puissance crête 25W avec un rendement global de 40% et une linéarité mesurée par un EVM à 5%. / The evolution of telecommunications systems, linked to a constantly increasing demand in terms of data rate and volume, leads to the development of systems offering very wide bandwidths, modulations with very high spectral efficiencies, increased power and frequency flexibilities in transmitters. Moreover, the implementation of such systems must be done with a permanent concern for energy saving, hence the recurring goal of the RF power amplification which is to combine the best efficiency, linearity and bandwidth. Conventional architectures of RF emitter front-ends consist in a first step in performing the frequency modulation-conversion operation (IQ Modulator) and then in a second step the DC-RF energy conversion operation (Power Amplifier), these two steps being usually managed independently. The aim of this thesis is to propose an alternative approach that consists in combining these two operations in only one function: a high efficiency vector power modulator. The core of the proposed system is based on a two-stage GaN HEMT circuit to obtain a variable power gain operating at saturation. It is associated with a specific multi-level bias modulator also design using GaN technology. The fabricated device generates, at a frequency of 2.5 GHz, a 16QAM modulation (100Msymb/s) with 13W average power, 25W peak power, with an overall efficiency of 40% and 5% EVM.

With the explosive development of wireless communication systems the specifications of the supporting hardware platforms have become more and more demanding. According to the long term goals of the industry, future communications systems should integrate a wide variety of standards. This leads to the idea of software defined radio, implemented on fully reconfigurable hardware.Among other reconfigurable hardware blocks, suitable for the software radio concept, an outstanding importance belongs to the reconfigurable filters that are responsible for the selectivity of the system. The problematic of filtering is strictly connected to the architecture chosen for a multi-mode receiver realization. According to the chosen architecture, the filters can exhibit low pass or band pass frequency responses.The idea of reconfigurable frequency parameters has been introduced since the beginning of modern filtering applications due to the required precision of the frequency response. However, the reconfiguration of the parameters was usually done in a limited range around ideal values. The purpose of the presented research is to transform the classical filter structures with simple self-correction into fully reconfigurable filters over a wide range of frequencies. The ideal variation of the frequency parameters is continuous and consequently difficult to implement in real circuits. Therefore, it is usually sufficient to use a discrete programming template with reasonably small steps.There are several methods to implement variable frequency parameters. The most often used programming templates employ resistor and capacitor arrays, switched according to a given code. The low pass filter implementation proposed in this work uses a special switching template, optimized for a quasi-linear frequency variation over logarithmic axes. The template also includes the possibility to compensate errors caused by component tolerances and temperature. Another important topic concerns the implementation of programmable band pass filters, suitable for IF sampling receivers. The discussion is centered on the feasibility and the flexibility of different band pass filter architectures. Due to the high frequency requirements, the emphasis lays on filters that employ transconductance amplifiers and capacitors. / Die rasch fortschreitende Entwicklung drahtloser Kommunikationssysteme führt zu immer anspruchsvolleren Spezifikationen der diese Systeme unterstützenden Hardwareplattformen. Zukünftige Kommunikationssysteme sollen übereinstimmend mit den längerfristigen Zielen der Industrie verschiedene Standards integrieren. Dies führt zu der Idee von vollständig rekonfigurierbarer Hardware, welche mittels Software gesteuert wird.Inmitten anderer rekonfigurierbarer Hardwareblöcke, die für das Software Radio Konzept geeignet sind, besitzen die steuerbaren Filter, welche wesentlichen Einfluss auf die Selektivität des Systems haben, eine enorme Bedeutung. Die Filterproblematik ist eng mit der gewählten Architektur der standardübergreifenden Empfängerrealisierung verknüpft. Die Filter können entsprechend der ausgesuchten Architektur Tiefpass- oder Bandpasscharakter annehmen.Die Idee rekonfigurierbarer Frequenzparameter wurde bereits mit Beginn moderner Filteranwendungen auf Grund geforderter Frequenzganggenauigkeit umgesetzt. Jedoch wurde die Parameterrekonfiguration üblicherweise nur in einem begrenzten Bereich um die Idealwerte herum vorgenommen. Das Ziel der vorgestellten Forschungsarbeit ist es, diese klassischen Filterstrukturen mit einfacher Selbstkorrektur in über große Frequenzbereiche voll rekonfigurierbare Filter zu transformieren. Idealerweise werden die Frequenzparameter kontinuierlich variiert weswegen sich die Implementierung in reellen Schaltkreisen als schwierig erweist. Deshalb ist es üblicherweise ausreichend, ein diskretes Steuerschema mit kleinen Schrittweiten zu verwenden.Es gibt verschiedene Methoden, variable Frequenzparameter zu implementieren. Die meisten Schemata verwenden Widerstands- und Kondensatorfelder, die entsprechend eines Kodes geschaltet werden. Die in dieser Arbeit vorgestellte Implementierung eines Tiefpassfilters nutzt ein spezielles Umschaltschema, welches für die quasi-lineare Frequenzvariation bei Darstellung über logarithmischen Axen optimiert wurde. Es beinhaltet weiterhin die Möglichkeit, Fehler zu kompensieren, die durch Bauelementtoleranzen und Temperaturschwankungen hervorgerufen werden.Ein weiteres interessantes Thema betrifft die Implementierung steuerbarer Bandpassfilter, die für Empfänger mit Zwischenfrequenzabtastung geeignet sind. Die Betrachtung beschränkt sich hierbei auf die Durchführbarkeit und Flexibilität verschiedener Bandpassfilterarchitekturen. Auf Grund hoher Frequenzanforderungen liegt der Schwerpunkt auf Filtern, die auf Transkonduktanzverstärkern und Kondensatoren basieren.

LOW power operation for wireless radio receivers has been gaining importance lately on account of the recent spurt of growth in the usage of ubiquitous embedded mobile devices. These devices are becoming relevant in all domains of human influence. In most cases battery life for these devices continue to be an us-age bottleneck as energy storage techniques have not kept pace with the growing demand of such mobile computing devices. Many applications of these radios have limitations on recharge cycle, i.e. the radio needs to last out of a battery for long duration. This will specially be true for sensor network applications and for im-plantable medical devices. The search for low power wireless receivers has become quite advanced with a plethora of techniques, ranging from circuit to architecture to system level approaches being formulated as part of standard design procedures. However the next level of optimization towards “Smart” receiver systems has been gaining credence and may prove to be the next challenge in receiver design and de-velopment. We aim to proceed further on this journey by proposing Power Scalable Wireless Receivers (PSRX) which have the capability to respond to instantaneous performance requirements to lower power even further. Traditionally low power receivers were designed for worst-case input conditions, namely low signal and high interference, leading to large dynamic range of operation which directly im-pacts the power consumption. We propose to take into account the variation in performance required out of the receiver, under varying Signal and Interference conditions, to trade-off power. We have analyzed, designed and implemented a Power Scalable Receiver tar-geted towards low data-rate receivers which can work for Zigbee or Bluetooth Low Energy (BLE) type standards. Each block of such a receiver system was evaluated for performance-power trade-offs leading to identification of tuning/control knobs at the circuit architecture level of the receiver blocks. Then we developed an usage algorithm for finding power optimal operational settings for the tuning knobs, while guaranteeing receiver reception performance in terms of Bit-Error-Rate (BER). We have proposed and demonstrated a novel signal measurement system to gen-erate digitized estimates of signal and interference strength in the received signal, called Received Signal Quality Indicator (RSQI). We achieve a RSQI average energy consumption of 8.1nJ with a peak energy consumption of 9.4nJ which is quite low compared to the packet reception energy consumption for low power receivers, and will be substantially lower than the energy savings which will be achieved from a power scalable receiver employing a RSQI. The full PSRX system was fabricated in UMC 130nm RF-CMOS process to test out our concepts and to formally quantify the power savings achieved by following the design methodology. The test chip occupied an area of 2.7mm2 with a peak power consumption of 5.5mW for the receiver chain and 18mW for the complete PSRX. We were able to meet the receiver performance requirements for Zigbee standard and achieved about 5X power savings for the range of input condition variations.

This research looks into the design of an integrated in-phase/quadrature (I/Q) VCO operating at 5 GHz. The goal is to design a phase shifter that is implemented at the LO used for RF up conversion. The target application for the phase shifter is towards phased array antennas operating at 5 GHz. Instead of designing multiple VCOs that each deliver a variety of phases, two identical LC-VCOs are coupled together to oscillate at the same frequency and deliver four outputs that are 90 ° out of phase. By varying the amplitudes of the in-phase and quadrature signals independently using VGAs before adding them together, a resultant out-of-phase signal is obtained. A number of independently variable out-of-phase signals can be obtained from these 90 ° out-of-phase signals and this technique is better known as the vector sum method of phase shifting. Control signals to the inputs of the VGAs required to obtain 22.5 ° phase shifts were designed from simulations and are generated using 16-bit DACs. The design is implemented and manufactured using a 0.35 µm SiGe BiCMOS process and the complete prototype IC occupies an area of 2.65 × 2.65 mm2. The I/Q VCO with 360 ° variable phase outputs occupies 1.10 × 0.85 mm2 of chip area and the 16-bit DAC along with its decoding circuitry occupies 0.41 × 0.13 mm2 of chip area. The manufactured quadrature VCO was found to oscillate between 4.12 ~ 4.74 GHz and consumes 23.1 mW from a 3.3 V supply without its buffer circuitry. A maximum phase noise of -78.5 dBc / Hz at a 100 kHz offset and -108.17 dBc / Hz at a 1 MHz offset was measured and the minimum VCO figure of merit is 157.8 dBc / Hz. The output voltages of the 16 bit DAC are within 3.5 % of the design specifications. When the phase shifter is controlled by the 16 DAC signals, the maximum measured phase error of the phase shifter is lower than 10 %. / Dissertation (MEng)--University of Pretoria, 2009. / Electrical, Electronic and Computer Engineering / unrestricted

Les systèmes de communication mobiles permettent l’utilisation de l’information en environnements complexes grâce à des dispositifs portables qui ont comme principale restriction la durée de leurs batteries. Des nombreux efforts se sont focalisés sur la réduction de la consommation d’énergie des circuits électroniques de ces systèmes, une fois que le développent des technologies des batteries ne avance pas au rythme nécessaire. En outre, les systèmes RF sont généralement conçus pour fonctionner de manière fixe, spécifiés pour le pire cas du lien de communication. Toutefois, ce scénario peut se produire dans une petite partie du temps, entraînant ainsi en perte d’énergie dans le reste du temps. La recherche des circuits RF adaptatifs, pour adapter le niveau du signal d'entrée pour réduire la consommation d'énergie est donc d'un grand intérêt et de l'importance. Dans la chaîne de réception radiofréquence, l'amplificateur à faible bruit (LNA) se montre un composant essentiel, autant pour les performances de la chaîne que pour la consommation d'énergie. Au cours des dernières décennies, des techniques pour la conception de LNAs reconfigurables ont été proposées et mises en oeuvre. Cependant, la plupart d'entre elles s’applique seulement au contrôle du gain, sans exploiter Le réglage de la linéarité et du bruit envisageant l'économie d'énergie. De plus,ces circuits occupent une grande surface de silicium, ce qui entraîne un coût élevé, ou NE correspondent pas aux nouvelles technologies CMOS à faible coût. L'objectif de cette étude est de démontrer la faisabilité et les avantages de l'utilisation d'un LNA reconfigurable numériquement dans une chaîne de réception radiofréquence, du point de vue de la consommation d'énergie et de coût de fabrication. / Mobile communication systems allow exploring information in complex environments by means of portable devices, whose main restriction is battery life. Once battery development does not follow market expectations, several efforts have been made in order to reduce energy consumption of those systems. Furthermore, radio-frequency systems are generally designed to operate as fixed circuits, specified for RF link worst-case scenario. However, this scenario may occur in a small amount of time, leading to energy waste in the remaining periods. The research of adaptive radio-frequency circuits and systems, which can configure themselves in response to input signal level in order to reduce power consumption, is of interest and importance. In a RF receiver chain, Low Noise Amplifier (LNA) stand as critical elements, both on the chain performance or power consumption. In the past some techniques for reconfigurable LNA design were proposed and applied. Nevertheless, the majority of them are applied to gain control, ignoring the possibility of linearity and noise figure adjustment, in order to save power. In addition, those circuits consume great area, resulting in high production costs, or they do not scale well with CMOS. The goal of this work is demonstrate the feasibility and advantages in using a digitally controlled LNA in a receiver chain in order to save area and power. / Os sistemas de comunicação móveis permitem a exploração da informação em ambientes complexos através dos dispositivos portáteis que possuem como principal restrição a duração de suas baterias. Como o desenvolvimento da tecnologia de baterias não ocorre na velocidade esperada pelo mercado, muitos esforços se voltam à redução do consumo de energia dos circuitos eletrônicos destes sistemas. Além disso, os sistemas de radiofrequência são em geral projetados para funcionarem de forma fixa, especificados para o cenário de pior caso do link de comunicação. No entanto, este cenário pode ocorrer em uma pequena porção de tempo, resultando assim no restante do tempo em desperdício de energia. A investigação de sistemas e circuitos de radiofrequência adaptativos, que se ajustem ao nível de sinal de entrada a fim de reduzir o consumo de energia é assim de grande interesse e importância. Dentro de cadeia de recepção de radiofrequência, os Amplificadores de Baixo Ruído (LNA) se destacam como elementos críticos, tanto para o desempenho da cadeia como para o consumo de potência. No passado algumas técnicas para o projeto de LNA reconfiguráveis foram propostas e aplicadas. Contudo, a maioria delas só se aplica ao controle do ganho, deixando de explorar o ajuste da linearidade e da figura de ruído com fins de economia de energia. Além disso, estes circuitos ocupam grande área de silício, resultando em alto custo, ou então não se adaptam as novas tecnologias CMOS de baixo custo. O objetivo deste trabalho é demonstrar a viabilidade e as vantagens do uso de um LNA digitalmente configurável em uma cadeia de recepção de radiofrequência do ponto de vista de custo e consumo de potência.