京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第20405号 / 工博第4342号 / 新制||工||1673(附属図書館) / 京都大学大学院工学研究科高分子化学専攻 / (主査)教授 大北 英生, 教授 赤木 和夫, 教授 木村 俊作 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DGAM

As tensões induzidas e sobretensões geradas por descarga atmosféricas diretas e indiretas são um dos principais causadores de desligamentos não programados em redes de transmissão e distribuição. Estes desligamentos comprometem o fornecimento de energia a milhares de consumidores, sobretudo em regiões com constantes variações climáticas e com características orográficas bastante diversificadas, como apresentado no território brasileiro. Desse modo, cada vez mais esses fenômenos são estudados a fim de desenvolverem-se procedimentos para proteção contra distúrbios causados por descargas atmosféricas. Neste contexto, esta pesquisa contempla o estudo do estabelecimento das descargas atmosféricas indiretas e das tensões por elas induzidas em linhas de distribuição, assim como o assentamento das mesmas nestas redes de energia. Não obstante, utilizando-se um software capaz de representar transitórios eletromagnéticos são modelados e implementados um alimentador teste de distribuição e um sistema para estimação de tensões induzidas no domínio do tempo baseado no modelo de Sune Rusck. Também são modelados e implementados para-raios de óxido de zinco, de forma a representar suas características dinâmicas, para proteger a linha sob apreciação dos distúrbios provocados pelas tensões induzidas. A partir de uma análise comparativa entre a operação do sistema de distribuição em regime permanente e frente aos desdobramentos promovidos pelas tensões induzidas, é determinada a melhor configuração, localização e quantificação dos para-raios a serem instalados para proteção do sistema teste. Por meio da avaliação dos resultados das simulações computacionais observa-se a robustez da subestação e quais os ramos e cargas mais suscetíveis a perturbações frente às tensões induzidas, bem como a maior proteção oferecida pelos para-raios aos elementos conectados próximos aos seus nós de alocação. / The induced voltages and overvoltages generated by direct and indirect lightning are a major cause of not programmed shutdowns in transmission and distribution networks. These shutdowns compromise the power supply of thousands of consumers, especially in regions with frequent climatic variations and quite diverse orographic characteristics, as occurred on Brazilian soil. Thus, these phenomena are more and more studied in order to develop procedures for protection against disturbances caused by lightning. In this context, this research focuses on the study of the establishment of indirect lightning and the voltage induced by them on distribution lines, as well as their settlement on energy networks. However, using a software able to represent electromagnetic transients, a distribution test feeder and a system for estimating induced voltages in the time domain based on the Sune Rusck model are modeled and implemented. In addition, metal oxide surge arresters are modeled and implemented to represent its dynamic characteristics, in order to protect the line under consideration of disturbances caused by induced voltages. From a comparative analysis between the operation of the distribution system in steady state and facing the developments promoted by induced voltages, it is determined the best configuration, as well as the location and quantification of the surge arrester to be installed to protect the test system. Through evaluation of the results of computer simulations, it is observed the robustness of the substation and which branches and loads are more susceptible to the disturbances facing the induced voltages, and the greater protection offered by the surge arresters elements connected near to its nodes allocation.

As tensões induzidas e sobretensões geradas por descarga atmosféricas diretas e indiretas são um dos principais causadores de desligamentos não programados em redes de transmissão e distribuição. Estes desligamentos comprometem o fornecimento de energia a milhares de consumidores, sobretudo em regiões com constantes variações climáticas e com características orográficas bastante diversificadas, como apresentado no território brasileiro. Desse modo, cada vez mais esses fenômenos são estudados a fim de desenvolverem-se procedimentos para proteção contra distúrbios causados por descargas atmosféricas. Neste contexto, esta pesquisa contempla o estudo do estabelecimento das descargas atmosféricas indiretas e das tensões por elas induzidas em linhas de distribuição, assim como o assentamento das mesmas nestas redes de energia. Não obstante, utilizando-se um software capaz de representar transitórios eletromagnéticos são modelados e implementados um alimentador teste de distribuição e um sistema para estimação de tensões induzidas no domínio do tempo baseado no modelo de Sune Rusck. Também são modelados e implementados para-raios de óxido de zinco, de forma a representar suas características dinâmicas, para proteger a linha sob apreciação dos distúrbios provocados pelas tensões induzidas. A partir de uma análise comparativa entre a operação do sistema de distribuição em regime permanente e frente aos desdobramentos promovidos pelas tensões induzidas, é determinada a melhor configuração, localização e quantificação dos para-raios a serem instalados para proteção do sistema teste. Por meio da avaliação dos resultados das simulações computacionais observa-se a robustez da subestação e quais os ramos e cargas mais suscetíveis a perturbações frente às tensões induzidas, bem como a maior proteção oferecida pelos para-raios aos elementos conectados próximos aos seus nós de alocação. / The induced voltages and overvoltages generated by direct and indirect lightning are a major cause of not programmed shutdowns in transmission and distribution networks. These shutdowns compromise the power supply of thousands of consumers, especially in regions with frequent climatic variations and quite diverse orographic characteristics, as occurred on Brazilian soil. Thus, these phenomena are more and more studied in order to develop procedures for protection against disturbances caused by lightning. In this context, this research focuses on the study of the establishment of indirect lightning and the voltage induced by them on distribution lines, as well as their settlement on energy networks. However, using a software able to represent electromagnetic transients, a distribution test feeder and a system for estimating induced voltages in the time domain based on the Sune Rusck model are modeled and implemented. In addition, metal oxide surge arresters are modeled and implemented to represent its dynamic characteristics, in order to protect the line under consideration of disturbances caused by induced voltages. From a comparative analysis between the operation of the distribution system in steady state and facing the developments promoted by induced voltages, it is determined the best configuration, as well as the location and quantification of the surge arrester to be installed to protect the test system. Through evaluation of the results of computer simulations, it is observed the robustness of the substation and which branches and loads are more susceptible to the disturbances facing the induced voltages, and the greater protection offered by the surge arresters elements connected near to its nodes allocation.

Cette thèse s’intéresse au diagnostic de défauts de réseaux électriques filaires à l'aide de la réflectométrie. Pour concevoir des algorithmes de diagnostic, nous avons étudié le problème direct (simulations numériques des réseaux électriques) et le problème inverse (détermination de certaines propriétés d’un réseau à partir des mesures de réflectométrie). Concernant le problème direct, nous avons développé une méthode de calcul du coefficient de réflexion d’un réseau sous forme d’arbre qui est basée sur la résolution successive d’équations différentielles de Riccati. Nous avons également généralisé l’équation de BLT pour des réseaux électriques composés de branches non uniformes et automatisé la méthode de sa résolution. La thèse a apporté deux nouveaux résultats concernant le problème inverse. Le premier résultat porte sur l’estimation des longueurs et des coefficients de pertes des branches d'un réseau électrique sous forme d’étoiles via une méthode itérative. Le deuxième porte sur l’identification, au moins partiellement, des matrices d’admittance des branches d’un réseau électrique modélisé par l’équation de BLT. Les méthodologies et les formalismes proposés dans la thèse sont validés soit par des simulations numériques, soit par des mesures réelles. / This thesis focuses on fault diagnosis of wired electric networks using reflectometry. To develop diagnostic algorithms, we studied the direct problem (numerical simulations of electrical networks) and the inverse problem (determination of certain properties of a network from reflectometry measurements). For the direct problem, we developed a method for the computation of reflection coefficients. This method is based on the successive solving for a Riccati differential equation. We also generalized the BLT equation for the nonuniform electric networks and automated the resolution of this method. The thesis has made two new results concerning the inverse problem. The first result concerns the estimation of lengths and loss coefficients of the branches of a star network via an iterative method. The second focuses on the identification, at least partially, of the branches admittance matrices of a electric network modeled by the equation of BLT. The methodologies and formalisms proposed in this thesis are validated either by numerical simulations or by real measurements.

<p>U ovoj doktorskoj disertaciji razvijena je tehnika upravljanja za<br />pretvarač energetske elektronike pri nesimetričnim naponskim<br />prilikama u elektroenergetskom sistemu. Kao što je pokazano,<br />primenom tehnike poništavanja signala kašnjenjem moguće je<br />izdvajanje komponenti struje inverznog redosleda i njihovo<br />potpuno poništenje, što će omogućiti pouzdanu kontrolu<br />komponenti struje direktnog redosleda upotrebom klasičnih<br />tehnika upraljanja, uz adekvatno unapređenje tehnike za<br />sinhronizaciju sa vektorskim reprezentom napona. Predložena<br />je i upotreba algoritama za poboljšanje parametara kvaliteta<br />električne energije bez dodatnih pasivnih elemenata.</p> / <p>This PhD thesis presents an improved control technique for grid<br />connected converter under asymmetrical voltages at the point of<br />common coupling. As presented, using delay signal cancellation<br />technique it is possible to differentiate and completely mitigate the<br />negative sequence current, offering the possibility of reliable positive<br />sequence current control using classical control algorithms. The<br />improvements made in synchronization offered adequate<br />phase angle estimation under voltage asymmetry. Furthermore, a<br />technique for the improvement of power quality indices without<br />passive elements between the grid and</p>

Les développements récents des techniques IRM engendre des sources de potentiels induits qui « polluent » les signaux électrophysiologiques, utilisé simultanément en IRM pour surveiller le patient et synchroniser les images. Le système élaboré dans ce travail est compose de deux modules « émetteur-récepteur » IRM-compatibles. Le premier permet d’introduire dans le tunnel d’IRM des signaux EPS dont on connait les caractéristiques. Les signaux sont injectés dans un tissu conducteur placé dans le tunnel. Le second module permet de recueillir les signaux après leur contamination par les artéfacts générés par les séquences d’imagerie. Il comporte 20 canaux répartis en quatre bandes fréquentielles (40, 80, 160 et 350 Hz). Des mesures du potentiel induit ont été réalisées en environnements 1,5 T et 3 T. Nous pouvons ainsi analyser les modifications des paramètres des signaux selon les séquences, mais aussi à l’intérieur des différentes bandes de fréquences. Dans ce travail, nous présentons une caractérisation et modélisation des potentiels induits par les commutations de gradients de champ magnétique recueilli par notre dispositif expérimental. La caractérisation et la modélisation permettent d’obtenir des informations pertinentes à prendre en compte pour l’élaboration des algorithmes de filtrage efficaces et robustes. / New developments in MRI techniques create sources of induced voltages that “pollute” the simultaneously acquired electrophysiological signals (EPS), used to monitor patients and/or synchronize images. We developed a device to allow a deep study of the contamination mechanism, which would assist in elaborating new tools to obtain higher quality EPS. The system consists of three main modules: (i) a signal transmission system composed of an EPS generator and a transmission box, which transmits the EPS to a MR-compatible receiver inside the tunnel, (ii) an electro-conductive tissue-mimicking phantom in which the EPS is injected, (iii) a signal collection module composed of a MR compatible amplifier-transmitter that emits, via an optical cable, the collected signal to a receiver box placed outside the MRI room. The receiver box comprises 20 channels distributed into four frequency bands (40, 80, 160, and 350 Hz). Measurements of the induced voltages were performed in 1.5 T and 3 T MRI environments. An algorithm to extract and analyze and model the induced voltages was developed. The modeling algorithm is based on a sinusoidal decomposition of the induced voltages. This work aimed to assess the disturbance level of the EPS, when using larger bandwidth amplifiers. The characterization and modeling of the induced voltages, which represent the dominant noise, reveal relevant information which can be used to develop robust and efficient noise reduction algorithms.

The proliferation of portable systems and mobile computing platforms has increased the need for the design of low power consuming integrated circuits. The increase in chip density and clock frequencies due to technology advances has made low power design a critical issue. Low power design is further driven by several other factors such as thermal considerations and environmental concerns. In low-power design for battery driven portable applications, the reduction of peak power, peak power differential, average power and energy are equally important. In this dissertation, we propose a framework for the reduction of these parameters through datapath scheduling at behavioral level. Several ILP based and heuristic based scheduling schemes are developed for datapath synthesis assuming : (i) single supply voltage and single frequency (SVSF), (ii) multiple supply voltages and dynamic frequency clocking (MVDFC), and (iii) multiple supply voltages and multicycling (MVMC). The scheduling schemes attempt to minimize : (i) energy, (ii) energy delay product, (iii) peak power, (iv) simultaneous peak power and average power, (v) simultaneous peak power, average power, peak power differential and energy, and (vi) power fluctuation. A new parameter called "Cycle Power Function" (CPF) is defined which captures the transient power characteristics as the equally weighted sum of normalized mean cycle power and normalized mean cycle differential power. Minimizing this parameter using multiple supply voltages and dynamic frequency clocking results in the reduction of both energy and transient power. The cycle differential power can be modeled as either the absolute deviation from the average power or as the cycle-to-cycle power gradient. The switching activity information is obtained from behavioral simulations. Power fluctuation is modeled as the cycle-to-cycle power gradient and to reduce fluctuation the mean power gradient (MPG) is minimized. The power models take into consideration the effect of switching activity on the power consumption of the functional units. Experimental results for selected high-level synthesis benchmark circuits under different constraints indicate that significant reductions in power, energy and energy delay product can be obtained and that the MVDFC and MVMC schemes yield better power reduction compared to the SVSF scheme. Several application specific VLSI circuits were designed and implemented for digital watermarking of images. Digital watermarking is the process that embeds data called a watermark into a multimedia object such that the watermark can be detected or extracted later to make an assertion about the object. A class of VLSI architectures were proposed for various watermarking algorithms : (i) spatial domain invisible-robust watermarking scheme, (ii) spatial domain invisible-fragile watermarking scheme, (iii) spatial domain visible watermarking scheme, (iv) DCT domain invisible-robust watermarking scheme, and (v) DCT domain visible watermarking scheme. Prototype implementation of (i), (ii) and (iii) are given. The hardware modules can be incorporated in a "JPEG encoder" or in a "digital still camera".

Multilevel inverters have advantages over two-level inverters such as reduced THD, ability to operate at low switching frequencies, reduced switching losses etc. Moreover, higher voltage levels can be handled with devices of lower voltage rating. The main disadvantage with the multilevel configurations compared to the two-level inverter configuration is the increase in the number of power devices required and the circuit complexity, which necessitates complex control schemes that add to the cost. Also, the reliability of the converters comes down as the number of devices increases. Reduction in complexity and modularity are desirable characteristics for the multilevel inverters. Open-end winding Induction Motor (IM) drive configurations are shown to have advantages over the motor drive schemes with isolated neutral. The DC-link requirement in case of open-end winding structures comes down to half the voltage rating of the conventional NPC inverters. The DC- link requirement in case of open-end winding structures comes down to half compared to that of the conventional NPC inverters. The number of switching states is higher in the case of open-end winding configuration compared to multiplicity of switching states of conventional NPC inverters, which gives a control flexibility that can be used for optimizing the hardware requirements. Taking advantage of the flexibility given by open-end winding configuration, this thesis proposes schemes which have reduced power circuit complexity. Non-sinusoidal voltage fed IM drives suffer from the problems related to the common mode voltage (CMV) generated by the inverters. This CMV causes bearing currents and shaft voltages which in turn cause increased conducted EMI, ground loop currents and premature bearing failure. A three-level scheme was proposed for an open-end winding Induction machine in the literature, which completely eliminate the CMV variation from the pole voltages as well as the phase voltages. This configuration uses 24 controlled switches and two isolated DC-sources. In this thesis, three-level inverter schemes with CMV elimination and reduced power device count for an open-end winding IM drive are proposed. The first scheme gets the reduction in switch count by sharing the top inverter of the three-level scheme and the second scheme achieves the same by sharing the bottom inverter. This way, the number of controlled switches comes down to 18 from 24. Another problem with multilevel inverters is the large number of isolated DC-sources required to achieve the multilevel inversion. Reducing the number of isolated supplies and using capacitors to split the voltage levels poses the problem of capacitor voltage balancing. A four-level inverter with both CMV elimination and capacitor voltage balancing for an open-end winding IM drive is proposed in this thesis. The motor is fed by two four-level inverters from both the sides. A closed loop capacitor voltage balancing scheme is implemented and the redundancies in the switching states are used for achieving the capacitor voltage balancing and thereby reducing the total number of DC-link to two. The control scheme is independent of the load power factor and maintains the balance in the entire modulation range. A five-level inverter scheme is proposed for an open-end winding IM drive in this thesis. It requires only two isolated DC-sources to achieve the five-level inversion. The motor is fed by one NPC three-level inverter from one side and a two-level inverter from the other. The inverters on either side share the DC-sources. Common mode voltage in the phases are made zero in an average sense using sine-triangle modulation in the proposed scheme so that the common mode currents through the phases are suppressed. The maximum fundamental voltage that can be obtained at the phase is limited to 0.5Vdc. DC-link requirement of the inverter scheme is half of that of conventional five-level inverter scheme because of the open-end winding structure. The two-level inverter, which should withstand half the DC-link voltage, is always in square wave operation and hence the switching losses are very less. All the schemes are simulated extensively in MATLAB/Simulink and experimentally verified on laboratory prototypes under V/f control. TI Motor control DSP and Xilinx CPLD/FPGA are used for generation of the PWM signals for the schemes. The inverters are switched at around 1.25 kHz to keep the switching losses low. Due to laboratory constraints, the experimental verification is done on low power prototypes. Nonetheless, the generality of the schemes allow them to be used for medium voltage high power applications.

The demand for devices like Personal Digital Assistants (PDA’s), Laptops, Smart Mobile Phones, are at an all time high. As the demand for these devices increases, so is the push to provide sophisticated functionalities in these devices. However energy consumption has become a major constraint in providing increased functionality for these devices. A majority of the applications meant for these devices are rich with multimedia content. In this thesis, we propose two approaches for compiler directed energy reduction, one targeting the memory subsystem and another the processor. The first technique is a compiler directed optimization technique that reduces the energy consumption of the memory subsystem, for an off-chip partitioned memory archi- tecture, having multiple memory banks, and various low-power operating modes for each of these banks. We propose an efficient layout of the data segment to reduce the number of simultaneously active memory banks, so that the other memory banks that are inactive can be put to low power modes to reduce the energy. We model this problem as a graph partitioning problem, and use well known heuristics to solve the same. We also propose a simple Integer Linear Programming (ILP) formulation for the above problem. Perfor- mance results indicate that our approach achieves an energy reduction of 20% compared to the base scheme, and a reduction of 8%-10% over a previously suggested method. Also, our results are well within the optimal results obtained by using ILP method. The second approach proposed in this thesis reduces the dynamic energy consumed by the processor using dynamic voltage and frequency scaling technique. Earlier works on dynamic voltage scaling focused mainly on performing voltage scaling when the CPU is waiting for memory subsystem or concentrated chiefly on loop nests and/or subroutine calls having sufficient number of dynamic instructions. We concentrate on coarser pro- gram regions and for the first time uses program phase behavior for performing dynamic voltage scaling. We relate the Dynamic Voltage Scaling Problem to the Multiple Choice Knapsack Problem, and use well known heuristics to solve it efficiently. Also, we develop a simple Integer Linear Programming (ILP) problem formulation for this problem. Experi-mental evaluation on a set of media applications reveal that our heuristic method obtains 35-40% reduction in energy consumption on an average, with a negligible performance degradation. Further the energy consumed by our heuristic solution is within 1% the optimal solution obtained by the ILP approach.

Includes vita. / Title from PDF of title page. / Document formatted into pages; contains 289 pages. / Thesis (Ph.D.)--University of South Florida, 2003. / Includes bibliographical references. / Text (Electronic thesis) in PDF format. / ABSTRACT: The proliferation of portable systems and mobile computing platforms has increased the need for the design of low power consuming integrated circuits. The increase in chip density and clock frequencies due to technology advances has made low power design a critical issue. Low power design is further driven by several other factors such as thermal considerations and environmental concerns. In low-power design for battery driven portable applications, the reduction of peak power, peak power differential, average power and energy are equally important. In this dissertation, we propose a framework for the reduction of these parameters through datapath scheduling at behavioral level. Several ILP based and heuristic based scheduling schemes are developed for datapath synthesis assuming : (i) single supply voltage and single frequency (SVSF), (ii) multiple supply voltages and dynamic frequency clocking (MVDFC), and (iii) multiple supply voltages and multicycling (MVMC). / ABSTRACT: The scheduling schemes attempt to minimize : (i) energy, (ii) energy delay product, (iii) peak power, (iv) simultaneous peak power and average power, (v) simultaneous peak power, average power, peak power differential and energy, and (vi) power fluctuation. A new parameter called "Cycle Power Function" CPF) is defined which captures the transient power characteristics as the equally weighted sum of normalized mean cycle power and normalized mean cycle differential power. Minimizing this parameter using multiple supply voltages and dynamic frequency clocking results in the reduction of both energy and transient power. The cycle differential power can be modeled as either the absolute deviation from the average power or as the cycle-to-cycle power gradient. The switching activity information is obtained from behavioral simulations. Power fluctuation is modeled as the cycle-to-cycle power gradient and to reduce fluctuation the mean power gradient MPG is minimized. / ABSTRACT: The power models take into consideration the effect of switching activity on the power consumption of the functional units. Experimental results for selected high-level synthesis benchmark circuits under different constraints indicate that significant reductions in power, energy and energy delay product can be obtained and that the MVDFC and MVMC schemes yield better power reduction compared to the SVSF scheme. Several application specific VLSI circuits were designed and implemented for digital watermarking of images. Digital watermarking is the process that embeds data called a watermark into a multimedia object such that the watermark can be detected or extracted later to make an assertion about the object. / ABSTRACT: A class of VLSI architectures were proposed for various watermarking algorithms : (i) spatial domain invisible-robust watermarking scheme, (ii) spatial domain invisible-fragile watermarking scheme, (iii) spatial domain visible watermarking scheme, (iv) DCT domain invisible-robust watermarking scheme, and (v) DCT domain visible watermarking scheme. Prototype implementation of (i), (ii) and (iii) are given. The hardware modules can be incorporated in a "JPEG encoder" or in a "digital still camera". / System requirements: World Wide Web browser and PDF reader. / Mode of access: World Wide Web.