In this work the usage of a WLC (Wafer Level Camera) for ensuring road safety has been presented. A prototype of a WLC along with the Aptina MT9M114 stereoboard has been used for this project. The basic idea is to observe the movements of the driver. By doing so an understanding of whether the driver is concentrating on the road can be achieved. For this project the display of the required scene is captured with a wafer-level camera pair. Using the image pairs stereo processing is performed to obtain the real depth of the objects in the scene. Image recognition is used to separate the object from the background. This ultimately leads to just concentrating on the object which in the present context is the driver.

In today's semiconductor-based computer and communication technology, system performance is determined primarily by two factors, namely on-chip and off-chip operating frequency. In this dissertation, time-domain measurement-based methods that enable gigabit data transmission in both the IC and package have been proposed using Time-Domain Reflectometry (TDR) equipment. For the evaluation of the time-domain measurement-based method, a wafer level package test vehicle was designed, fabricated and characterized using the proposed measurement-based methods. Electrical issues associated with gigabit data transmission using the wafer-level package test vehicle were investigated. The test vehicle consisted of two board transmission lines, one silicon transmission line, and solder bumps with 50um diameter and 100um pitch. In this dissertation, 1) the frequency-dependent characteristic impedance and propagation constant of the transmission lines were extracted from TDR measurements. 2) Non-physical RLGC models for transmission lines were developed from the transient behavior for the simulation of the extracted characteristic impedance and propagation constant. 3) the solder bumps with 50um diameter and 100um pitch were analytically modeled. Then, the effect of the assembled wafer-level package, silicon substrate and board material, and material interfaces on gigabit data transmission were discussed using the wafer-level package test vehicle. Finally, design recommendations for the wafer-level package on integrated board were proposed for gigabit data transmission in both the IC and package.

According to the fast development of portable electronic devices, their characteristics are inclined to miniature profile and lightweight. Nowadays, the wafer-level package (WLP) has been widely applied in portable electronic devices for its miniature profile and lightweight. It will become the mainstream trend later soon. The normal use of portable electronic devices brings low-frequency random vibrations to the electronic packages inside. Because of the increasing demand of these devices, the reliability of electronic packages subjected to repeated mechanical loads has become an important issue in the contemporary electronic packaging industry. In this paper both numerical and experimental studies were carried out to investigate the reliability life of Ultra-CSP under cyclic bending conditions. We perform four-point cyclic bending with various combinations of amplitudes and frequencies. Then, we do failure analysis in Ultra-CSP by observing the failure modes. A finite element model for the package is built up for dynamic as well as quasi-static analyses. Accumulated plastic work per bending cycle within the critical solder ball were calculated and together with the experimental results the parameters for the Coffin-Manson fatigue equation were fitted. Through finite element analysis we find that the solder ball which located in the corner has higher accumulated plastic work. Therefore, the crack in the solder ball grew more easily. Thus it lets package resistance rise to determine failure. It was observed from the bending experiments that the influence of frequencies on the fatigue life of the solder interconnects is inapparent. However, influence of amplitude is significant. From the results of both experiments and FEA, it was found that for this particular ultra-CSP specimen under cyclic bending conditions, the characteristic life was expressed as

L’étude présentée s’inscrit dans le cadre général de l’amélioration de la fiabilité mécanique des composants électroniques. Les composants de type WL-CSP (Wafer-Level Chip-Scale Package : boîtier aux dimensions comparables à celles de la puce) sont couramment utilisés dans les appareils nomades (par exemple les téléphones) et assurent de nombreuses fonctions. La tenue dans le temps de ces appareils passe par l’allongement de la durée de vie de leurs éléments. Ce sujet est une problématique complexe car la structure des composants peut varier selon les technologies employées et nécessite des essais spécifiques, qui consomment beaucoup de temps et de ressources.Un modèle numérique est développé afin d’accélérer le développement des boîtiers de ces composants et d’optimiser les ressources disponibles. Des essais de fiabilité sont menés sur le test de chute et un banc d’essai de flexion est mis en place. Les résultats de ces essais permettent de valider la simulation numérique et de mettre au point un modèle de fatigue.D’autre part, une campagne de caractérisation des matériaux permet de déterminer les propriétés mécaniques de la structure étudiée. La caractérisation concerne notamment les couches minces pour lesquelles les propriétés mécaniques sont fortement dépendantes de leurs conditions de dépôts.Ces éléments sont incorporés dans un modèle numérique incluant un certain nombre d’hypothèses. Le modèle est confronté à l’expérience pour déterminer les constantes d’un modèle de fatigue. Ensuite, la simulation et le modèle de fatigue sont utilisés conjointement pour évaluer l’influence de paramètres géométriques et matériaux sur la fiabilité des composants de type WL-CSP. / The work described in this report is related to the mechanical improvement of electronicdevices mechanical reliability. WL-CSP (Wafer-Level Chip-Scale Package) components are widely used in handheld devices and run many functions. The longevity increase of such adevice necessarily requires progresses in its components reliability. This subject is complexas the component structure can vary depending on the employed technologies. So, it requires time and ressources.A numerical model is developed to enhance the packages development as well as available resources. Reliability tests are performed on the drop-test bench and a bend-testbench is designed. These tests provide results to validate the numerical results and to establish a fatigue model.Aside from these tests, the component materials are characterized to determine the studied structure properties. It specifically concerns the thin layers for which mechanical properties strongly depends on the deposition process. All of this is incorporated in a numerical model which includes hypotheses. The model is compared with the experiments to determine fatigue model constants. Then, modeling and experiments are used together to evaluate material and geometrical parameters influence.

Kyoto University (京都大学) / 0048 / 新制・論文博士 / 博士(工学) / 乙第12493号 / 論工博第4047号 / 新制||工||1503(附属図書館) / 28243 / (主査)教授 平尾 一之, 教授 横尾 俊信, 教授 田中 勝久 / 学位規則第4条第2項該当

L'objectif de cette thèse est d'établir les liens entre élaboration, microstructure et comportement des getters non-évaporables (NEG) en couches minces, en vue de leur utilisation dans le cadre du packaging collectif des MEMS sous vide ou sous atmosphère contrôlée. Après une étude bibliographique sur l'herméticité des MEMS et l'effet getter, la modification du comportement de piégeage de gaz par les NEG couches minces, engendré par l'ajout de sous-couches métalliques, est mise en évidence. Afin d'expliquer cette influence, la microstructure des couches minces est étudiée, notamment sa dépendance aux paramètres d'élaboration et aux traitements thermiques. Ensuite, le comportement macroscopique de piégeage de l'azote est caractérisé, de même que les mécanismes microscopiques d'activation et de pompage. Ces derniers permettent finalement d'élaborer quelques recommandations pour l'intégration des NEG couches minces dans les MEMS. / Whilst satisfying low-cost requirements, performances and lifetime of many MEMS can be enhanced by performing wafer-level packaging of devices under vacuum or controlled atmosphere conditions. However, this implies the use of non-evaporable getters (NEG) inside MEMS cavities for residual gases removal. Relationships between elaboration, microstructure and pumping behavior of NEG thin films are investigated in this thesis. After a literature review on MEMS hermetic sealing and getter effect, NEG thin films pumping behavior modification by metallic sub-layers addition is presented. Then, in order to explain this modification, elaboration parameters and thermal treatments influence on thin films microstructure is analyzed. Lastly, nitrogen gettering behavior of NEG is characterized, as well as activation and pumping mechanisms. From these results, some recommendations for NEG thin films integration in MEMS are finally proposed.

Depuis l'invention du transistor dans les années 50, les performances des composants microélectroniques n'ont cessé de progresser, en passant notamment par l'augmentation de leur densité. Malheureusement, la miniaturisation des composants augmente les coûts de fabrication de façon prohibitive. Une solution, permettant d'accroître la densification et les fonctionnalités tout en limitant les coûts, passe par l'empilement des composants microélectroniques. Leurs connexions électriques s'effectuent alors à l'aide d'interconnexions verticales soudées au moyen d'un joint de brasure. Afin d'empêcher leurs ruptures lors des dilatations thermiques, les interconnexions sont protégées au moyen d'un polymère underfill. L'objectif de cette thèse est d'évaluer la faisabilité et la pertinence d'une nouvelle solution de remplissage par polymère, appelée wafer-level underfill (WLUF). L'écoulement de l'underfill durant l'étape d'assemblage des composants est modélisé afin de prédire les paramètres de scellement idéaux, permettant la formation des interconnexions électriques. Puis, l'intégration de nouveaux underfills, possédant des propriétés thermomécaniques différentes, pouvant affecter l'intégrité et le fonctionnement du dispositif, l'étude de la fiabilité du procédé WLUF et, par conséquent, l'évaluation de sa possibilité d'industrialisation est effectuée. / Since the invention of the transistor in the Fifties, performances of microelectronics components did not cease progressing thanks to their density increase. Unfortunately, miniaturization of components increases manufacturing costs in a prohibitory way. A solution, allowing densification and functionalization increase without costs rise, is microelectronics components stack. Their electrical connections are carried out using vertical interconnections welded by means of solder joints. In order to prevent their ruptures during thermal dilatations, interconnections are protected thanks to polymer underfill. The objective of this thesis is to evaluate the feasibility and the relevance of a new solution of polymer filling, called wafer-level underfill (WLUF). Flow of underfill during components assembly step is modeled in order to predict ideal bonding parameters, allowing electrical interconnections formation. Then, integration of new underfills, having different thermomechanical properties, being able to affect device integrity and functioning, the study of WLUF process reliability and, consequently, the evaluation of its industrialization possibility is carried out.

Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung List of symbols and abbreviations Acknowledgement 1. Introduction 2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias 3. Fabrication of BiCMOS & Silicon Interposer with TSVs 4. Characterization of BiCMOS Embedded Through-Silicon Vias 5. Applications 6. Conclusion and Future Work 7. Appendix 8. Publications & Patents 9. Bibliography 10. List of Figures and Tables

Ce travail de thèse vise la définition et la mise au point de technologies pour l'empilement depuces microélectroniques dans un polymère et connectées électriquement par des viastraversants. Il explore deux voies : l’une de caractère industriel, utilisant une résine époxychargée en billes de silice E2517, l'autre, plus exploratoire, est basée sur l'utilisation de laSU8.Nous avons travaillé sur la mise au point des différentes étapes permettant d'empiler 4niveaux de puces amincies à 80 microns (enrobées) et empilées sur des épaisseurs de l'ordredu millimètre. Le problème du perçage des vias a été abordé et étudié à travers la mise aupoint de procédés d'usinage au laser des résines de type industriel. La métallisation encouches minces de ces trous de facteur de forme élevée (20) a été menée de sorte à atteindredes valeurs de résistance d'accès les plus faibles possibles.Un comparatif des deux voies utilisant la SU8 et la résine E2517 a été effectué et ses résultatscommentés en termes de faisabilité techniques et ses projections dans le domaine industriel.Des tests de fiabilité thermomécaniques ont été menés de concert avec une modélisation paréléments fini afin de valider les résultats des expérimentations réalisées dans le cadre de cetteétude / The subject of this thesis is the definition and development of TPV (Through Polymer Via)technology to stacking chips. The principal objective is to increase the potentialities of thevertical staking (complex IC; multiple I/O...) of Si chips without loss of performance or yield.The technique used consists to surround the IC chips by using particular resin and to fill (withmetallic films) the vertical holes drilled in this material. It explores two ways: one of anindustrial character, using an epoxy resin filled with silica beads E2517, other, moreexploratory, is based on the use of SU8.We worked on the development of different stages to stack four levels of chips thinned to 80microns (coated) and stacked on the thickness of one millimeter. The problem of drilling viashas been discussed and studied through the development of laser drilling processes ofindustrial resins. The thin-film metallization of the holes of high aspect ratio (20) wasconducted in order to reach values of access resistance as low as possible.A comparison of the two channels using SU8 resin and E2517 was carried out and the resultsdiscussed in terms of technical feasibility and its projections in the industrial field.Thermomechanical reliability tests were conducted in conjuction with finite element modelingto validate the results of experiments conducted in this study.

Conventional tin-lead solder alloys have been widely used in electronics interconnection owing to their properties such as low melting temperature, good ductility and excellent wettability on copper and other substrates. However, due to the worldwide legislation addressing the concern over the toxicity of lead, the usage of lead-containing solders has been phased out, thus stimulating substantial efforts on lead-free alternatives, amongst which eutectic Sn-Ag and Sn-Cu, and particularly Sn-Ag-Cu alloys, are promising candidates as recommended by international parties. To meet the increasing demands of advanced electronic products, high levels of integration of electronic devices are being developed and employed, which is leading to a reduction in package size, but with more and more input/output connections. Flip chip technology is therefore seen as a promising technique for chip interconnection compared with wire bonding, enabling higher density, better heat dissipation and a smaller footprint. This thesis is intended to investigate lead-free (eutectic Sn-Ag, Sn-Cu and Sn-Ag-Cu) wafer level solder bumping through electrodeposition for flip chip interconnection, as well as electroplating lead-free solderable finishes on electronic components. The existing knowledge gap in the electrochemical processes as well as the fundamental understanding of the resultant tin-based lead-free alloys electrodeposits are also addressed. For the electrodeposition of the Sn-Cu solder alloys, a methanesulphonate based electrolyte was established, from which near-eutectic Sn-Cu alloys were achieved over a relatively wide process window of current density. The effects of methanesulphonic acid, thiourea and OPPE (iso-octyl phenoxy polyethoxy ethanol) as additives were investigated respectively by cathodic potentiodynamic polarisation curves, which illustrated the resultant electrochemical changes to the electrolyte. Phase identification by X-ray diffraction showed the electrodeposits had a biphasic structure (β-Sn and Cu6Sn5). Microstructures of the Sn-Cu electrodeposits were comprehensively characterised, which revealed a compact and crystalline surface morphology under the effects of additives, with cross-sectional observations showing a uniform distribution of Cu6Sn5 particles predominantly along β-Sn grain boundaries. The electrodeposition of Sn-Ag solder alloys was explored in another pyrophosphate based system, which was further extended to the application for Sn-Ag-Cu solder alloys. Cathodic potentiodynamic polarisation demonstrated the deposition of noble metals, Ag or Ag-Cu, commenced before the deposition potential of tin was reached. The co-deposition of Sn-Ag or Sn-Ag-Cu alloy was achieved with the noble metals electrodepositing at their limiting current densities. The synergetic effects of polyethylene glycol (PEG) 600 and formaldehyde, dependent on reaching the cathodic potential required, helped to achieve a bright surface, which consisted of fine tin grains (~200 nm) and uniformly distributed Ag3Sn particles for Sn-Ag alloys and Ag3Sn and Cu6Sn5 for Sn-Ag-Cu alloys, as characterised by microstructural observations. Near-eutectic Sn-Ag and Sn-Ag-Cu alloys were realised as confirmed by compositional analysis and thermal measurements. Near-eutectic lead-free solder bumps of 25 μm in diameter and 50 μm in pitch, consisting of Sn-Ag, Sn-Cu or Sn-Ag-Cu solder alloys depending on the process and electrolyte employed, were demonstrated on wafers through the electrolytic systems developed. Lead-free solder bumps were further characterised by material analytical techniques to justify the feasibility of the processes developed for lead-free wafer level solder bumping.