Power device robustness refers to the device capability of withstanding abnormal events in power electronics applications, which is one of the key device capabilities that are desired in numerous applications. While the current robustness test methods and qualification standards are developed across the 70 years of Silicon (Si) device history, their applicability to the recent wide bandgap (WBG) power devices is questionable. While the market of WBG power devices has exceeded $1 billion and is fast growing, there are many knowledge gaps regarding their robustness, including the failure or degradation physics, testing methods, and lifetime extraction. This dissertation work studies the robustness of Gallium Nitride (GaN) power device. The structures of many GaN power devices are fundamentally different from Si or Silicon Carbide (SiC) power devices, leading to numerous open questions on GaN power device robustness. Based on the device structure, this dissertation is divided into two parts: The first half discusses the robustness of lateral GaN high electron mobility transistor (HEMT), which recently sees rapid adoption among wide range of applications such as the power adapter and chargers, data center, and photovoltaic panels. The absence of p-n junction between the source and drain of GaN HEMT results in the lack of avalanche mechanism. This raises a concern on the device capability of withstanding surge-energy or overvoltage stress, which hinders the penetration of GaN HEMTs in broader applications. To address this concern, the study begins with conducting the single-event unclamped inductive switching (UIS) test on two mainstream commercial p-gate GaN HEMTs with the Ohmic- and Schottky-type gate contacts, where the GaN HEMT is found to withstand surge energy through a resonant energy transfer between the device capacitance and the loop inductance. The failure mechanism is identified to be a pure electrical breakdown determined by device transient breakdown voltage (BV). The BV of GaN HEMT is further found to be "dynamic" from the switching tests with various pulse widths and frequencies, which is further explained by the time-dependent buffer trapping. This dynamic BV (BVDYN) phenomenon indicates that the static or single-pulse test may not reveal the true BV of GaN HEMT in high frequency switching applications. To address this gap, a novel testbed based on a zero-voltage-switching converter with an active clamping circuit is developed to enable the stable switching with kilovolt overvoltage and megahertz frequency. The overvoltage failure boundaries and failure mechanisms of four commercial p-gate GaN HEMTs from multiple vendors are explored. In addition to the frequency-dependent BVDYN, two new failure mechanisms are observed in some devices, which are attributable to the serious carrier trapping in GaN HEMTs under the high-frequency overvoltage switching. At last, based on the findings in the high frequency overvoltage test (HFOT), a physics-based lifetime model for commercial GaN HEMTs utilizing the device on resistance (RON) shift is established and validated by experimental results. Overall, the switching-based test methodology and experimental results provide critical references for the overvoltage protection and qualification of GaN power HEMTs. The second half of the dissertation discusses the robustness of the vertical GaN fin-channel junction field effect transistor (Fin-JFET), a promising pre-commercialized GaN power device with the p-n junction embedded between the gate and drain which enables the avalanche breakdown. The robustness study on GaN JFET follows similar test approaches as Si metal-oxide-semiconductor field-effect transistor (MOSFET) with two key interests: the avalanche and short circuit capabilities. The avalanche breakdown is first explored via the single-event and repetitive UIS tests and under various gate drivers, from which an interesting "avalanche-through-fin-channel" mechanism is discovered. By leveraging this avalanche path, the electro-thermal stress migrates from the main blocking p-n junction to the n-GaN fin channel, resulting in a very favorable failure-to-open-circuit signature. The single-pulse critical avalanche energy density (EAVA) of vertical GaN Fin-JFET is measured to be as high as 10 J/cm2, which is much higher than the Si MOSFET and comparable to the SiC MOSFET. The short circuit capability is explored utilizing the hard-switching fault on the 650-V rated GaN Fin-JFET, with a gate driving circuit identical to the switching application to best mimic device operation in converters. The short circuit withstanding time is measured to be 30.5 µs at an input voltage of 400 V, 17.0 µs at 600 V, and 11.6 µs at 800 V, all among the longest reported for 600-700 V normally-off transistors. In addition, the failure-to-open-circuit signature is also shown in the single-event and repetitive short circuit tests; all devices retain the avalanche breakdown after failure, which is highly desirable for system applications. These results suggest that, while GaN HEMT is already available in market, vertical GaN Fin-JFET shows superior avalanche and short-circuit robustness and thereby can unlock great potential of GaN devices for applications like automotive powertrains, motor drives, and grids. / Doctor of Philosophy / In recent years, many power electronics applications such as data centers and electric vehicles have witnessed a rapid increase in the adoption of wide bandgap (WBG) power devices. The Gallium Nitride (GaN) device is one of the most attractive candidates in WBG devices, owing to its good tradeoff between breakdown voltage and on resistance, as well as the small gate charge that enables high frequency switching. For power devices, their robustness against overvoltage and overcurrent stresses is as important as their performance under normal operations. However, the new material, new device structure, and new device physics in GaN power devices brought up many open knowledge gaps in their robustness study, particularly under the dynamic operation in switching circuits. This dissertation presents the work in exploring the robustness of GaN power devices. Based on the device structure, the discussion is divided in two parts: The first half of the dissertation focuses on the overvoltage robustness of the lateral GaN High Electron Mobility Transistor (HEMT), the commercially available device covering 30 to 900 V voltage classes. A key feature of this device is the lack of p-n junction between source and drain, leading to an absence of avalanche capability. The study is conducted on mainstream, commercial p-gate GaN HEMTs, with a combination of circuit testing, microscale failure analysis, and physics-based device simulation. The main contribution is on three aspects: identifying the single-event and high-frequency repetitive overvoltage boundaries of GaN HEMT, unveiling the failure and degradation mechanisms under transient overvoltage conditions, and providing guidelines to GaN HEMT device users with proper robustness test methodology for device qualification and screening. The second half of the dissertation focuses on the robustness of vertical GaN fin-channel junction field effect transistor (Fin-JFET), a promising pre-commercial GaN power device with the p-n junction implemented between the source and drain. The robustness tests follow the classic approaches deployed for Silicon power devices, where both the avalanche and short circuit capabilities are investigated. From the single-event and repetitive test results, the GaN JFET shows excellent avalanche robustness with a desirable failure-to-open-circuit behavior, as well as a critical avalanche energy (EAVA) of 10 J/cm2 that is higher than the Silicon metal-oxide-semiconductor field-effect transistor (MOSFET) and comparable to the Silicon Carbide MOSFET. For a 650-V rated GaN Fin-JFET, a record high 30.5 μs short circuit time is demonstrated under the hard-switching fault condition at 400 V input voltage. Overall, the results show great potential of GaN power devices for the power electronics applications that involve more stressful operation conditions for devices.

No description available.

The emergence of wide-bandgap-based (WBG) devices, such as silicon carbide (SiC) and gallium nitride (GaN), have unveiled unprecedented opportunities, enabling the realization of superior power conversion systems. Among the potential areas of advancement are medium-voltage (MV) and high-voltage (HV) applications, due to the growing demand for high-power-density and high-efficiency power electronics converters. These advancements have propelled a wide adoption of electric vehicles (EV), which in the future will require great improvements in the charging time of these vehicles. Thereby, this thesis attempts to address such a challenge and bring about technological improvements, enabling faster, more efficient, and more effective ways of charging an electric vehicle through the application of MV 3.3 kV SiC MOSFETs. The current fast-charging solution involves heavy and bulky MV-LV transformers, which add installation complexity for EV charging stations. However, this thesis presents an alternative power-delivery solution utilizing an MV dual-active-bridge (DAB) converter. The proposed architecture is designed to directly interface with the MV grid for high-power, fast-charging capabilities while eliminating the need for an installation of the MV-LV transformer. The MV DAB converter utilizes 3.3 kV SiC MOSFETs to realize the next 800 V EV charging system, along with an extended zero-voltage-switching (ZVS) scheme, in order to provide an efficient charging strategy across a wide range of battery voltage levels. Lastly, a detailed design comparison analysis of an MV Flyback converter, targeted for the auxiliary power supply for the proposed MV EV charging architecture, is presented. / The field of power electronics, which controls and manages the conversion of electrical energy, is an important topic of discussion, as new technologies like electric vehicles (EV) are quickly emerging and disrupting the current status-quo of vehicle-choice. In order to promote timely and extensive adoption of such an enabling EV technology, it is critical to understand the current challenges involving EV charging stations and seek out opportunities to engender future innovations. Indeed, wide-bandgap (WBG) devices, such as silicon carbide (SiC) and gallium nitride (GaN), have unveiled unprecedented opportunities in enabling the realization of superior power conversion systems. Thus, utilizing these WGB devices in EV charging applications can bring about improved design and development of EV fast chargers that are faster-charging, more efficient, and more effective. Hence, this thesis presents an opportunity in EV charging station applications with the utilization of medium-voltage SiC MOSFETs. Because the current fast-charging solution involves a heavy and bulky transformer, it adds installation complexity for EV charging stations. However, this thesis presents an alternative power-delivery solution that could potentially provide an efficient and fast-charging mechanism of EVs while reducing the size of EV chargers. All things considered, this thesis provides in-depth evaluation-studies of medium-voltage 3.3 kV SiC MOSFET-based power converters, targeted for future fast EV charging applications. The development and design of the hardware prototype is presented in this thesis, along with testing and verification of experimental results.

Power electronics plays an important role in many energy conversion applications in modern society including consumer electronics, data centers, electric vehicles, and power grids, etc. The key components of power electronic circuits are power semiconductor devices including diodes and transistors, which determine the performance of power electronics circuits. Traditional power devices are based on the semiconductor silicon (Si), which have already reached the silicon's material limit. Gallium nitride (GaN) is a wide bandgap semiconductor with high electron mobility and high critical electric field. GaN-based power devices promise superior device performance over the Si-based counterpart. The primary design target of a unipolar power device is to achieve low on-resistance and high breakdown voltage. Although GaN high electron mobility transistor (HEMT) is commercially available in a voltage class from 15 V to 900 V, the performance of GaN devices is still far below the GaN material limit, due to several reasons: 1) To achieve the normally-off operation in a GaN HEMT, the density of two-dimensional electron gas (2DEG) channel cannot be too high; this limits the on-resistance reduction in the access region. 2) The gate capacitance of GaN HEMT is usually low so that the carrier concentration in the channel underneath the gate is relatively low, limiting the on-resistance reduction in the gated channel region. 3) The electric-field distribution in the drift region is not uniform, resulting in a limited breakdown voltage. We proposed to use the junction-based structure in GaN power devices to address the above problems and fully exploit GaN's material properties. The first part of this dissertation characterizes nickel oxide (NiO) as a p-type material to construct the junction-based GaN power devices. Although the homogenous p-GaN/n-GaN junction is preferred in many devices, the selective-area, p-GaN regrowth can lead to excessive leakage current; in comparison, the p-NiO/n-GaN junction is stable without leakage. This section describes the optimization of NiO deposition as well as the NiO characterization. Although acceptor in NiO is not generated by impurity doping, the acceptor concentration modulation is realized by tuning the O2 partial pressure during the sputtering process. Practical breakdown electric field is also characterized and confirmed to be higher than GaN. These results provide the design guidelines for NiO-GaN junction-based power devices. The second part of this dissertation demonstrates the 3D NiO-GaN junction gate to improve the GaN HEMT's on-resistance. The 3D junction gate structure enables a high carrier concentration under the gate region in the device on-state. Meanwhile, the strong depletion effect of the junction-based gate allows for a robust normally-off operation; as a result, the GaN wafer with a higher 2DEG concentration can be used to achieve both normally-off and low on-state resistance in HEMT devices. Simulation is also performed to project the performance space of trigate GaN junction HEMTs using the p-GaN instead of NiO. The third part of this dissertation presents the application of the p-GaN/n-GaN junction in the drift region of the multi-channel lateral devices to achieve the high breakdown voltage. Here p-GaN is grown in-situ with the multi-channel AlGaN/GaN structure, and there is no leakage problem. The structure is designed to achieve charge balance between the acceptor in p-GaN and the net donor in the multichannel AlGaN/GaN. This design enables a uniform electric field distribution and breakdown voltage over 10 kV. The fourth part of this dissertation presents the application of the p-NiO/n-GaN junction in vertical superjunction (SJ) devices. We show the design and simulation of this heterojunction structure in a SJ and confirm the uniform electric field and high breakdown voltage under the charge balance. Then the device fabrication is presented in detail, which mainly comprises the deep GaN trench etch, NiO self-aligned lift off, and photoresist trench planarization. The optimized device shows a trade-off between its drift region specific on-resistance versus breakdown that exceeds the 1D GaN's limit. The last part of this dissertation is exploring the design and fabrication of p-GaN/n-GaN based SJ devices. First, the challenges in p-GaN regrowth especially the introduction of interface impurities are discussed, followed by device simulation and modeling to optimize the SJ performance considering these interface impurities. The activation of regrown p-GaN in deep trenches is more difficult than planar p-GaN, and we present the characterization and physical model for the activation of the deep buried p-GaN. Last, the results of p-GaN filling regrowth and the acceptor concentration calibration in the lightly doped p-GaN are presented and discussed. In summary, our work combines experimental device fabrication and characterization, TCAD simulation, and device modeling to demonstrate the benefit of multi-dimensional, junction-based GaN power devices as compared to the traditional GaN power devices. The junction-based structure at gate region can provides stable normally-off operation and low on-resistance. When being applied to the drift region, the multidimensional junction structure can push the device specific on-resistance versus breakdown voltage trade-off near or even exceeding the material limit. These results will advance the performance and application spaces of GaN power devices. / Doctor of Philosophy / Power electronics plays an important role in many energy conversion applications in modern society including consumer electronics, data centers, electric vehicles, and power grids, etc. The key components of power electronic circuits are power semiconductor devices including diodes and transistors, which determine the performance of power electronics circuits. Traditional power devices are based on the semiconductor silicon (Si), which have already reached the silicon's material limit. Gallium nitride (GaN) is a wide bandgap semiconductor with high electron mobility and high critical electric field. GaN-based power devices promise superior device performance over the Si-based counterpart. Currently, GaN power devices performance is still far below its material limit due to several reasons: 1) To achieve normally-off operation, the carriers at gate region need to be fully depleted at zero bias. Due to a relatively limited depletion capability of the planar gate, the normally-off operation poses an upper limit on the channel carrier density, which increases the device on-resistance. 2) The electric field distribution is not uniform when the device is blocking off-state voltage, and the crowded electric field will cause the device premature breakdown. This work proposed to use multi-dimensional, p-n junction-based device structure to overcome the above challenges. The devices with diverse structures are fabricated, characterized, and compared with the commercially available devices. The multi-dimensional, junction-based gate structure provides strong electrostatic control to realize normally-off operation and allow for higher carrier concentration and lower on-resistance. The devices with multi-dimensional, junction-based drift region enables the uniform electric field distribution at the device off-state, allowing devices to block high voltage without compromising the on-state resistance. Examples of such devices investigated in this dissertation include the tri-gate junction transistors, reduced-surface-field (RESURF) diodes, and superjunction diodes. In summary, this work demonstrates the multi-dimensional, junction-based device structure to overcome the performance limitations of planar devices and fully exploit GaN's material benefits for power devices. The multi-dimensional, junction-based devices are experimentally fabricated and characterized, manifesting the superior performance over traditional GaN devices. This work will significantly boost the performance and application space of GaN power devices.

State-of-the-art silicon-based power supplies have reached a point of maturity in performance. Efficiency, power density, and cost are major trade-offs involved in further improvements. Most products are custom designed with significant non-recurrent engineering and manufacturing processes that are labor intensive. In particular, conventional magnetic components, including transformers and inductors, have largely remained the same for the past five decades. Those large and bulky magnetic components are major roadblocks toward an automated manufacturing process. In addition, there is no specific approach to reduce electromagnetic interference (EMI) in conventional practices. In certain cases, EMI filter design even requires a trial-and-error process. With recent advances in wide-bandgap (WBG) power semiconductor devices, namely, SiC and GaN, we have witnessed significant improvements in efficiency and power density, compared to their silicon counterparts. In a power factor correction (PFC) rectifier/inverter, the totem-pole configuration with critical conduction mode (CRM) operation to realize zero-voltage switching (ZVS) is deemed most desirable for a switching frequency 10 times higher than current practice. With a significantly higher operating frequency, the integration of inductors with embedded windings in the printed circuit board (PCB) is feasible. However, a PCB winding-based inductor has a fundamental limitation in terms of its power handling capability. The winding loss is proportional to the magnetomotive force (MMF), which is Ni. That is to say, with the number of layers (turns) and currents increased, winding loss is increased nonlinearly. Furthermore, for a large-size planar inductor, flux distribution is usually non-uniform, resulting in dramatically increased hysteresis loss and eddy loss. Thus, current designs are challenged by the capability to increase their power range. To address those issues, a modular building block approach is proposed in this dissertation. A planar PCB inductor is formed by an array of pillars that are integrated into one magnetic core, where each pillar handles roughly 750 W of power. The winding loss is reduced by limiting the number of turns for each pillar. The core loss is minimized with a proposed planar magnetic structure where rather uniformly distributed fluxes were observed in the plates. The proposed approach has a similar loss to a conventional litz wire-based design but features a higher power density and can be easily assembled in automation. A 3 kW high frequency PFC converter with 99% efficiency is demonstrated as an example. Furthermore, PCB-based designs up to 6 kW are provided. Another challenge in a WBG-based PFC/inverter is the high common-mode (CM) noises associated with the high dv/dt of the WBG devices. Symmetry and cancellation techniques are often employed to suppress CM noises in switching power converters. Meanwhile, shielding technique has been demonstrated to effectively suppress CM noises in an isolated converter with PCB-based transformer design. However, for non-isolated converters, such as PFC circuits, none of the techniques mentioned above are deemed applicable or justifiable. Recently, the balance technique has been demonstrated to effectively suppress CM noises up to a point where the parasitic ringing between the inductor and its winding capacitor is observed. This dissertation presents an improved balance technique in a PCB-based coupled inductor design that compensates for the detrimental effect of the interwinding capacitors. A CM noise model is established to simplify the convoluted couplings into a decoupled representation so as to illustrate the necessary conditions for realizing a balanced network. In the given 1 kW PFC example, CM noise suppression is effective in the frequency range of interest up to 30 MHz. The parasitic oscillation of inductors, known to be detrimental for CM noise reduction, is circumvented with the improved magnetic structure. By applying the balance technique to a PFC converter and the shielding technique to an LLC DC/DC converter, significant noise reductions were realized. This provides the opportunity to use a simple one-stage EMI filter to achieve the required EMI noise attenuation for a server power supply. This dissertation further offers an in-depth study on reducing the unwanted near-field couplings between the CM/DM inductors and DM filter capacitors, as well as unwanted self-parasitics such as the ESL of the DM capacitors. An exhaustive finite element analysis (FEA) and near field measurements are conducted to better understand the effect of frequency on the polarization of the near field due to the displacement current. The knowledge gained in this study enables one to minimize unwanted mutual coupling effects by means of physical placement of these filter components. Thus, for the first time, a single-stage EMI filter is demonstrated to meet the EMI standard in an off-line 1 kW, 12 V server power supply. With the academic contributions in this dissertation, a PCB winding-based inductor can be successfully applied to a high-frequency PFC/inverter to achieve high efficiency, high power density, automation in manufacturing, lower EMI, and lower cost. Suffice it to say, the proposed approach enables a paradigm shift in the designing and manufacturing of a PFC/inverter for the next generation of power supplies. / Doctor of Philosophy / State-of-the-art silicon device-based switching power supplies have reached a point of maturity in performance. Efficiency, power density, and cost are major trade-offs involved in performance improvements. Most products are custom designed, requiring significant non-recurrent engineering and labor-intensive manufacturing processes. In particular, conventional magnetic components, including transformers and inductors, have largely remained the same for the past five decades. Those large and bulky magnetic components are major roadblocks toward an automated manufacturing process. In addition, there is no specific approach to reduce electromagnetic interference (EMI) in conventional practices. In consequence, a large multi-stage EMI filter is usually adopted between the power converter and the grid to reduce the EMI noise. It generally occupies 1/4-1/3 of the total converter volume. In certain cases, EMI filter design even requires a trial-and-error process. Suffice it to say, EMI is still regarded as both science and art. With recent advances in wide-bandgap (WBG) power semiconductor devices, namely, SiC and GaN, we have witnessed significant improvements in efficiency and power density, compared to their silicon counterparts. With GaN devices, the switching frequency of a PFC converter is able to be increased by 10 times compared to the state-of-the-art design without compromising efficiency. With a significantly higher operating frequency, the integration of inductors with embedded windings in the printed circuit board (PCB) is feasible. However, the state-of-the-art PCB winding-based inductor has a fundamental limitation in power range. Its winding loss and core loss increase dramatically in high powers. To address this issue, a modular building block approach is proposed in this dissertation. A planar PCB inductor is formed by an array of pillars that are integrated into one magnetic core, where each pillar handles roughly 750 W of power. The winding loss is reduced by limiting the number of turns for each pillar. The core loss is minimized with a proposed planar magnetic structure where rather uniformly distributed fluxes have been observed in the magnetic core plates. A 3 kW high-frequency PFC converter with a 99% peak efficiency is demonstrated as an example. Furthermore, PCB-based designs up to 6 kW are provided. Another challenge in a WBG-based PFC/inverter is the high common-mode (CM) noises caused by the high switching speed of the WBG devices. Symmetry and cancellation techniques are often employed to suppress CM noises in switching power converters. Meanwhile, shielding technique has been demonstrated to effectively suppress CM noises in an isolated converter with PCB-based transformer. However, for non-isolated converters, such as PFC circuits, none of the techniques mentioned above are deemed applicable or justifiable. Recently, the balance technique has been demonstrated to effectively suppress CM noises up to several MHz. However, the CM noise reduction is not effective beyond that. This dissertation presents an improved balance technique in a PCB-based coupled inductor to circumvent the limits. In the given 1 kW PFC example, CM noise suppression is effective in the frequency range of interest up to 30 MHz. By applying the balance technique to a PFC converter and the shielding technique to an LLC DC/DC converter, significant noise reductions were realized. This provides the opportunity to use a simple one-stage EMI filter to achieve the required EMI noise attenuation for a server power supply. It features a smaller volume compared to a conventional multi-stage filter. To further enhance the filter's performance at high frequencies, an exhaustive finite element analysis and near field measurements are conducted to better understand the effect of frequency on the polarization of the near field due to the displacement current. The knowledge gained in this study enables one to minimize unwanted mutual coupling effects through physical placement of these filter components. Several approaches for improving the filter performance at high frequency are conducted. With these approaches applied, a single-stage filter is demonstrated in an off-line 1 kW, 12 V server power supply. Thus, for the first time, a single-stage EMI filter can be contemplated to meet the EMI standard in server power supplies. With the academic contributions in this dissertation, a PCB-winding based inductor can be successfully applied to a high-frequency PFC/inverter to achieve high efficiency, high power density, automation in manufacturing, lower EMI, and lower cost. Suffice it to say, the proposed approach in this work enables a paradigm shift in the designing and manufacturing of a PFC/inverter for the next generation of power supplies.

Interest in wide bandgap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ) and diamond has increased due to their ability to deliver high power, high switching frequency and low loss electronic devices for power conversion applications. To meet these requirements, semiconductor material defects, introduced during growth and fabrication, must be minimized. Otherwise, theoretical limits of operation cannot be achieved. In this dissertation, the non-ideal current- voltage (IV) behavior of GaN-based Schottky diodes is discussed first. Here, a new model is developed to explain better the temperature dependent performance typically associated with a multi-Gaussian distribution of barrier heights at the metal-semiconductor interface [Section 3.1]. Application of this model gives researches a means of understanding not only the effective barrier distribution at the MS interface but also its voltage dependence. With this information, the consequence that material growth and device fabrication methods have on the electrical characteristics can be better understood. To show its applicability, the new model is applied to Ru/GaN Schottky diodes annealed at increasing temperature under normal laboratory air, revealing that the origin of excess reverse leakage current is attributed to the low-side inhomogeneous barrier distribution tail [Section 3.2]. Secondly, challenges encountered during MOCVD growth of low-doped GaN drift layers for high-voltage operation are discussed with focus given to ongoing research characterizing deep-level defect incorporation by deep level transient spectroscopy (DLTS) and deep level optical spectroscopy (DLOS) [Section 3.3 and 3.4]. It is shown that simply increasing TMGa so that high growth rates (>4 µm/hr) can be achieved will cause the free carrier concentration and the electron mobilities in grown drift layers to decrease. Upon examination of the deep-level defect concentrations, it is found that this is likely caused by an increase in 4 deep level defects states located at E C - 2.30, 2.70, 2.90 and 3.20 eV. Finally, samples where the ammonia molar flow rate is increased while ensuring growth rate is kept at 2 µm/hr, the concentrations of the deep levels located at 0.62, 2.60, and 2.82 eV below the conduction band can be effectively lowered. This accomplishment marks an exciting new means by which the intrinsic impurity concentration in MOCVD-grown GaN films can be reduced so that >20 kV capable devices could be achieved. / Doctor of Philosophy / We constantly rely on electronics to help assist us in our everyday lives. However, to ensure functionality we require that they minimize the amount of energy lost through heat during operation. One contribution to this inefficiency is incurred during electrical power conversion. Examples of power conversion include converting from the 120 V wall outlet to the 5 V charging voltage used by cellphones or converting the fluctuating voltage from a solar panel (due to varying sun exposure) to the 120 V AC power found in a typical household. Electrical circuits can be simply designed to accomplish these conversions; however, consideration to every component must be given to ensure high efficiency. A popular example of an electrical power conversion circuit is one that switches the input voltage on and off at high rates and smooths the output with an inductor/capacitor network. A good analogy of this process is trying to create a small stream of water from a fire hydrant which can either be off or on at full power. Here we can use a small cup but turning the fire hydrant on and trying to fill the cup will destroy it. However, if the fire hydrant is pulsed on and off at very short intervals (1 µs), its possible to fill the cup without damaging it or having it overflow. Now, under ideal circumstances if a small hole is poked in the bottom of the cup and the interval of the fire hydrant is timed correctly, a small low power stream of water is created without overflowing the cup and wasting water. In this analogy, a devices capable of switching the stream of water on and off very fast would need to be implemented. In electrical power conversion circuits this device is typically a transistor and diode network created from a semiconducting material. Here, similar to the fire hydrant analogy, a switch would need to be capable of holding off the immense power when in the off position and not impeding the powerful flow when in the on position. The theoretical limit of these two characteristics is dependent on the material properties of the switch where typically used semiconductors include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). Currently, GaN is considered to be a superior option over Si or SiC to make the power semiconductor switching device, however research is still required to remove non-ideal behavior that ultimately effects power conversion efficiency. In this work, we first examine the spurious behavior in GaN-based Schottky diodes and effectively create a new model to describe the observed behavior. Next, we fabricated Ru/GaN Schottky diodes annealed at different temperatures and applied the model to explain the room-temperature electrical characteristics. Finally, we grew GaN under different conditions (varying TMGa and ammonia) so that quantum characteristics, which have been shown to affect the overall ability of the device, could be measured.

Efficient and robust blue InGaN multiple quantum well (MQW) light emitters have become ubiquitous; however, they still have unattained theoretical potential. It is widely accepted that “localization” of carriers due to indium fluctuations theoretically enhance their efficiency by moderating defect-associated nonradiative recombination. To help develop a complete understanding of localization effects on carrier dynamics, this thesis explores degree of localization in InGaN MQWs and its dependence on well thickness and number of wells, through temperature and power dependent photoluminescence measurements. Additionally, silicon-compatible, nontoxic, colloidally synthesizable 2-5 nm Ge1-xSnx alloy quantum-dots (QDs) are explored for potential visible to near-IR optoelectronic applications. While bulk Ge is an indirect gap material, QD confinement allows enhanced direct transitions, and alloying with Sn improves transition oscillator strengths. Temperature dependent steady-state and time-resolved photoluminescence reveal relaxation pathways involving bright/dark excitons and surface states in Ge1-xSnx QDs, showing their great potential for future use.

Diamond is a semiconductor with many superior material properties such as high breakdown field, high saturation velocity, high carrier mobilities and the highest thermal conductivity of all materials. These extreme properties, as compared to other (wide bandgap) semiconductors, make it desirable to develop single-crystalline epitaxial diamond films for electronic device and detector applications. Future diamond devices, such as power diodes, photoconductive switches and high-frequency field effect transistors, could in principle deliver outstanding performance due to diamond's excellent intrinsic properties. However, such electronic applications put severe demands on the crystalline quality of the material. Many fundamental electronic properties of diamond are still poorly understood, which severely holds back diamond-based electronic device and detector development. This problem is largely due to incomplete knowledge of the defects in the material and due to a lack of understanding of how these defects influence transport properties. Since diamond lacks a shallow dopant that is fully thermally activated at room temperature, the conventional silicon semiconductor technology cannot be transferred to diamond devices; instead, new concepts have to be developed. Some of the more promising device concepts contain thin delta-doped layers with a very high dopant concentration, which are fully activated in conjunction with undoped (intrinsic) layers where charges are transported. Thus, it is crucial to better understand transport in high-quality undoped layers with high carrier mobilities. The focus of this doctoral thesis is therefore the study of charge transport and related electronic properties of single-crystalline plasma-deposited (SC-CVD) diamond samples, in order to improve knowledge on charge creation and transport mechanisms. Fundamental characteristics such as drift mobilities, compensation ratios and average pair-creation energy were measured. Comparing them with theoretical predictions from simulations allows for verification of these models and improvement of the diamond deposition process.

abstract: The dissertation encompasses the transformer-less single phase PV inverters for both the string and microinverter applications. Two of the major challenge with such inverters include the presence of high-frequency common mode leakage current and double line frequency power decoupling with reliable capacitors without compromising converter power density. Two solutions are presented in this dissertation: half-bridge voltage swing (HBVS) and dynamic dc link (DDCL) inverters both of which completely eliminates the ground current through topological improvement. In addition, through active power decoupling technique, the capacitance requirement is reduced for both, thus achieving an all film-capacitor based solution with higher reliability. Also both the approaches are capable of supporting a wide range of power factor. Moreover, wide band-gap devices (both SiC and GaN) are used for implementing their hardware prototypes. It enables the switching frequency to be high without compromising on the converter efficiency. Also it allows a reduced magnetic component size, further enabling a high power density solution, with power density far beyond the state-of-the art solutions. Additionally, for the transformer-less microinverter application, another challenge is to achieve a very high gain DC-DC stage with a simultaneous high conversion efficiency. An extended duty ratio (EDR) boost converter which is a hybrid of switched capacitors and interleaved inductor technique, has been implemented for this purpose. It offers higher converter efficiency as most of the switches encounter lower voltage stress directly impacting switching loss; the input current being shared among all the interleaved converters (inherent sharing only in a limited duty ratio), the inductor conduction loss is reduced by a factor of the number of phases. Further, the EDR boost converter has been studied for both discontinuous conduction mode (DCM) operations and operations with wide input/output voltage range in continuous conduction mode (CCM). A current sharing between its interleaved input phases is studied in detail to show that inherent sharing is possible for only in a limited duty ratio span, and modification of the duty ratio scheme is proposed to ensure equal current sharing over all the operating range for 3 phase EDR boost. All the analysis are validated with experimental results. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

Ce travail de thèse porte sur la diffusion des porteurs de charge en excès dans deux semiconducteurs à large bande interdite: l’alliage ZnMgO et le diamant 13C. Il est basé sur l’étude d’hétérostructures ZnMgO/ZnO/ZnMgO et 13C/12C/13C à puits de collecte ZnO ou 12C. Sur leurs sections transverses et avec la résolution nanométrique en excitation par cathodoluminescence (CL), nous avons étudié l’évolution de l’intensité de l’émission issue du puits en ZnO ou 12C en fonction de la distance entre l’impact de l’excitation et le puits. Cela nous a permis de mesurer directement les longueurs de diffusion effectives dans ZnMgO et le diamant.Dans ZnMgO, la valeur de 55 nm à 300 K, mesurée sur section transverse clivée, est proche de celle du matériau massif. Elle correspond à une diffusion mixte excitons/porteurs libres. Avec l’utilisation de lames minces érodées par faisceau d’ions, une diminution de a été observée jusqu’à 8 nm dans les parties les plus fines. Cet effet est attribué aux recombinaisons non radiatives de surface. Les lames minces apparaissent alors d’un grand intérêt pour améliorer la résolution spatiale des images CL.Dans le diamant, la diffusion excitonique à basse température montre une faible dépendance de avec l’énergie incidente des électrons. Cela indique que ≈ 15 µm à 20 K dans le diamant massif 13C. Une diminution de jusqu’à 3,3 µm à 118 K est observée en fonction de la température.Enfin, nous avons mis en évidence la formation de polyexcitons dans le diamant en augmentant la densité des paires électron-trou, soit par la puissance d’excitation, soit par le confinement spatial des excitons dans des puits de diamant 12C de faible épaisseurs. / This work focuses on the determination of the carrier diffusion length in two wide bandgap semiconductors: the ternary alloy ZnMgO and diamond. This determination has been achieved by using of ZnMgO/ZnO/ZnMgO and 13C/12C/13C heterostructures containing ZnO or 12C collecting wells. Their transverse section was scanned by CL spectroscopy with a nanometer scale resolution in excitation. The effective excess carrier diffusion length is deduced from the evolution of the well emission intensity with the distance between the excitation impact and the well.In ZnMgO, the value at 300 K is 55 nm, obtained from a cleaved cross section. It is close to the bulk material diffusion and is attributed to a mixed diffusion of excitons/free carriers. A decrease of down to 8 nm is observed in the thinnest portions of cross sections shaped by focused ion beam (FIB). This effect is attributed to non-radiative surface recombinations. These thin slabs appear of great interest to enhance the spatial resolution of CL images.In diamond, the exciton diffusion at 20 K exhibits a slight dependence on the incident electron energy. This indicates that the exciton diffusion length is around 15 µm in 13C bulk diamond. The values decrease down to 3.3 µm at 118 K.Finally, we highlighted the formation of polyexcitons in diamond by increasing the electron-hole pairs density either by the excitation power, or by the spatial confinement of excitons in thin 12C wells.