Thin-film transistors (TFTs) capable of low-voltage and high-frequency operation will be required to reduce the power consumption of next generation electronic devices driven by microelectronic components such as inverters, ring oscillators, and backplane circuits for mobile displays. To produce high performance TFTs, transparent oxide-semiconductors are becoming an attractive alternative to hydrogenated amorphous silicon (a-Si:H)- and organic-based materials because of their high electron mobility vlaues and low processing temperatures, making them compatible with flexible substrates and opening the potential for low production costs. Practical electronic devices are expected to use p- and n-channel TFT-based complementary inverters to operate with low power consumption, high gain values, and high and balanced noise margins. The p- and n-channel TFTs should yield comparable output characteristics despite differences in the materials used to achieve such performance. However, most oxide semiconductors are n-type, and the only high performance, oxide-based TFTs demonstrated so far are all n-channel, which prevents the realization of complementary metal-oxide-semiconductor (CMOS) technologies. On the other hand, ambipolar TFTs are very attractive microelectronic devices because, unlike unipolar transistors, they operate independently of the polarity of the gate voltage. This intrinsic property of ambipolar TFTs has the potential to lead to new paradigms in the design of analog and digital circuits. To date, ambipolar TFTs and their circuits, such as inverters, have shown very limited performance when compared with that obtained in unipolar TFTs. For instance, the electron and hole mobilities typically found in ambipolar TFTs (ATFTs) are, typically, at least an order of magnitude smaller than those found in unipolar TFTs. Furthermore, for a variety of circuits, ATFTs should provide balanced currents during p- and n-channel operations. Regardless of the selection of materials, achieving these basic transistor properties is a very challenging task with the use of current device geometries. This dissertation presents research work performed on oxide TFTs, oxide TFT-based electronic circuits, organic-inorganic hybrid complementary inverters, organic-inorganic hybrid ambipolar TFTs, and ambipolar TFT-based complementary-like inverters in an attempt to overcome some of the current issues. The research performed first was to develop low-voltage and high-performance oxide TFTs, with an emphasis on n-channel oxide TFTs, using high-k and/or thin dielectrics as gate insulators. A high mobility electron transporting semiconductor, amorphous indium gallium zinc oxide (a-IGZO), was used as the n-channel active material. Such oxide TFTs were employed to demonstrate active matrix organic light emitting diode (AMOLED) display backplane circuits operating at low voltage. Then, high-performance hybrid complementary inverters were developed using unipolar TFTs employing organic and inorganic semiconductors as p- and n-channel layers, respectively. An inorganic a-IGZO and pentacene, a widely used organic semiconductor, were used as the n- and p-channel semiconductors, respectively. By the integration of the p-channel organic and n-channel inorganic TFTs, high-gain complementary inverters with high and balanced noise margins were developed. A new approach to find the switching threshold voltage and the optimum value of the supply voltage to operate a complementary inverter was also proposed. Furthermore, we proposed a co-planar channel geometry for the realization of high-performance ambipolar TFTs. Using non-overlapping horizontal channels of pentacene and a-IGZO, we demonstrate hybrid organic-inorganic ambipolar TFTs with channels that show electrical properties comparable to those found in unipolar TFTs with the same channel aspect ratios. A key characteristic of this co-planar channel ambipolar TFT geometry is that the onset of ambipolar operation is mediated by a new operating regime where one of the channels can reach saturation while the other channel remains off. This allows these ambipolar TFTs to reach high on-off current ratios approaching 104. With the new design flexibility we demonstrated organic-inorganic hybrid ambipolar TFT-based complementary-like inverters, on rigid and flexible substrates, that show a significant improvement over the performance found in previously reported complementary-like inverters. From a materials perspective, this work shows that future breakthroughs in the performance of unipolar n-channel and p-channel semiconductors could be directly transposed into ambipolar transistors and circuits. Hence, we expect that this geometry will provide new strategies for the realization of high-performance ambipolar TFTs and novel ambipolar microelectronic circuits.

Avatrel 8000P's excellent photo-definition properties and mechanical strength make it an ideal polymer collar material. Avatrel 8000P is a high contrast, I-line sensitive mixture that can be developed in traditional aqueous-base developers. The great photolithographical performance of this photopolymer can be partly contributed to the minimal amount of light absorbed by the base norbornene polymer. The processing conditions noted in this work are an optimized version, which have been shown to give superior photolithographical performance. The simple baking procedures make Avatrel 8000P easier to process than SU-8. The ability to develop Avatrel 8000P in aqueous base can reduce chemical waste. As shown by SEM images, high fidelity structures with aspect ratios of 7:1 can be fabricated in thick films with vertical sidewalls. Bonding between two copper surfaces over various gap sizes was achieved by electroless deposition without the addition of surfactants or inhibitors in the bath. The effect of anneal temperature on the electroless bond formed was analyzed. The electroless bond strength increased with anneal temperature. However, the bond strength estimation for samples annealed at 80°C to 120°C is a minimum value due to the failure location of most of the pillars and the resulting area used in the calculation of bond strength. Grain growth from copper recrystallization and removal of small defects improve the bond strength. Large voids at the interface of the two pillars were related to rough starting surfaces for the electroplated pillars.

The work presented in this thesis shows how tunneling spectroscopy techniques can be applied to metallic nanoparticles to obtain useful information about fundamental physical processes in nanoscopic length scales. At low temperatures, the discrete character of the energy spectrum of these particles, allows the study of spin-polarized current via resolved "electron-in-a-box" energy levels. In samples consisting of two ferromagnetic electrodes tunnel coupled to single aluminum nanoparticles, spin accumulation mechanisms are responsible for the observed spin-polarized current. The observed effect of an applied perpendicular magnetic field, relative to the magnetization orientation of the electrodes, indicates the suppression of spin precession in such small particles. More generally, in the presence of an external non-collinear magnetic field, it is the local field "felt" by the particle that determines the character of the tunnel current. This effect is also observed in the case where only one of the electrodes is ferromagnetic. In contrast to the non-magnetic case, ferromagnetic nanoparticles exhibit a much more complex energy spectrum, which cannot be accounted for, using the simple free-electron picture. It will be shown that interactions between quasi-particle excitations due to sequential electron tunneling and spin excitations in the particle are likely to play an important role in the observed temperature/voltage dependence of magnetic hysteresis loops.

The mechanical reliability of electronic components has become harder and harder to predict due to the use of composite materials. One of the key issues is creating an accurate model of the delamination mechanism, which consists in the separation of two different bounded materials. This phenomenon is a very challenging issue that is investigated in the Nano Interface Project (NIP), in which this thesis is involved. The macroscopic adhesion force is governed by several parameters described at different length scales. Among these parameters, the roughness profile of the interface has a pronounced influence. The main difficulty for an accurate delamination characterization is then investigating the effects of this roughness profile and the modifications it implies for the overall cohesion. The objective of the NIP is to develop an interface model for the numerical testing of electronic components in a finite element software. The problem is that a direct modeling of all the mechanisms described previously is really expensive in term of computation time, if possible at all. This difficulty is increased by the huge mismatch of the mechanical properties of the materials in contact. A scale transition method is therefore required, which is provided by homogenization. The idea is to consider the delamination at a wider scale. Rather than modeling the whole roughness profile, the adhesion at the interface will be described by homogenized, or macroscopic, parameters extracted from a representative model at the micro-scale, the RVE. This thesis will deal with the determination of these homogenized parameters.

Fracture of polymer-metal interfaces is one of the main failure modes occurring in micro-electronic components. This phenomenon is particularly true when considering the delamination of several layers of an interconnect structure. In order to predict the failure nucleation and the crack propagation into the composite material, the finite element analysis is one of the key procedures. Even though simple linear models have been considered for years, we are now facing the necessity of using more complex models including non-linearity which can occur, in this case, with the presence of high local stresses near the crack front. However, the computational time can sometimes be incredibly long. Moreover, the fact that the considered materials are quasi-brittle brings some numerical difficulties such as sharp snap-back and snap-through. The actual challenge resides in obtaining a reliable result in a reasonable time of calculation. The present work considers the implementation of a new non-linear finite element solver, developed for the MSc. Marc/Mentat package software. It is based on a general arc-length constraint which considers the energy released during the propagation of the crack. This offers the advantage of being directly linked to the failure process, and no previous knowledge of the failure behavior is required. The models considered in this work represent the simulation of crack propagations in multilayer electronic systems, such as SIP devices, and are based on a cohesive zone approach. In order to clearly understand the issues of this problem, this work includes a brief description of the fracture mechanics and reviews the existing nonlinear finite element solvers. After explaining the principle of the energy release solver and the different issues due to its implementation, its efficiency is compared to pre-implemented solvers, such as the Crisfield method. The results show a significant improved robustness of the new energy released method compared to the previous arc-length methods.

The goal of the research in this dissertation is to develop techniques for 1) system-on-package integration of passive circuits using ultra-thin advanced polymers called RXP (Rogers experimental polymer), 2) extraction of frequency-dependent material properties up to millimeter-wave frequency, 3) development and synthesis of high-rejection filter topologies, 4) design and characterization of high performance miniaturized embedded passive circuits for microwave and millimeter-wave applications, and 5) development of via and through-silicon via (TSV) enhanced filter design method for integration in high-loss substrate. The RXP material is developed to reduce the layer-count for multi-layer configuration and adoption of advanced fabrication technologies. Frequency-dependent material properties of RXP, ceramic, and other materials have been extracted up to millimeter-wave frequency using parallel-plate resonator method. An automated extraction algorithm has been proposed to handle a large number of frequency samples efficiently. The accuracy of the extraction result has been improved by including the surface roughness effect for conductor operating at high frequency. Using extracted RXP material properties, 2.4/5 GHz WLAN bandpass filters have been designed and characterized. High-rejection bandpass filter topologies for narrow 2.4 GHz and wide 5 GHz have been proposed. The proposed topologies have been synthesized to provide design equations as well as graphical design methodologies using Z-parameters. A new capacitor design called 3D stitched capacitor has been proposed to achieve more symmetric layout by providing balanced shunt parasitics. The proposed topologies and design methodologies have been verified through the measurement of high-rejection RXP bandpass filters. Good correlation between the simulation and measurement was observed demonstrating an effective design methodology and embedding bandpass filters with good performance. Dual-band bandpass filters for WLAN applications have been implemented and measured. Instead of connecting two bandpass filter circuits, a new single bandpass filter topology has been developed with a compact size as well as high isolation between passbands. High-rejection duplexer has been designed in RXP substrate for chip-last embedded IC technology, and a novel matching circuit has been applied for the miniaturization as well. The 60 GHz V-band has special interest for wireless applications because of its high attenuation characteristics because of atmospheric oxygen. Millimeter-wave passive circuits such as bandpass filter, dual-band filter, and duplexer have been designed, and self-resonant frequency of passive components has been carefully avoided using the proposed method. For low-cost system integration, silicon interposer with through-silicon-via (TSV) technology has been studied. The filter design method for high-loss substrate has been proposed. The coupling characteristic of TSV has been investigated for obtaining good insertion loss in lossy substrates such as silicon, and TSV characteristics has been used to design bandpass and highpass filters. To demonstration of concept, bandpass filters with good insertion loss have been realized on high-loss FR4 substrate.

In conventional design of power delivery networks (PDNs), the PDN impedance is required to be less than the target impedance over the frequency range of interest to minimize the IR drop and to suppress the inductive noise during data transitions. As a result, most PDNs in high-speed systems consist of power and ground planes to provide a low-impedance path between the voltage regulator module (VRM) and the integrated circuit (IC) on the printed circuit board (PCB). For off-chip signaling, charging and discharging signal transmission lines induce return currents on the power and ground planes. The return current always follows the path of least impedance on the reference plane closest to the signal transmission line. The return current path plays a critical role in maintaining the signal integrity of the bits propagating on the signal transmission lines. The problem is that the disruption between the power and ground planes induces return path discontinuities (RPDs), which create displacement current sources between the power and ground planes. The current sources excite the plane cavity and cause voltage fluctuations. These fluctuations are proportional to the plane impedance since the current is drawn through the PDN by the driver. Therefore, low PDN impedance is required for power supply noise reduction. Alternatively, methods of preventing RPDs can be used to suppress power supply noise. Using a power transmission line (PTL) eliminates the discontinuity between the power and ground planes, thereby preventing the RPD effects. In this approach, transmission lines replace the power plane for conveying power from the VRM to each IC on the PCB. The PTL-based PDN enables both power and signal transmission lines to be referenced to the same ground plane so that a continuous current path can be formed, unlike the power-plane-based PDN. As a result, a closed current loop is achieved, and the voltage fluctuation caused by RPDs is removed in idealistic situations. Without the RPD-related voltage fluctuation, reducing the PDN impedance is not as critical as in the power-plane-based approach. Instead, the impedance of the PTL is determined by the impedance of the signaling circuits. To use the PTL-based PDN in a practical signaling environment, several issues need to be solved. First, the dc drop coming from the source termination of the PTL needs to be addressed. The driver being turned on and off dictates the current flow through the PTL, causing the dc drop to be dynamic, which depends on the data pattern. Second, impedance mismatch between the PTL and termination can occur due to manufacturing variations. Third, an increase in the number of PCB traces should be addressed by devising a method to feed more than one driver with one PTL. Lastly, the power required to transmit 1 bit of data should be optimized for the PTL by using a new signaling scheme and adjusting the impedance of the signaling circuit. Constant flow of current through the PDN is one solution proposed to address the first two issues. Constant current removes the dynamic characteristics of the dc drop by inducing a fixed amount of dc drop over the PTL. Moreover, constant current keeps the PTL fully charged at all times, and thereby eliminates the process of repeatedly charging and discharging the power transmission line. The constant current PTL (CCPTL) scheme maintains constant current flow regardless of the input data pattern. Early results on the CCPTL scheme have been discussed along with the measurements. The CCPTL scheme severs the link between the current flowing through the PTL and the output data of the I/O driver connected to it. Also, it eliminates the charging and discharging process of the PTL, thereby completely eliminating power supply noise in idealistic situations. To reduce any associated power penalty, a pseudo-balanced PTL (PBPTL) scheme is also proposed using the PTL concept. A pseudo-balanced (PB) signaling scheme, which uses an encoding technique to map N-bit data onto M-bit encoded data with fixed number of 1s and 0s, is applied. When the PB signaling scheme is combined with the PTL, the jitter performance improves significantly as compared to currently practiced design approach.

Fluoride-containing solutions are widely used to etch silicon dioxide-based films. A critical issue in integrated circuit (IC) and microelectromechanical systems (MEMS) fabrication is achievement of adequate selectivity during the etching of different film materials when they are present in different areas on a device or in a stack. The use of organic fluoride-based salts in aqueous/organic solvent solutions can yield etch selectivities <1.9 for thermally-grown silicon dioxide relative to borophosphosilicate glass films, and thus may also obviate the need to add surfactants to the etch solutions to realize uniform etching. Etch studies with aqueous-organic fluoride salt-based solutions also offer insight into the etch mechanism of these materials. Specifically, the importance of water content in the solutions and of ion solvation in controlling the etch chemistry is described. With respect to fluoride-containing solutions, etching of SiO₂ films using aqueous HF-based chemistries is widely used in IC and MEMS industries. To precisely control film loss during cleaning or etching processes, good control over the contact time between the liquid (wet) chemistry and the substrate is necessary. An integrated wet etch and dry reactor system has been designed and fabricated by studying various geometrical configurations using computational fluid dynamics (CFD) simulations incorporating reaction kinetics from laboratory data and previously published information. The effect of various process parameters such as HF concentration, flow rate, and flow velocity on the etch rates and uniformity of thermally-grown silicon dioxide and borophosphosilicate glass films was studied. Simulations agree with experiments within experimental error. This reactor can also be used to wet etch/clean and dry other films in addition to SiO₂-based films using aggressive chemistries as well as aqueous HF under widely different process conditions. A spectroscopic reflectometry technique has been implemented in-situ in this custom fabricated reactor to monitor the thickness and etch rate in wet etching environments. The advantages of this technique over spectroscopic ellipsometry in specific situations are discussed. A first principles model has been developed to analyze the reflectometry data. The model has been validated on a large number of previously published studies. The match between experimental and simulated thickness is good, with the difference ~ 5 nm. In-situ thickness and etch rate have been estimated using Recursive Least Squares (RLS), Extended Kalman Filter (EKF) and modified Moving Horizon Estimator (mMHE) analyses applied to spectroscopic reflectometry using multiple wavelengths with ZnO employed as a model film. The initial guess for EKF and mMHE has been obtained from a CFD model. It has been shown that both EKF and mMHE are less oscillatory than RLS/LS in the prediction of thickness and ER and more robust when a smaller number of wavelengths are used, in addition, the computational time for EKF is less than that of mMHE/RLS. For no restrictions on computational requirements, LS should be the method of choice whereas in the case of faster etching systems, with the availability of a better process model, EKF should be starting point. The choice of algorithm is thus based on sampling rate for data collection, process model uncertainty and the number of wavelengths required.

The need for post-CMOS nanoelectronics has led to the investigation of innovative device structures and materials. Graphene, a zero bandgap semiconductor with ballistic transport properties, has great potential to extend diversification and miniaturization beyond the limits of CMOS. The goal of this work is to study the growth of graphene on SiC using the novel method of selective graphitization. The major contributions of this research are as follows - First, epitaxial graphene is successfully grown on selected regions of SiC not capped by AlN deposited by molecular beam epitaxy. This contribution enables the formation of electronic-grade graphene in desired patterns without having to etch the graphene or expose it to any detrimental contact with external chemicals. Etching of AlN opens up windows to the SiC in desirable patterns for subsequent graphitization without leaving etch-residues (determined by XPS). Second, the impact of process parameters on the growth of graphene is investigated. Temperature, time, and argon pressure are the primary growth-conditions altered. A temperature of 1400oC in 1 mbar argon for 20 min produced the most optimal graphene growth without significant damage to the AlN capping-layer. Third, first-ever electronic transport measurements are achieved on the selective epitaxial graphene. Hall mobility of about 1550 cm2/Vs has been obtained to date. Finally, the critical limitations of the selective epitaxial graphene growth are enumerated. The advent of enhanced processing techniques that will overcome these limitations will create a multitude of opportunities for applications for graphene grown in this manner. It is envisaged to be a viable approach to fabrication of radio-frequency field-effect transistors.

Dans le but de réaliser des jonctions p/n monocristallines en diamant orienté selon {111}, des études ont été menées sur le substrat de diamant et sur les couches de diamant CVD dopées de type n au Phosphore et de type p au Bore. <br />Les défauts de surface et internes au substrat de diamant ont été analysés par des observations optiques, des mesures AFM et par des mesures en diffraction de rayons X. Les défauts dus au polissage de la surface du substrat ont en particulier été identifiés comme pouvant détériorer la qualité cristalline des couches CVD.<br />Un prétraitement par gravure RIE de la surface du substrat avant la croissance a été utilisé dans le but de supprimer les défauts induits par le polissage mécanique. Des paires d'échantillons dopés phosphore simultanément homoépitaxiés sur substrats non traités et prétraités RIE ont été caractérisées par cathodoluminescence et effet Hall. L'efficacité de la gravure de la surface du substrat a été prouvée par la diminution de l'émission de bande A reliée aux dislocations et par l'augmentation de la mobilité électronique de Hall pour les échantillons prétraités. Les données expérimentales ont été comparées à un modèle de mobilité basé sur l'approximation du temps de relaxation permettant de mettre en évidence la dépendance en température des différents modes de diffusion par les impuretés et les phonons ainsi que la détermination du potentiel de déformation acoustique du diamant de 17.7 eV. La valeur maximum de mobilité électronique possible à l'équilibre thermodynamique a ainsi pu être déterminée. Un nouveau mode de diffusion a été mis en évidence pour les échantillons non traités.<br />Les propriétés cristallines, optiques et électroniques d'une série de couches minces diamant CVD {111} couvrant une large gamme de dopage de 2x1015 à 3x1021 atomes de bore par cm3 ont été examinées en fonction de l'incorporation d'atomes dopants mesurés par SIMS.<br />Deux jonctions p/n, l'une réalisée sur un substrat fortement dopé bore, l'autre sur un substrat non dopé ont finalement été réalisées. Les caractéristiques I(V), les spectres de cathodoluminescence et d'électroluminescence et les résultats d'EBIC ont été comparés puis discutés.