Doctor of Philosophy / Department of Chemical Engineering / James H. Edgar / The integration of high-κ dielectrics with silicon and III-V semiconductors is important due to the need for high speed and high power electronic devices. The purpose of this research was to find the best conditions for fabricating high-κ dielectrics (oxides) on GaN or Si. In particular high-κ oxides can sustain the high breakdown electric field of GaN and utilize the excellent properties of GaN. This research developed an understanding of how process conditions impact the properties of high-κ dielectric on Si and GaN. Thermal and plasma-assisted atomic layer deposition (ALD) was employed to deposit TiO₂ on Si and Al₂O₃ on polar (c-plane) GaN at optimized temperatures of 200°C and 280°C respectively. The semiconductor surface treatment before ALD and the deposition temperature have a strong impact on the dielectric’s electrical properties, surface morphology, stoichiometry, and impurity concentration. Of several etches considered, cleaning the GaN with a piranha etch produced Al₂O₃/GaN MOS capacitors with the best electrical characteristics. The benefits of growing a native oxide of GaN by dry thermal oxidation before depositing the high-κ dielectric was also investigated; oxidizing at 850°C for 30 minutes resulted in the best dielectric-semiconductor interface quality. Interest in nonpolar (m-plane) GaN (due to its lack of strong polarization field) motivated an investigation into the temperature behavior of Al₂O₃/m-plane GaN MOS capacitors. Nonpolar GaN MOS capacitors exhibited a stable flatband voltage across the measured temperature range and demonstrated temperature-stable operation.

Doctor of Philosophy / Department of Chemical Engineering / James H. Edgar / Gallium nitride is a promising semiconductor for fabricating field effect transistors for power electronics because of its unique physical properties of wide energy band gap, high electron saturation velocity, high breakdown field and high thermal conductivity. However, these devices are extremely sensitive to the gate leakage current which reduces the breakdown voltage and the power-added efficiency and increases the noise figures. To solve this problem, employing a gate dielectric is crucial to the fabrication of metal insulator semiconductor high electron mobility transistors (MISHEMTs), to reduce the leakage current and increase the magnitude of voltage swings possible. For this device to be successful, imperfections at the oxide-semiconductor interface must be suppressed to maintain the high electron mobility of the device. This research explored multiple high dielectric constant gate oxides (Al[subscript]2O[subscript]3, TiO[subscript]2, and Ga[subscript]2O[subscript]3), deposited on different crystalline orientations and polarities of GaN by atomic layer deposition (ALD) to form metal oxide semiconductor capacitors, including effects of pretreatment on N-polar GaN, ALD TiO[subscript]2/Al[subscript]2O[subscript]3 nano-laminate on thermal oxidized Ga-polar GaN and ALD Al[subscript]2O[subscript]3 on [Italic]c- and [Italic]m-plane GaN Surface pretreatments were shown to greatly alter the morphology of reactive N-polar GaN which is detrimental to the electrical properties. 14 nm thick ALD Al[subscript]2O[subscript]3 films were directly deposited on N-polar GaN without thermal or chemical pretreatments which yield a smooth surface (RMS=0.23 nm), low leakage current (2.09 x 10[superscript]-[superscript]8 A/cm[superscript]2) and good Al[subscript]2O[subscript]3/GaN interface quality, as indicated by the low electron trap density (2.47 x 10[superscript]10 cm[superscript]-[superscript]2eV[superscript]-[superscript]1). In the nano-laminate study, a high dielectric constant of 12.5 was achieved by integrating a TiO[subscript]2/Al[subscript]2O[subscript]3/Ga[subscript]2O[subscript]3 oxide stack layer, while maintaining a low interface trap density and low leakage current. There was a strong correlation between the surface morphology and electrical properties of the device discovered from comparing the ALD Al[subscript]2O[subscript]3 on [Italic]c- and [Italic]m-plane GaN, namely smooth surface lead to small hysteresis. These results indicate the promising potential of incorporation gate dielectric for future GaN devices.

"Catalytic growth of Carbon Nanotubes (CNT) provides important advantages of controlling their diameters and possibly chirality. Our work involved growing CNT on model and supported catalyst by catalytic decomposition of carbon source such as benzene, methane and propylene. On supported catalyst, iron nitrate was deposited on alumina and reduced to form metallic iron clusters. These were reacted at 700 - 950 C under varying benzene concentrations. Multi Walled CNT (MWNT) grew below 800 C and Single Wall CNT (SWNT) are observed at 850 C and above as confirmed by TEM and Raman. Model catalysts were studied by producing CNT from ferrocene which acted as the carbon and catalyst source on Silica/Si (100). Large yield of MWNT was observed at 900 C. MWNT grew perpendicular to the model support as seen by SEM. In another model catalyst study, iron salt clusters were deposited on silica/Si (100) by spin coating, controlling their diameters by solution concentration and speed of spinning. Agglomeration of clusters at high temperatures produces only MWNT on silica/Si (100). Cluster agglomeration can be reduced with strong support metal interaction such as with alumina. We deposited alumina on silica/Si (100) by atomic layer deposition, with conformal coatings on surface and low relative roughness. Alumina film was stable under reaction temperatures of 900 C. Cluster deposition on alumina by spin coating was difficult because of different surface acidity compared to silica. Clusters on alumina did not agglomerate at high reaction temperatures. We report effect of parameters such as the temperature of reaction, conditions of pretreatment such as reduction and oxidation of catalyst precursor, type of precursor, type of carbon source, and type of support material on growth of CNT. The role of spin coating in controlling the diameter of salt clusters deposited is discussed. We also report deposition of alumina on top of silica/Si (100) by atomic layer deposition and the effect of deposition and calcination temperatures on the alumina film integrity."

La réduction de la taille des circuits CMOS vers des dimensions extrêmement petites est telle que son élément constitutif, le MOSFET à base de Silicium, commence à souffrir d’une faible efficacité de puissance. L’une des alternatives qui ne peut être écartée est le concept du transistor MOSFET à base de matériaux III-V. Ses propriétés de transport extraordinaires, apportées par les matériaux III-V, promettent de réduire la tension d’alimentation des circuits CMOS sans réduire leur performance. Cette transition technologique pourrait aboutir non seulement à des circuits CMOS plus petits, plus écologiques mais aussi à des circuits co-intégrés avec des technologies RF. C’est dans ce contexte que nous présentons, dans ce travail de thèse, la fabrication et la caractérisation des transistors MOSFET Ultra-Thin Body (UTB) à base d’InAs et du transistor FinFET à base d’InAs. La combinaison d’une longueur de grille extrêmement réduite, d’une faible résistance d’accès et d’une mobilité impressionnante dans le canal d’InAs a permis d’obtenir des courants importants (IMAX=2000mA/mm pour LG=25nm). Egalement, l‘utilisation des architectures du canal de type ultra mince et FinFET permet d’obtenir un bon contrôle électrostatique. De plus, une spécificité du procédé technologique présentée dans ce travail est les réalisations des contacts et du canal par une épitaxie par jets moléculaires (MBE) localisée. / Scaling the size of CMOS circuits to extremely small dimensions gets the semiconductor industry to a point where its cornerstone, Silicon-based MOSFET starts to suffer a poor power efficiency. In the quest for alternative solutions cannot be omitted a concept of III-V MOSFET. Its outstanding transport properties hold a promise of reduced CMOS supply voltage without compromising the performance. This can path a way not only to the smaller, greener electronics but also to more co-integrated RF and CMOS electronics. In this context, we present fabrication and characterization of Ultra-Thin body InAs MOSFETs and InAs FinFET. Synergy of a deeply scaled gate length, low access resistance and a high mobility of InAs channel enabled to obtain impressively high drain currents (IMAX=2000mA/mm for LG=25nm). Equally, the introduction of Ultra-Thin body and FinFET channel design provides an improved electrostatic control. A specific feature of the process presented in this work is a fabrication of contacts and channel by localized molecular beam epitaxy MBE epitaxy.

Area selective atomic layer deposition (ASALD) is demonstrated to be a promising route to perform direct patterned deposition. In particular, methods to modify (or mask) the surface and process parameters to perform selective deposition of titanium dioxide have been developed and investigated in detail. Results indicated that self assembled monolayer based masking methodology posses significant limitations due to challenges associated with obtaining defect free monolayer and absence of traditional patterning techniques. On the other hand, polymer films based masking methodology offer a better alternative to perform ASALD. A number of factors that must be considered in designing a successful ASALD process based on polymer films were identified. These include: reactivity of polymer with ALD precursor, diffusion of ALD precursors through polymer mask and remnant precursor content in the polymer film during ALD cycling. Investigations suggested that ALD nucleation can be successfully blocked on polymer films that do not contain direct OH sites in their backbone. It was observed that sorption of water in the polymer film does not pose a serious limitation however; metal precursor diffusion through the polymer mask was identified as a critical parameter in determining the minimum required masking layer thickness for a successful ASALD process. In addition, a novel ASALD-based top surface imaging (TSI) technique has been developed. The ASALD-TSI process has demonstrated sharp contrast (etch barrier deposition vs exposure dose) and therefore offers the potential to overcome many of the challenges experienced with conventional TSI schemes.

Thermische TaN ALD mit den Präkursoren TBTDET und TBTEMT, NH3 als zweiten Reaktanten und Ar als inertes Spülgas ist untersucht worden. Als Messverfahren zur Bewertung ist zeitlich aufgelöste in-situ spektroskopische Ellipsometrie mit einer Datenerfassungsrate von 0,86 Datenpunkte/s, sowie in-vacuo XPS und AFM verwendet worden. Es konnten sehr glatte homogene geschlossene TaN-Dünnschichten mit einem Ta:N-Verhältnis von 0,6, -Verunreinigungen von ca. 5 at.% (TBTDET) bzw. 9 at.% (TBTEMT) und einem GPC von ca. 0,6 nm/Zyklus im linearen Wachstumsbereich hergestellt werden. Eine O3-Vorbehandlung einer SiO2-Oberfläche beschleunigt die initiale Phase der TaN-Abscheidung. Die abgeschiedenen TaN-Schichten zeigen sich sehr reaktiv auf O2. / Thermal ALD with the precursors TBTDET and TBTEMT, NH3 as the second reactant and Ar as inert purging gas was studied. For measuring purposes time-resolved in-situ spectroscopic ellipsometry with an data acquisition rate of 0,86 data points/s, in-vacuo XPS and AFM was used. It was possible to deposit very smmoth homogenous closed TaN thin films with a Ta:N rate of about 0,6, contaminations of 5 at.% (TBTDET) and 9 at.% (TBTEMT), respectively, and a GPC of about 0,6 nm/Zyklus. An O3 pretreatment of a SiO2 surface accelerated the initial phase of the TaN atomic layer deposition (ALD) deposition. These TaN-Schichten were very reactiv against O2.

The continuous scaling of microelectronic devices requires high permittivity (high-k) dielectrics to replace SiO₂ as the gate material. HfO₂ is one of the most promising candidates but the crystallization temperature of amorphous HfO₂ is too low to withstand the fabrication process. To enhance the film thermal stability, HfO₂ is deposited using atomic layer deposition (ALD), and incorporated with various amorphizers, such as La₂O₃, Al₂O₃, and Ta₂O₅. The incorporation is achieved by growing multiple ALD layers of HfO₂ and one ALD layer of MO[subscript x] (M = La, Al, and Ta) alternately (denoted as [xHf + 1M]), and the incorporation concentration can be effectively controlled by the HfO₂-to-MO[subscript x] ALD cycle ratio (the x value). The crystallization temperature of 10 nm HfO₂ increases from 500 °C to 900 °C for 10 nm [xHf + 1M] film, where x = 3, 3, and 1 for M = La, Al, and Ta, respectively. The incorporation of La₂O₃, and Ta₂O₅ will not compromise the dielectric constant of the film because of the high-k nature of La₂O₃, and Ta₂O₅. Angle resolved X-ray photoelectron spectroscopy (AR-XPS) reveals that when the HfO₂-to-MO[scubscript x] ALD cycle ratio is large enough (x > 3 and 4 for La and Al, respectively), periodic structures exist in films grown by this method, which are comprised of repeated M-free HfO₂ ultrathin layers sandwiched between HfM[subscript x]O[scubscript y] layers. Generally, the film thermal stability increases with thinner overall thickness, higher incorporation concentration, and stronger amorphizing capability of the incorporated elements. When the x value is low, the films are more like homogeneous films, with thermal stabilities determined by the film thickness and the amorphizer. When the x value is large enough, the periodically-repeated structure may add an extra factor to stabilize the amorphous phase. For the same incorporation concentration, films with an appropriately high periodicity may have an increased thermal stability. The manner by which the periodic structure and incorporated element affect thermal stability is explored and resolved using nanolaminates comprised of alternating layers of [scubscript y]HfO₂ and [xHf + 1M] × n, where y varied from 2 to 20, x varied from 1 to 2, and n varied from 4 to 22. / text

This thesis investigates surface coatings as xenon diffusion barriers on plastic scintillators. The motivation for the work is improved radioxenon detection systems, used within the verification regime of the Comprehensive Nuclear-Test-Ban Treaty (CTBT). One type of radioxenon detection systems used in this context is the Swedish SAUNA system. This system uses a cylindrical plastic scintillator cell to measure the beta decay from radioxenon isotopes. The detector cell also acts as a container for the xenon sample during the measurement. One problem with this setup is that part of the xenon sample diffuses into the plastic scintillator material during the measurement, resulting in residual activity left in the detector during subsequent measurements. This residual activity is here referred to as the memory effect. It is here proposed, and demonstrated, that it is possible to coat the plastic scintillator material with a transparent oxide coating, working as a xenon diffusion barrier. It is found that a 425 nm Al2O3 coating, deposited with Atomic Layer Deposition, reduces the memory effect by a factor of 1000, compared an uncoated detector. Furthermore, simulations show that the coating might also improve the light collection in the detector. Finally, the energy resolution of a coated detector is studied, and no degradation is observed. The focus of the thesis is measurements of the diffusion barrier properties of Al2O3 films of different thicknesses deposited on plastic scintillators, as well as an evaluation of the expected effect of a coating on the energy resolution of the detector. The latter is studied through light transport simulations. As a final step, a complete coated plastic scintillator cell is evaluated in terms of memory effect, efficiency and energy resolution. In addition, the xenon diffusion process in the plastic material is studied, and molecular dynamics simulations of the Xe-Al2O3 system are performed in order to investigate the reason for the need for a rather thick coating to significantly reduce the memory effect.

The progress of the silicon-based complementary-metal-oxide-semiconductor (CMOS) technology is mainly contributed to the scaling of the individual component. After decades of development, the scaling trend is approaching to its limitation, and there is urgent needs for the innovations of the materials and structures of the MOS devices, in order to postpone the end of the scaling. Atomic layer deposition (ALD) provides precise control of the deposited thin film at the atomic scale, and has wide application not only in the MOS technology, but also in other nanostructures. In this dissertation, I study rapid thermal processing (RTP) treatment of thermally grown SiO2, ALD growth of SiO2, and ALD growth of high-k HfO2 dielectric materials for gate oxides of MOS devices. Using a lateral heating treatment of SiO2, the gate leakage current of SiO2 based MOS capacitors was reduced by 4 order of magnitude, and the underlying mechanism was studied. Ultrathin SiO2 films were grown by ALD, and the electrical properties of the films and the SiO2/Si interface were extensively studied. High quality HfO2 films were grown using ALD on a chemical oxide. The dependence of interfacial quality on the thickness of the chemical oxide was studied. Finally I studied growth of HfO2 on two innovative interfacial layers, an interfacial layer grown by in-situ ALD ozone/water cycle exposure and an interfacial layer of etched thermal and RTP SiO2. The effectiveness of growth of high-quality HfO2 using the two interfacial layers are comparable to that of the chemical oxide. The interfacial properties are studied in details using XPS and ellipsometry.

AlGaN/GaN high electron mobility transistors (HEMTs) have appeared as attractive candidates for high power, high frequency, and high temperature operation at microwave frequencies. In particular, these devices are being considered for use in the area of high RF power for microwave and millimeter wave communications transmitter applications at frequencies greater than 100 GHz and at temperatures greater than about 150 °C. However, there are concerns regarding the reliability of AlGaN/GaN HEMTs. First of all, thermal reliability is the chief concern since high channel temperatures significantly affect the lifetime of the devices. Therefore, it is necessary to find the solutions to decrease the temperature of AlGaN/GaN HEMTs. In this study, we explored the methods to reduce the channel temperature via high thermal conductivity diamond as substrates of GaN. Experimental verification of AlGaN/GaN HEMTs on diamond substrates was performed using micro-Raman spectroscopy, and investigation of the design space for devices was conducted using finite element analysis as well. In addition to the thermal impact on reliability, environmental effects can also play a role in device degradation. Using high density and pinhole free films deposited using atomic layer deposition, we also explore the use of ultra-thin barrier films for the protection of AlGaN/GaN HEMTs in high humidity and high temperature environments. The results show that it is possible to protect the devices from the effects of moisture under high negative gate bias stress testing, whereas devices, which were unprotected, failed under the same bias stress conditions. Thus, the use of the atomic layer deposition (ALD) coatings may provide added benefits in the protection and packaging of AlGaN/GaN HEMTs.