This dissertation is focused on developing a new passband behavioral model in order to account for asymmetric intermodulation distortion resulted from memory effect. First, a measurement setup is prepared to measure the AM/AM, AM/PM distortion, magnitudes and the phases of intermodulation (IMD) and fundamental (FUND) components which are created by the amplifier where phase is calculated only by measuring magnitudes. Then, responses of a sample amplifier are measured for different excitation situations (center frequency and tone spacing are swept). A new modeling technique, namely Odd Order Modeling (OOM), is proposed which has unequal time delay terms. The reason of unequal time delay addition is the change of effective channel length according to the average power passing through that channel. These unequal delays create asymmetry in the IMD components. General Power Series Expansion (GPSE) model is also extracted, OOM and GPSE model performances are compared by using NMSE metric. In order to improve model performance, even order terms with envelope of input are added. It is mathematically proven that even order terms with envelope of the input have contribution to IMD and FUND components&rsquo / . This improved version of modeling is named as Even Order modeling (EOM). EOM model performance is compared with the others&rsquo / performance for two-tone excitation measurement results. It is shown that EOM gives the most accurate result. Model performance is checked for unequal four-tone signal as well. EOM model is applied to baseband DPD circuit after making some modifications. Model linearization performance is compared with the performances of the other memory polynomial modeling techniques.

Conversores analógico-digitais (ADCs) têm papel fundamental na implementação dos sistemas-em-chip, do inglês System-on-Chip (SoC), atuais. Em razão dos requisitos destes sistemas e dos compromissos entre as características fundamentais dos ADCs, como largura de banda, consumo de energia e exatidão, diversas topologias e estratégias para sua implementação em circuitos integrados (CIs) têm sido desenvolvidas através dos tempos. Dentre estas topologias, os conversores sigma-delta (SDC) têm se destacado pela versatilidade, aliada ao baixo consumo e excelente exatidão. Inicialmente desenvolvidos e empregados para a conversão de sinais de baixa frequência e com operação em tempo discreto (DT), esta classe de conversores têm evoluído e nos últimos anos está sendo desenvolvida para operar em tempo contínuo e ser empregada na conversão de sinais com frequências de centenas de kHz a dezenas de MHz. Neste trabalho, os moduladores sigma-delta em tempo contínuo (SDMs-CT) são estudados, visando sua aplicação à conversão analógico-digital (AD). Os SDMs-CT oferecem vantagens significativas sobre seus homólogos em tempo discreto, como menor consumo de energia, maior largura de banda do sinal de entrada e filtro anti-alias, do inglês anti-alias filter (AAF), implícito. Entretanto, os SDMs-CT apresentam limitações adicionais, responsáveis pela degradação de seu desempenho, como os efeitos do jitter do sinal de relógio, o atraso excessivo do laço de realimentação, do inglês Excess Loop Delay (ELD), e as limitações impostas aos integradores analógicos. Após o estudo e análise de SDMs-CT e de suas limitações, foi desenvolvido um modelo comportamental no ambiente Matlab/Simulink R , que permite a simulação do impacto destas limitações no modulador, possibilitando a obtenção de uma estimativa mais aproximada do seu desempenho. Com base nestas simulações foi possível a determinação das especificações mínimas de cada bloco analógico que compõe o modulador (como o slew rate, a frequência de ganho unitário (fu) e o ganho DC dos amplificadores operacionais utilizados nos integradores) e os valores toleráveis de ELD e jitter do sinal de relógio. Adicionalmente, neste trabalho foi desenvolvida uma metodologia para simulação de SDMs-CT compostos por DACs a capacitor chaveado e resistor, do inglês Switched-Capacitor-Resistor (SCR). Com base neste modelo e no estudo das diferentes topologias de SDMs, um circuito foi desenvolvido para aplicação em receptores de RF, sendo do tipo passa-baixas de laço único, do inglês single-loop, single-bit, de terceira ordem, voltado ao baixo consumo de energia. Este circuito foi desenvolvido em tecnologia CMOS IBM de 130 nanômetros, tendo sido enviado para fabricação. Através das simulações pós-leiaute realizadas espera-se que seu desempenho fique próximo ao que tem sido publicado recentemente sobre SDMs-CT passa-baixas de laço único e single-bit. / Analog-to-Digital Converters (ADCs) play a fundamental role in the implementation of current systems-on-chip (SoC). Due to the requirements of these systems and the tradeoffs between the main ADCs characteristics, such as signal bandwidth, power consumption and accuracy, many topologies and strategies for their implementation in integrated circuits (ICs) have been developed through the ages. Among these topologies, the sigmadelta converters (SDC) have highlighted the versatility combined with low power consumption and excellent accuracy. Initially developed and used for the conversion of low frequency signals and operation in the discrete time (DT) domain, this class of converters have been evolved and developed over the past to operate in continuous time domain for the conversion of signals with frequencies of hundreds of kHz up to tens of MHz. In this work, continuous time sigma-delta modulators (CT-SDMs) are studied focusing its application to the analog-to-digital (AD) conversion. CT-SDMs offer significant advantages over their discrete-time counterparts, such as lower power consumption, higher input signal bandwidth and implicit anti-alias filter (AAF). However, CT-SDMs present additional limitations that are responsible for their performance degradation, such as the clock jitter, Excess Loop Delay (ELD) and the limitations imposed on the analog integrators. After the study and analysis of CT-SDMs and their performance limitations, a behavioral model approach was developed in the Matlab/Simulink R environment, which allows the simulation of the limitations impact on the modulator, allowing the obteinment of a more accurate estimate of its performance. Based on these simulations it was possible to determine the minimum specifications for each block that composes the analog modulator (such as slew rate, the unity gain frequency (fu) and the DC gain of the operational amplifiers used in integrators) and tolerable values of ELD and clock jitter. Additionally, it was developed in this work a methodology for simulate CT-SDMs with Switched-Capacitor- Resistor (SCR) DACs that provide exponential waveforms. Based on this model and the study of different SDMs topologies, it was developed a low-pass, single-loop, single-bit, third order circuit focused on low-power intended for application in RF receivers. This circuit was developed in an IBM 130 nanometers CMOS technology, and was send to manufacturing. Based on the post-layout simulations it is expected to have performance close to what has been recently published of low-pass, single-loop, single-bit CT-SDMs.

Conversores analógico-digitais (ADCs) têm papel fundamental na implementação dos sistemas-em-chip, do inglês System-on-Chip (SoC), atuais. Em razão dos requisitos destes sistemas e dos compromissos entre as características fundamentais dos ADCs, como largura de banda, consumo de energia e exatidão, diversas topologias e estratégias para sua implementação em circuitos integrados (CIs) têm sido desenvolvidas através dos tempos. Dentre estas topologias, os conversores sigma-delta (SDC) têm se destacado pela versatilidade, aliada ao baixo consumo e excelente exatidão. Inicialmente desenvolvidos e empregados para a conversão de sinais de baixa frequência e com operação em tempo discreto (DT), esta classe de conversores têm evoluído e nos últimos anos está sendo desenvolvida para operar em tempo contínuo e ser empregada na conversão de sinais com frequências de centenas de kHz a dezenas de MHz. Neste trabalho, os moduladores sigma-delta em tempo contínuo (SDMs-CT) são estudados, visando sua aplicação à conversão analógico-digital (AD). Os SDMs-CT oferecem vantagens significativas sobre seus homólogos em tempo discreto, como menor consumo de energia, maior largura de banda do sinal de entrada e filtro anti-alias, do inglês anti-alias filter (AAF), implícito. Entretanto, os SDMs-CT apresentam limitações adicionais, responsáveis pela degradação de seu desempenho, como os efeitos do jitter do sinal de relógio, o atraso excessivo do laço de realimentação, do inglês Excess Loop Delay (ELD), e as limitações impostas aos integradores analógicos. Após o estudo e análise de SDMs-CT e de suas limitações, foi desenvolvido um modelo comportamental no ambiente Matlab/Simulink R , que permite a simulação do impacto destas limitações no modulador, possibilitando a obtenção de uma estimativa mais aproximada do seu desempenho. Com base nestas simulações foi possível a determinação das especificações mínimas de cada bloco analógico que compõe o modulador (como o slew rate, a frequência de ganho unitário (fu) e o ganho DC dos amplificadores operacionais utilizados nos integradores) e os valores toleráveis de ELD e jitter do sinal de relógio. Adicionalmente, neste trabalho foi desenvolvida uma metodologia para simulação de SDMs-CT compostos por DACs a capacitor chaveado e resistor, do inglês Switched-Capacitor-Resistor (SCR). Com base neste modelo e no estudo das diferentes topologias de SDMs, um circuito foi desenvolvido para aplicação em receptores de RF, sendo do tipo passa-baixas de laço único, do inglês single-loop, single-bit, de terceira ordem, voltado ao baixo consumo de energia. Este circuito foi desenvolvido em tecnologia CMOS IBM de 130 nanômetros, tendo sido enviado para fabricação. Através das simulações pós-leiaute realizadas espera-se que seu desempenho fique próximo ao que tem sido publicado recentemente sobre SDMs-CT passa-baixas de laço único e single-bit. / Analog-to-Digital Converters (ADCs) play a fundamental role in the implementation of current systems-on-chip (SoC). Due to the requirements of these systems and the tradeoffs between the main ADCs characteristics, such as signal bandwidth, power consumption and accuracy, many topologies and strategies for their implementation in integrated circuits (ICs) have been developed through the ages. Among these topologies, the sigmadelta converters (SDC) have highlighted the versatility combined with low power consumption and excellent accuracy. Initially developed and used for the conversion of low frequency signals and operation in the discrete time (DT) domain, this class of converters have been evolved and developed over the past to operate in continuous time domain for the conversion of signals with frequencies of hundreds of kHz up to tens of MHz. In this work, continuous time sigma-delta modulators (CT-SDMs) are studied focusing its application to the analog-to-digital (AD) conversion. CT-SDMs offer significant advantages over their discrete-time counterparts, such as lower power consumption, higher input signal bandwidth and implicit anti-alias filter (AAF). However, CT-SDMs present additional limitations that are responsible for their performance degradation, such as the clock jitter, Excess Loop Delay (ELD) and the limitations imposed on the analog integrators. After the study and analysis of CT-SDMs and their performance limitations, a behavioral model approach was developed in the Matlab/Simulink R environment, which allows the simulation of the limitations impact on the modulator, allowing the obteinment of a more accurate estimate of its performance. Based on these simulations it was possible to determine the minimum specifications for each block that composes the analog modulator (such as slew rate, the unity gain frequency (fu) and the DC gain of the operational amplifiers used in integrators) and tolerable values of ELD and clock jitter. Additionally, it was developed in this work a methodology for simulate CT-SDMs with Switched-Capacitor- Resistor (SCR) DACs that provide exponential waveforms. Based on this model and the study of different SDMs topologies, it was developed a low-pass, single-loop, single-bit, third order circuit focused on low-power intended for application in RF receivers. This circuit was developed in an IBM 130 nanometers CMOS technology, and was send to manufacturing. Based on the post-layout simulations it is expected to have performance close to what has been recently published of low-pass, single-loop, single-bit CT-SDMs.

Conversores analógico-digitais (ADCs) têm papel fundamental na implementação dos sistemas-em-chip, do inglês System-on-Chip (SoC), atuais. Em razão dos requisitos destes sistemas e dos compromissos entre as características fundamentais dos ADCs, como largura de banda, consumo de energia e exatidão, diversas topologias e estratégias para sua implementação em circuitos integrados (CIs) têm sido desenvolvidas através dos tempos. Dentre estas topologias, os conversores sigma-delta (SDC) têm se destacado pela versatilidade, aliada ao baixo consumo e excelente exatidão. Inicialmente desenvolvidos e empregados para a conversão de sinais de baixa frequência e com operação em tempo discreto (DT), esta classe de conversores têm evoluído e nos últimos anos está sendo desenvolvida para operar em tempo contínuo e ser empregada na conversão de sinais com frequências de centenas de kHz a dezenas de MHz. Neste trabalho, os moduladores sigma-delta em tempo contínuo (SDMs-CT) são estudados, visando sua aplicação à conversão analógico-digital (AD). Os SDMs-CT oferecem vantagens significativas sobre seus homólogos em tempo discreto, como menor consumo de energia, maior largura de banda do sinal de entrada e filtro anti-alias, do inglês anti-alias filter (AAF), implícito. Entretanto, os SDMs-CT apresentam limitações adicionais, responsáveis pela degradação de seu desempenho, como os efeitos do jitter do sinal de relógio, o atraso excessivo do laço de realimentação, do inglês Excess Loop Delay (ELD), e as limitações impostas aos integradores analógicos. Após o estudo e análise de SDMs-CT e de suas limitações, foi desenvolvido um modelo comportamental no ambiente Matlab/Simulink R , que permite a simulação do impacto destas limitações no modulador, possibilitando a obtenção de uma estimativa mais aproximada do seu desempenho. Com base nestas simulações foi possível a determinação das especificações mínimas de cada bloco analógico que compõe o modulador (como o slew rate, a frequência de ganho unitário (fu) e o ganho DC dos amplificadores operacionais utilizados nos integradores) e os valores toleráveis de ELD e jitter do sinal de relógio. Adicionalmente, neste trabalho foi desenvolvida uma metodologia para simulação de SDMs-CT compostos por DACs a capacitor chaveado e resistor, do inglês Switched-Capacitor-Resistor (SCR). Com base neste modelo e no estudo das diferentes topologias de SDMs, um circuito foi desenvolvido para aplicação em receptores de RF, sendo do tipo passa-baixas de laço único, do inglês single-loop, single-bit, de terceira ordem, voltado ao baixo consumo de energia. Este circuito foi desenvolvido em tecnologia CMOS IBM de 130 nanômetros, tendo sido enviado para fabricação. Através das simulações pós-leiaute realizadas espera-se que seu desempenho fique próximo ao que tem sido publicado recentemente sobre SDMs-CT passa-baixas de laço único e single-bit. / Analog-to-Digital Converters (ADCs) play a fundamental role in the implementation of current systems-on-chip (SoC). Due to the requirements of these systems and the tradeoffs between the main ADCs characteristics, such as signal bandwidth, power consumption and accuracy, many topologies and strategies for their implementation in integrated circuits (ICs) have been developed through the ages. Among these topologies, the sigmadelta converters (SDC) have highlighted the versatility combined with low power consumption and excellent accuracy. Initially developed and used for the conversion of low frequency signals and operation in the discrete time (DT) domain, this class of converters have been evolved and developed over the past to operate in continuous time domain for the conversion of signals with frequencies of hundreds of kHz up to tens of MHz. In this work, continuous time sigma-delta modulators (CT-SDMs) are studied focusing its application to the analog-to-digital (AD) conversion. CT-SDMs offer significant advantages over their discrete-time counterparts, such as lower power consumption, higher input signal bandwidth and implicit anti-alias filter (AAF). However, CT-SDMs present additional limitations that are responsible for their performance degradation, such as the clock jitter, Excess Loop Delay (ELD) and the limitations imposed on the analog integrators. After the study and analysis of CT-SDMs and their performance limitations, a behavioral model approach was developed in the Matlab/Simulink R environment, which allows the simulation of the limitations impact on the modulator, allowing the obteinment of a more accurate estimate of its performance. Based on these simulations it was possible to determine the minimum specifications for each block that composes the analog modulator (such as slew rate, the unity gain frequency (fu) and the DC gain of the operational amplifiers used in integrators) and tolerable values of ELD and clock jitter. Additionally, it was developed in this work a methodology for simulate CT-SDMs with Switched-Capacitor- Resistor (SCR) DACs that provide exponential waveforms. Based on this model and the study of different SDMs topologies, it was developed a low-pass, single-loop, single-bit, third order circuit focused on low-power intended for application in RF receivers. This circuit was developed in an IBM 130 nanometers CMOS technology, and was send to manufacturing. Based on the post-layout simulations it is expected to have performance close to what has been recently published of low-pass, single-loop, single-bit CT-SDMs.

No description available.

No description available.

Cette thèse porte sur la caractérisation, la modélisation et l'analyse des phénomènes de «Pulling» et de «Pushing» dans les systèmes de boucles à verrouillage de phase (PLL), utilisant une approche globale où les effets de couplages électromagnétiques aux différents niveaux d'intégration (niveau puce, niveau assemblage, niveau report sur PCB) sont pris en compte de manière distribuée. L'approche de modélisation adopte une méthodologie hybride où l'analyse des couplages électromagnétiques combinée à des schémas équivalents large-bande (compatibles avec les modèles de composants actifs disponibles dans les librairies) est couplée à des représentations comportementales dynamiques. Les représentations comportementales développées permettent de capturer des effets de non-linéarités tant au niveau composant (caractéristique non-linéaire des Varicap en fonction des tensions de contrôle) qu'au niveau block de fonction (gain KVCO non uniforme de l'oscillateur contrôlé en tension (VCO) en fonction de la fréquence).Cette méthodologie hybride permet l'évaluation d'effets compétitifs résultant de phénomènes de «pulling» et de «Pushing» au niveau de la puce (influence de la PLL, effets de l'amplificateur de puissance, intégrité des alimentations ou distribution des références de masse, etc.) , et des distorsions induites par des éléments extérieurs à la puce (exemple de composants sur PCB : Filtre SAW, capacités de découplages, réseaux d'adaptation).L'approche proposée est utilisée pour l'étude et la conception de deux types de circuits développés par NXP-semi-conducteurs pour des applications liées à la sécurité automobile (PLL fonctionnant aux alentours de 1.736GHz) et à la réception satellitaire (PLL de faible consommation fonctionnant à 9.75/10.6 GHz pour les circuits LNB).Les résultats de modélisation obtenus sont validés par corrélations avec les données expérimentales et par comparaison avec les résultats obtenus de différents outils (ADS Harmonic- Balance/Transient de Agilent, Spectre de Cadence / This thesis work focuses on characterization, modeling and analysis of «Pulling» and «Pushing» phenomena in Phase Locked Loops (PLL) based on a global approach where distributed effects of electromagnetic couplings at different integration levels (chip-level, assembly-level, board or PCB-level) are taken into account. The modeling approach adopts a hybrid methodology where the analysis of electromagnetic couplings combined with broadband equivalent circuit synthesis (compatible with library models of active components) is coupled with dynamic behavioral representations. The derived behavioral representations properly capture the effects of nonlinearities both at component scale (non-linear characteristic of varicap as function of control voltages) and at function block level (non-uniform gain KVCO of VCO circuits depending on frequency).The hybrid methodology renders possible the assessment of competitive effects resulting from «Pulling» and «Pushing» phenomena at chip level (influence of the PLL, effects of the power amplifier, power integrity, or ground reference distribution, etc..), and the distortions induced by components external to the chip at package and board levels (such as components on PCB: SAW filters, decoupling capacitors, matching networks).The proposed approach is used for the study and design of two types of circuits developed by NXP- Semiconductors, for applications related to automotive security and immobilization (an RF low power transceiver Integrated Circuit (PLL running around 1.763GHz), and to satellite receiver (PLL operating at low power for LNB circuits working at 9.75/10.6 GHz).The obtained modeling results are validated by correlation with experimental data and by comparison with different time-domain and frequency-domain simulation tools results (ADS-Harmonic Balance, ADS-Shooting solutions, Cadence-Spectre)

The advent of deep submicron technology coupled with ever increasing demands from the customer for more functionality on a compact silicon real estate has led to a proliferation of highly complex integrated RF system-on-chip (SoC) and system-on-insulator (SoI) solutions. The use of scaled CMOS technologies for high frequency wireless applications is posing daunting technological challenges both in design and manufacturing test. To ensure market success, manufacturers need to ensure the quality of these advanced RF devices by subjecting them to a conventional set of production test routines that are both time consuming and expensive. Typically the devices are tested for parametric specifications such as gain, linearity metrics, quadrature mismatches, phase noise, noise figure (NF) and end-to-end system level specifications such as EVM (error vector magnitude), BER (bit-error-rate) etc. Due to the reduced visibility imposed by high levels of integration, testing for parametric specifications are becoming more and more complex. To offset the yield loss resulting from process variability effects and reliability issues in RF circuits, the use of self-healing/self-tuning mechanisms will be imperative. Such self-healing is typically implemented as a test/self-test and self-tune procedure and is applied post-manufacture. To enable this, simple test routines that can accurately diagnose complex performance parameters of the RF circuits need to be developed first. After diagnosing the performance of a complex RF system appropriate compensation techniques need to be developed to increase or restore the system performance. Moreover, the test, diagnosis and compensation approach should be low-cost with minimal hardware and software overhead to ensure that the final product is economically viable for the manufacturer. The main components of the thesis are as follows: 1) Low-cost specification testing of advanced radio frequency front-ends: Methodologies are developed to address the issue of test cost and test time associated with conventional production testing of advanced RF front-ends. The developed methodologies are amenable for performing self healing of RF SoCs. Test generation algorithms are developed to perform alternate test stimulus generation that includes the artifacts of test signal path such as response capture accuracy, load-board DfT etc. A novel cross loop-back methodology is developed to perform low cost system level specification testing of multi-band RF transceivers. A novel low-cost EVM testing approach is developed for production testing of wireless 802.11 OFDM front-ends. A signal transformation based model extraction technique is developed to compute multiple RF system level specifications of wireless front-ends from a single data capture. The developed techniques are low-cost and facilitate a reduction in the overall contribution of test cost towards the manufacturing cost of advanced wireless products. 2)Analog tuning methodologies for compensating wireless RF front ends: Methodologies for performing low-cost self tuning of multiple impairments of wireless RF devices are developed. This research considers for the first time, multiple analog tuning parameters of a complete RF transceiver system (transmitter and receiver) for tuning purposes. The developed techniques are demonstrated on hardware components and behavioral models to improve the overall yield of integrated RF SoCs.

Pour répondre au besoin de 14 millions de personnes, dont près de 10% vit en situation de perte d'autonomie ou de grande dépendance, notre société va devoir trouver rapidement des solutions de prise en charge. La télémédecine, et plus particulièrement la télésurveillance médicale à domicile, constitue aujourd'hui une solution pour pallier le manque de professionnels de santé face au fort accroissement de la population âgée en Europe. Dans ce contexte, nous nous intéressons au HIS -« Habitat intelligent pour la Santé ». Le travail de la thèse a été de développer un outil informatique de simulation des activités (déplacements) d'une personne suivie à l'intérieur d'un HIS. La création d'un simulateur est vue comme un moyen d'améliorer les performances et la qualité de service de la télésurveillance à domicile. Nous avons testé plusieurs méthodes de simulations (réseaux de neurones artificiel, chaines de Markov, urnes de Polya) et retenu les chaines de Markov cachées (HMM). Le simulateur a été implémenté en MATLAB à partir de la modélisation de données réelles provenant d'HIS occupés par des personnes âgées, dont certaines vivent seules. La validation des données produites par le simulateur a été effectuée par mesure de corrélation surfacique entre les données réelles et les données simulées. Ce travail ouvre la voie à la production de données d'activités simulées suivant un profil type de patient, sans passer par de longues et couteuses expérimentations de terrain. / Our societies will have to meet rapidly the needs of 14 million people who often live in situations of loss of autonomy or dependence with quick solutions supported. Telemedicine, and especially the home telemonitoring, is now a solution to alleviate the shortage of health professionals confronted to the great increase in population in Europe. In this context, we investigated the HIS "Smart Habitat for Health". The work of this thesis was to develop a digital simulator of activities (displacements) of a person followed within a HIS. The creation of a simulator is seen as a solution to improve performance and quality of service of home telemonitoring. We tested several methods of simulation (artificial neural networks, Markov chains, Polya urns) and retained the hidden Markov (HMM). This simulator was implemented under MATLAB, after the modeling of data collected in HIS occupied by elderly people, some living alone. Validation of data generated by the simulator was performed by measuring surface correlation between real and simulated data. This work paves the way for production activity data simulated according to a profile type of patient, without going through lengthy and costly field experiments.

A Modelagem Orientada a Objetos (MOO) é o processo de construção de modelos de sistemas através da identificação e definição de um conjunto de objetos relacionados, que comportam-se e colaboram entre si conforme os requisitos estabelecidos para o sistema. Esta definição inclui os três aspectos ortogonais, ou dimensões, deste tipo de modelagem: a dimensão estrutural dos objetos, a dimensão dinâmica do comportamento e a dimensão funcional dos requisitos. Conforme a importância relativa dada a cada uma destas dimensões, podem ser definidas três estratégias possíveis para conduzir a MOO. Estas estratégias são as dirigidas por dados, por comportamento e por processos. A estratégia dirigida por processos já esta superada. Atualmente, a estratégia dirigida por dados domina na maioria das técnicas de MOO. A estratégia dirigida por comportamento propõe que a estrutura dos objetos em um sistema pode ser determinada a partir do comportamento externo e interno que o sistema deve apresentar. Esta idéia é interessante, porque permite introduzir tardiamente o encapsulamento na MOO. Conforme é argumentado neste trabalho, as vantagens atribuídas a orientação a objetos são de implementação, isto é, a decisão de orientar ou não a objetos é, na realidade, uma decisão de design. Ao introduzir o encapsulamento na modelagem inicial do sistema, ganha-se o benefício da continuidade estrutural ao custo de colocar a MOO mais perto do design. Neste contexto, este trabalho apresenta um processo de modelagem conceitual de sistemas do ponto de vista comportamental que introduz tardiamente o encapsulamento da orientação a objetos como primeiro passo de design. Em outras palavras, é proposta uma técnica de modelagem sob uma estratégia dirigida por comportamento (privilegiando, assim, o aspecto dinâmico dos sistemas) com o suficiente poder de expressão para, ao mesmo tempo, permitir a modelagem de sistemas de informação no nível conceitual e derivar dos modelos dinâmicos obtidos uma representação estrutural orientada a objetos. 0 sistema, na concepção desta proposta, é composto por um conjunto de processos concorrentes, cada um dos quais recebe um estimulo do ambiente, realiza um tratamento especifico sobre ele e gera para o ambiente uma resposta. Os estímulos externos são decompostos em conjuntos de eventos concorrentes tratados no interior do processo. As ações realizadas no interior do mesmo são compostas nas respostas geradas para o exterior. Os processos são modelados comportamentalmente, utilizando o formalismo proposto High-Level Statecharts (HLS). HLS é uma extensão dos statecharts de Harel. As principais extensões propostas são a introdução de estados "parametrizados" usando variáveis e a representação genérica de conjuntos de estados concorrentes e exclusivos. 0 modelo de processos e desintegrado em unidades de comportamento que tratam das mesmas variáveis. Estas unidades são integradas em um modelo de ciclos de vida para estas variáveis. Finalmente, apos a aplicação da técnica de modelagem conceitual, e obtido um modelo estrutural orientado a objetos. Este modelo e derivado utilizando unicamente informações contidas nos modelos dinâmicos gerados no processo da técnica proposta. No modelo estrutural são identificadas classes, objetos, atributos, associações estáticas, hierarquias de herança e operações. Todo o processo e exemplificado utilizando o problema padrão de preparação de congressos da IFIP. / Object-Oriented Modeling (OOM) is the process of construction of systems models, through an identification and definition of a set of relating objects. These objects have a collaborative behavior according to the system requirements previously defined. This definition includes three modeling aspects or dimensions: object structural dimension, behavior dynamic dimension and requirements functional dimension. Depending on a relative importance of each dimension, three possible strategies to drive OOM are defined. The strategies are: data-driven, behavior-driven and process-driven. Process-driven strategy is obsolete. Nowadays, data-driven is the dominant strategy in the world of OOM techniques. Behavior-driven strategy suggests both internal and external system behaviors define its object structure. This idea is attractive because it allows a late encapsulation in the OOM. As explained in this work, the main advantage to use object-orientation is for implementation. So, to object-orient or not to object-orient is a design decision. If encapsulation is introduced in the very beginning of systems modeling, the structural continuity is achieved at the cost of pulling OOM closer to design. In this context, the work presents a process of systems conceptual modeling using a behavioral point of view. This process introduces object-oriented encapsulation lately as a first step in the design phase. In other words, this work is a proposal of a modeling technique under a behavior-driven strategy (focusing the dynamic aspect of the systems) with enough expression power to model information systems at conceptual level and, at the same time, to derive of an object-oriented structural representation from the dynamic models. As conceived in the proposal, a system is composed by a set of concurrent processes. Each process receives a stimuli from the environment, makes a specific treatment on it and generates a response to the environment. The external stimuli is decomposed into a set of concurrent events which are internally handled by the process. Actions internally performed by the process are composed into a response which is sent outside the process. Processes are behaviorally modeled using a proposed formalism called High-Level Statecharts (HLS). HLS is a extension of Harel's statecharts. The main extensions proposed are parameterized states using variables and generic representation of concurrent and exclusive sets of states. Process model is disintegrated into behavior units handling the same variables. The units are integrated into a life cycle model for these variables. Finally, after the modeling technique has been applied, an object-oriented structural model is obtained. This model is derived exclusively using information from the dynamic models constructed during the modeling process. Classes, objects, attributes, static associations, inheritance hierarchies and operations in the structural model are identified. Examples used in all the modeling process are taken from the standard problem of IFIP conference.